Initial import of onewire-to-usb bridge

diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..05a3fb1
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,108 @@
+#
+#  There exist several targets which are by default empty and which can be 
+#  used for execution of your targets. These targets are usually executed 
+#  before and after some main targets. They are: 
+#
+#     .build-pre:              called before 'build' target
+#     .build-post:             called after 'build' target
+#     .clean-pre:              called before 'clean' target
+#     .clean-post:             called after 'clean' target
+#     .clobber-pre:            called before 'clobber' target
+#     .clobber-post:           called after 'clobber' target
+#     .all-pre:                called before 'all' target
+#     .all-post:               called after 'all' target
+#     .help-pre:               called before 'help' target
+#     .help-post:              called after 'help' target
+#
+#  Targets beginning with '.' are not intended to be called on their own.
+#
+#  Main targets can be executed directly, and they are:
+#  
+#     build                    build a specific configuration
+#     clean                    remove built files from a configuration
+#     clobber                  remove all built files
+#     all                      build all configurations
+#     help                     print help mesage
+#  
+#  Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and
+#  .help-impl are implemented in nbproject/makefile-impl.mk.
+#
+#  Available make variables:
+#
+#     CND_BASEDIR                base directory for relative paths
+#     CND_DISTDIR                default top distribution directory (build artifacts)
+#     CND_BUILDDIR               default top build directory (object files, ...)
+#     CONF                       name of current configuration
+#     CND_ARTIFACT_DIR_${CONF}   directory of build artifact (current configuration)
+#     CND_ARTIFACT_NAME_${CONF}  name of build artifact (current configuration)
+#     CND_ARTIFACT_PATH_${CONF}  path to build artifact (current configuration)
+#     CND_PACKAGE_DIR_${CONF}    directory of package (current configuration)
+#     CND_PACKAGE_NAME_${CONF}   name of package (current configuration)
+#     CND_PACKAGE_PATH_${CONF}   path to package (current configuration)
+#
+# NOCDDL
+
+
+# Environment 
+MKDIR=mkdir
+CP=cp
+CCADMIN=CCadmin
+RANLIB=ranlib
+
+
+# build
+build: .build-post
+
+.build-pre:
+# Add your pre 'build' code here...
+
+.build-post: .build-impl
+# Add your post 'build' code here...
+
+
+# clean
+clean: .clean-post
+
+.clean-pre:
+# Add your pre 'clean' code here...
+
+.clean-post: .clean-impl
+# Add your post 'clean' code here...
+
+
+# clobber
+clobber: .clobber-post
+
+.clobber-pre:
+# Add your pre 'clobber' code here...
+
+.clobber-post: .clobber-impl
+# Add your post 'clobber' code here...
+
+
+# all
+all: .all-post
+
+.all-pre:
+# Add your pre 'all' code here...
+
+.all-post: .all-impl
+# Add your post 'all' code here...
+
+
+# help
+help: .help-post
+
+.help-pre:
+# Add your pre 'help' code here...
+
+.help-post: .help-impl
+# Add your post 'help' code here...
+
+
+
+# include project implementation makefile
+include nbproject/Makefile-impl.mk
+
+# include project make variables
+include nbproject/Makefile-variables.mk

diff --git a/build/XC8_12F1822/production/configuration_bits.p1 b/build/XC8_12F1822/production/configuration_bits.p1
new file mode 100644 (file)
index 0000000..fd2cfed
--- /dev/null
+++ b/build/XC8_12F1822/production/configuration_bits.p1
@@ -0,0 +1,2120 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[; ;pic12f1822.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[; ;pic12f1822.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1822.h: 49: typedef union {
+[; ;pic12f1822.h: 50: struct {
+[; ;pic12f1822.h: 51: unsigned INDF0 :8;
+[; ;pic12f1822.h: 52: };
+[; ;pic12f1822.h: 53: } INDF0bits_t;
+[; ;pic12f1822.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1822.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1822.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1822.h: 68: typedef union {
+[; ;pic12f1822.h: 69: struct {
+[; ;pic12f1822.h: 70: unsigned INDF1 :8;
+[; ;pic12f1822.h: 71: };
+[; ;pic12f1822.h: 72: } INDF1bits_t;
+[; ;pic12f1822.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1822.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1822.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1822.h: 87: typedef union {
+[; ;pic12f1822.h: 88: struct {
+[; ;pic12f1822.h: 89: unsigned PCL :8;
+[; ;pic12f1822.h: 90: };
+[; ;pic12f1822.h: 91: } PCLbits_t;
+[; ;pic12f1822.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1822.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1822.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1822.h: 106: typedef union {
+[; ;pic12f1822.h: 107: struct {
+[; ;pic12f1822.h: 108: unsigned C :1;
+[; ;pic12f1822.h: 109: unsigned DC :1;
+[; ;pic12f1822.h: 110: unsigned Z :1;
+[; ;pic12f1822.h: 111: unsigned nPD :1;
+[; ;pic12f1822.h: 112: unsigned nTO :1;
+[; ;pic12f1822.h: 113: };
+[; ;pic12f1822.h: 114: struct {
+[; ;pic12f1822.h: 115: unsigned CARRY :1;
+[; ;pic12f1822.h: 116: };
+[; ;pic12f1822.h: 117: struct {
+[; ;pic12f1822.h: 118: unsigned :2;
+[; ;pic12f1822.h: 119: unsigned ZERO :1;
+[; ;pic12f1822.h: 120: };
+[; ;pic12f1822.h: 121: } STATUSbits_t;
+[; ;pic12f1822.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1822.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1822.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1822.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1822.h: 169: typedef union {
+[; ;pic12f1822.h: 170: struct {
+[; ;pic12f1822.h: 171: unsigned FSR0L :8;
+[; ;pic12f1822.h: 172: };
+[; ;pic12f1822.h: 173: } FSR0Lbits_t;
+[; ;pic12f1822.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1822.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1822.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1822.h: 188: typedef union {
+[; ;pic12f1822.h: 189: struct {
+[; ;pic12f1822.h: 190: unsigned FSR0H :8;
+[; ;pic12f1822.h: 191: };
+[; ;pic12f1822.h: 192: } FSR0Hbits_t;
+[; ;pic12f1822.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1822.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1822.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1822.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1822.h: 210: typedef union {
+[; ;pic12f1822.h: 211: struct {
+[; ;pic12f1822.h: 212: unsigned FSR1L :8;
+[; ;pic12f1822.h: 213: };
+[; ;pic12f1822.h: 214: } FSR1Lbits_t;
+[; ;pic12f1822.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1822.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1822.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1822.h: 229: typedef union {
+[; ;pic12f1822.h: 230: struct {
+[; ;pic12f1822.h: 231: unsigned FSR1H :8;
+[; ;pic12f1822.h: 232: };
+[; ;pic12f1822.h: 233: } FSR1Hbits_t;
+[; ;pic12f1822.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1822.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1822.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1822.h: 248: typedef union {
+[; ;pic12f1822.h: 249: struct {
+[; ;pic12f1822.h: 250: unsigned BSR0 :1;
+[; ;pic12f1822.h: 251: unsigned BSR1 :1;
+[; ;pic12f1822.h: 252: unsigned BSR2 :1;
+[; ;pic12f1822.h: 253: unsigned BSR3 :1;
+[; ;pic12f1822.h: 254: unsigned BSR4 :1;
+[; ;pic12f1822.h: 255: };
+[; ;pic12f1822.h: 256: struct {
+[; ;pic12f1822.h: 257: unsigned BSR :5;
+[; ;pic12f1822.h: 258: };
+[; ;pic12f1822.h: 259: } BSRbits_t;
+[; ;pic12f1822.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1822.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1822.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1822.h: 299: typedef union {
+[; ;pic12f1822.h: 300: struct {
+[; ;pic12f1822.h: 301: unsigned WREG0 :8;
+[; ;pic12f1822.h: 302: };
+[; ;pic12f1822.h: 303: } WREGbits_t;
+[; ;pic12f1822.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1822.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1822.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1822.h: 318: typedef union {
+[; ;pic12f1822.h: 319: struct {
+[; ;pic12f1822.h: 320: unsigned PCLATH :7;
+[; ;pic12f1822.h: 321: };
+[; ;pic12f1822.h: 322: } PCLATHbits_t;
+[; ;pic12f1822.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1822.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1822.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1822.h: 337: typedef union {
+[; ;pic12f1822.h: 338: struct {
+[; ;pic12f1822.h: 339: unsigned IOCIF :1;
+[; ;pic12f1822.h: 340: unsigned INTF :1;
+[; ;pic12f1822.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1822.h: 342: unsigned IOCIE :1;
+[; ;pic12f1822.h: 343: unsigned INTE :1;
+[; ;pic12f1822.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1822.h: 345: unsigned PEIE :1;
+[; ;pic12f1822.h: 346: unsigned GIE :1;
+[; ;pic12f1822.h: 347: };
+[; ;pic12f1822.h: 348: struct {
+[; ;pic12f1822.h: 349: unsigned :2;
+[; ;pic12f1822.h: 350: unsigned T0IF :1;
+[; ;pic12f1822.h: 351: unsigned :2;
+[; ;pic12f1822.h: 352: unsigned T0IE :1;
+[; ;pic12f1822.h: 353: };
+[; ;pic12f1822.h: 354: } INTCONbits_t;
+[; ;pic12f1822.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1822.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1822.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1822.h: 414: typedef union {
+[; ;pic12f1822.h: 415: struct {
+[; ;pic12f1822.h: 416: unsigned RA0 :1;
+[; ;pic12f1822.h: 417: unsigned RA1 :1;
+[; ;pic12f1822.h: 418: unsigned RA2 :1;
+[; ;pic12f1822.h: 419: unsigned RA3 :1;
+[; ;pic12f1822.h: 420: unsigned RA4 :1;
+[; ;pic12f1822.h: 421: unsigned RA5 :1;
+[; ;pic12f1822.h: 422: };
+[; ;pic12f1822.h: 423: struct {
+[; ;pic12f1822.h: 424: unsigned AN0 :1;
+[; ;pic12f1822.h: 425: unsigned AN1 :1;
+[; ;pic12f1822.h: 426: unsigned AN2 :1;
+[; ;pic12f1822.h: 427: unsigned :1;
+[; ;pic12f1822.h: 428: unsigned AN3 :1;
+[; ;pic12f1822.h: 429: };
+[; ;pic12f1822.h: 430: struct {
+[; ;pic12f1822.h: 431: unsigned CPS0 :1;
+[; ;pic12f1822.h: 432: unsigned CPS1 :1;
+[; ;pic12f1822.h: 433: unsigned CPS2 :1;
+[; ;pic12f1822.h: 434: unsigned :1;
+[; ;pic12f1822.h: 435: unsigned CPS3 :1;
+[; ;pic12f1822.h: 436: };
+[; ;pic12f1822.h: 437: struct {
+[; ;pic12f1822.h: 438: unsigned C1INP :1;
+[; ;pic12f1822.h: 439: unsigned C1IN0N :1;
+[; ;pic12f1822.h: 440: unsigned C1OUT :1;
+[; ;pic12f1822.h: 441: unsigned :1;
+[; ;pic12f1822.h: 442: unsigned C1IN1N :1;
+[; ;pic12f1822.h: 443: };
+[; ;pic12f1822.h: 444: struct {
+[; ;pic12f1822.h: 445: unsigned DACOUT :1;
+[; ;pic12f1822.h: 446: unsigned SRI :1;
+[; ;pic12f1822.h: 447: unsigned SRQ :1;
+[; ;pic12f1822.h: 448: unsigned :2;
+[; ;pic12f1822.h: 449: unsigned SRNQ :1;
+[; ;pic12f1822.h: 450: };
+[; ;pic12f1822.h: 451: struct {
+[; ;pic12f1822.h: 452: unsigned :1;
+[; ;pic12f1822.h: 453: unsigned SCK :1;
+[; ;pic12f1822.h: 454: unsigned T0CKI :1;
+[; ;pic12f1822.h: 455: unsigned :1;
+[; ;pic12f1822.h: 456: unsigned T1OSO :1;
+[; ;pic12f1822.h: 457: unsigned T1CKI :1;
+[; ;pic12f1822.h: 458: };
+[; ;pic12f1822.h: 459: struct {
+[; ;pic12f1822.h: 460: unsigned :1;
+[; ;pic12f1822.h: 461: unsigned SCL :1;
+[; ;pic12f1822.h: 462: unsigned SDA :1;
+[; ;pic12f1822.h: 463: unsigned nMCLR :1;
+[; ;pic12f1822.h: 464: unsigned CLKR :1;
+[; ;pic12f1822.h: 465: unsigned T1OSI :1;
+[; ;pic12f1822.h: 466: };
+[; ;pic12f1822.h: 467: struct {
+[; ;pic12f1822.h: 468: unsigned MDOUT :1;
+[; ;pic12f1822.h: 469: unsigned MDMIN :1;
+[; ;pic12f1822.h: 470: unsigned MDCIN1 :1;
+[; ;pic12f1822.h: 471: unsigned :1;
+[; ;pic12f1822.h: 472: unsigned MDCIN2 :1;
+[; ;pic12f1822.h: 473: };
+[; ;pic12f1822.h: 474: struct {
+[; ;pic12f1822.h: 475: unsigned :2;
+[; ;pic12f1822.h: 476: unsigned SDI :1;
+[; ;pic12f1822.h: 477: unsigned :1;
+[; ;pic12f1822.h: 478: unsigned OSC2 :1;
+[; ;pic12f1822.h: 479: unsigned OSC1 :1;
+[; ;pic12f1822.h: 480: };
+[; ;pic12f1822.h: 481: struct {
+[; ;pic12f1822.h: 482: unsigned :2;
+[; ;pic12f1822.h: 483: unsigned FLT0 :1;
+[; ;pic12f1822.h: 484: unsigned :1;
+[; ;pic12f1822.h: 485: unsigned CLKOUT :1;
+[; ;pic12f1822.h: 486: unsigned CLKIN :1;
+[; ;pic12f1822.h: 487: };
+[; ;pic12f1822.h: 488: } PORTAbits_t;
+[; ;pic12f1822.h: 489: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1822.h: 698: extern volatile unsigned char PIR1 @ 0x011;
+"700
+[; ;pic12f1822.h: 700: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1822.h: 703: typedef union {
+[; ;pic12f1822.h: 704: struct {
+[; ;pic12f1822.h: 705: unsigned TMR1IF :1;
+[; ;pic12f1822.h: 706: unsigned TMR2IF :1;
+[; ;pic12f1822.h: 707: unsigned CCP1IF :1;
+[; ;pic12f1822.h: 708: unsigned SSP1IF :1;
+[; ;pic12f1822.h: 709: unsigned TXIF :1;
+[; ;pic12f1822.h: 710: unsigned RCIF :1;
+[; ;pic12f1822.h: 711: unsigned ADIF :1;
+[; ;pic12f1822.h: 712: unsigned TMR1GIF :1;
+[; ;pic12f1822.h: 713: };
+[; ;pic12f1822.h: 714: } PIR1bits_t;
+[; ;pic12f1822.h: 715: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1822.h: 759: extern volatile unsigned char PIR2 @ 0x012;
+"761
+[; ;pic12f1822.h: 761: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1822.h: 764: typedef union {
+[; ;pic12f1822.h: 765: struct {
+[; ;pic12f1822.h: 766: unsigned :3;
+[; ;pic12f1822.h: 767: unsigned BCL1IF :1;
+[; ;pic12f1822.h: 768: unsigned EEIF :1;
+[; ;pic12f1822.h: 769: unsigned C1IF :1;
+[; ;pic12f1822.h: 770: unsigned :1;
+[; ;pic12f1822.h: 771: unsigned OSFIF :1;
+[; ;pic12f1822.h: 772: };
+[; ;pic12f1822.h: 773: } PIR2bits_t;
+[; ;pic12f1822.h: 774: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1822.h: 798: extern volatile unsigned char TMR0 @ 0x015;
+"800
+[; ;pic12f1822.h: 800: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1822.h: 803: typedef union {
+[; ;pic12f1822.h: 804: struct {
+[; ;pic12f1822.h: 805: unsigned TMR0 :8;
+[; ;pic12f1822.h: 806: };
+[; ;pic12f1822.h: 807: } TMR0bits_t;
+[; ;pic12f1822.h: 808: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1822.h: 817: extern volatile unsigned short TMR1 @ 0x016;
+"819
+[; ;pic12f1822.h: 819: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1822.h: 823: extern volatile unsigned char TMR1L @ 0x016;
+"825
+[; ;pic12f1822.h: 825: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1822.h: 828: typedef union {
+[; ;pic12f1822.h: 829: struct {
+[; ;pic12f1822.h: 830: unsigned TMR1L :8;
+[; ;pic12f1822.h: 831: };
+[; ;pic12f1822.h: 832: } TMR1Lbits_t;
+[; ;pic12f1822.h: 833: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1822.h: 842: extern volatile unsigned char TMR1H @ 0x017;
+"844
+[; ;pic12f1822.h: 844: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1822.h: 847: typedef union {
+[; ;pic12f1822.h: 848: struct {
+[; ;pic12f1822.h: 849: unsigned TMR1H :8;
+[; ;pic12f1822.h: 850: };
+[; ;pic12f1822.h: 851: } TMR1Hbits_t;
+[; ;pic12f1822.h: 852: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1822.h: 861: extern volatile unsigned char T1CON @ 0x018;
+"863
+[; ;pic12f1822.h: 863: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1822.h: 866: typedef union {
+[; ;pic12f1822.h: 867: struct {
+[; ;pic12f1822.h: 868: unsigned TMR1ON :1;
+[; ;pic12f1822.h: 869: unsigned :1;
+[; ;pic12f1822.h: 870: unsigned nT1SYNC :1;
+[; ;pic12f1822.h: 871: unsigned T1OSCEN :1;
+[; ;pic12f1822.h: 872: unsigned T1CKPS0 :1;
+[; ;pic12f1822.h: 873: unsigned T1CKPS1 :1;
+[; ;pic12f1822.h: 874: unsigned TMR1CS0 :1;
+[; ;pic12f1822.h: 875: unsigned TMR1CS1 :1;
+[; ;pic12f1822.h: 876: };
+[; ;pic12f1822.h: 877: struct {
+[; ;pic12f1822.h: 878: unsigned :4;
+[; ;pic12f1822.h: 879: unsigned T1CKPS :2;
+[; ;pic12f1822.h: 880: unsigned TMR1CS :2;
+[; ;pic12f1822.h: 881: };
+[; ;pic12f1822.h: 882: } T1CONbits_t;
+[; ;pic12f1822.h: 883: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1822.h: 932: extern volatile unsigned char T1GCON @ 0x019;
+"934
+[; ;pic12f1822.h: 934: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1822.h: 937: typedef union {
+[; ;pic12f1822.h: 938: struct {
+[; ;pic12f1822.h: 939: unsigned T1GSS0 :1;
+[; ;pic12f1822.h: 940: unsigned T1GSS1 :1;
+[; ;pic12f1822.h: 941: unsigned T1GVAL :1;
+[; ;pic12f1822.h: 942: unsigned T1GGO_nDONE :1;
+[; ;pic12f1822.h: 943: unsigned T1GSPM :1;
+[; ;pic12f1822.h: 944: unsigned T1GTM :1;
+[; ;pic12f1822.h: 945: unsigned T1GPOL :1;
+[; ;pic12f1822.h: 946: unsigned TMR1GE :1;
+[; ;pic12f1822.h: 947: };
+[; ;pic12f1822.h: 948: struct {
+[; ;pic12f1822.h: 949: unsigned T1GSS :2;
+[; ;pic12f1822.h: 950: unsigned :1;
+[; ;pic12f1822.h: 951: unsigned T1GGO :1;
+[; ;pic12f1822.h: 952: };
+[; ;pic12f1822.h: 953: } T1GCONbits_t;
+[; ;pic12f1822.h: 954: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1822.h: 1008: extern volatile unsigned char TMR2 @ 0x01A;
+"1010
+[; ;pic12f1822.h: 1010: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1822.h: 1013: typedef union {
+[; ;pic12f1822.h: 1014: struct {
+[; ;pic12f1822.h: 1015: unsigned TMR2 :8;
+[; ;pic12f1822.h: 1016: };
+[; ;pic12f1822.h: 1017: } TMR2bits_t;
+[; ;pic12f1822.h: 1018: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1822.h: 1027: extern volatile unsigned char PR2 @ 0x01B;
+"1029
+[; ;pic12f1822.h: 1029: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1822.h: 1032: typedef union {
+[; ;pic12f1822.h: 1033: struct {
+[; ;pic12f1822.h: 1034: unsigned PR2 :8;
+[; ;pic12f1822.h: 1035: };
+[; ;pic12f1822.h: 1036: } PR2bits_t;
+[; ;pic12f1822.h: 1037: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1822.h: 1046: extern volatile unsigned char T2CON @ 0x01C;
+"1048
+[; ;pic12f1822.h: 1048: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1822.h: 1051: typedef union {
+[; ;pic12f1822.h: 1052: struct {
+[; ;pic12f1822.h: 1053: unsigned T2CKPS0 :1;
+[; ;pic12f1822.h: 1054: unsigned T2CKPS1 :1;
+[; ;pic12f1822.h: 1055: unsigned TMR2ON :1;
+[; ;pic12f1822.h: 1056: unsigned T2OUTPS0 :1;
+[; ;pic12f1822.h: 1057: unsigned T2OUTPS1 :1;
+[; ;pic12f1822.h: 1058: unsigned T2OUTPS2 :1;
+[; ;pic12f1822.h: 1059: unsigned T2OUTPS3 :1;
+[; ;pic12f1822.h: 1060: };
+[; ;pic12f1822.h: 1061: struct {
+[; ;pic12f1822.h: 1062: unsigned T2CKPS :2;
+[; ;pic12f1822.h: 1063: unsigned :1;
+[; ;pic12f1822.h: 1064: unsigned T2OUTPS :4;
+[; ;pic12f1822.h: 1065: };
+[; ;pic12f1822.h: 1066: } T2CONbits_t;
+[; ;pic12f1822.h: 1067: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1822.h: 1116: extern volatile unsigned char CPSCON0 @ 0x01E;
+"1118
+[; ;pic12f1822.h: 1118: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1822.h: 1121: typedef union {
+[; ;pic12f1822.h: 1122: struct {
+[; ;pic12f1822.h: 1123: unsigned T0XCS :1;
+[; ;pic12f1822.h: 1124: unsigned CPSOUT :1;
+[; ;pic12f1822.h: 1125: unsigned CPSRNG0 :1;
+[; ;pic12f1822.h: 1126: unsigned CPSRNG1 :1;
+[; ;pic12f1822.h: 1127: unsigned :2;
+[; ;pic12f1822.h: 1128: unsigned CPSRM :1;
+[; ;pic12f1822.h: 1129: unsigned CPSON :1;
+[; ;pic12f1822.h: 1130: };
+[; ;pic12f1822.h: 1131: struct {
+[; ;pic12f1822.h: 1132: unsigned :2;
+[; ;pic12f1822.h: 1133: unsigned CPSRNG :2;
+[; ;pic12f1822.h: 1134: };
+[; ;pic12f1822.h: 1135: } CPSCON0bits_t;
+[; ;pic12f1822.h: 1136: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1822.h: 1175: extern volatile unsigned char CPSCON1 @ 0x01F;
+"1177
+[; ;pic12f1822.h: 1177: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1822.h: 1180: typedef union {
+[; ;pic12f1822.h: 1181: struct {
+[; ;pic12f1822.h: 1182: unsigned CPSCH0 :1;
+[; ;pic12f1822.h: 1183: unsigned CPSCH1 :1;
+[; ;pic12f1822.h: 1184: };
+[; ;pic12f1822.h: 1185: struct {
+[; ;pic12f1822.h: 1186: unsigned CPSCH :2;
+[; ;pic12f1822.h: 1187: };
+[; ;pic12f1822.h: 1188: } CPSCON1bits_t;
+[; ;pic12f1822.h: 1189: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1822.h: 1208: extern volatile unsigned char TRISA @ 0x08C;
+"1210
+[; ;pic12f1822.h: 1210: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1822.h: 1213: typedef union {
+[; ;pic12f1822.h: 1214: struct {
+[; ;pic12f1822.h: 1215: unsigned TRISA0 :1;
+[; ;pic12f1822.h: 1216: unsigned TRISA1 :1;
+[; ;pic12f1822.h: 1217: unsigned TRISA2 :1;
+[; ;pic12f1822.h: 1218: unsigned TRISA3 :1;
+[; ;pic12f1822.h: 1219: unsigned TRISA4 :1;
+[; ;pic12f1822.h: 1220: unsigned TRISA5 :1;
+[; ;pic12f1822.h: 1221: };
+[; ;pic12f1822.h: 1222: } TRISAbits_t;
+[; ;pic12f1822.h: 1223: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1822.h: 1257: extern volatile unsigned char PIE1 @ 0x091;
+"1259
+[; ;pic12f1822.h: 1259: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1822.h: 1262: typedef union {
+[; ;pic12f1822.h: 1263: struct {
+[; ;pic12f1822.h: 1264: unsigned TMR1IE :1;
+[; ;pic12f1822.h: 1265: unsigned TMR2IE :1;
+[; ;pic12f1822.h: 1266: unsigned CCP1IE :1;
+[; ;pic12f1822.h: 1267: unsigned SSP1IE :1;
+[; ;pic12f1822.h: 1268: unsigned TXIE :1;
+[; ;pic12f1822.h: 1269: unsigned RCIE :1;
+[; ;pic12f1822.h: 1270: unsigned ADIE :1;
+[; ;pic12f1822.h: 1271: unsigned TMR1GIE :1;
+[; ;pic12f1822.h: 1272: };
+[; ;pic12f1822.h: 1273: } PIE1bits_t;
+[; ;pic12f1822.h: 1274: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1822.h: 1318: extern volatile unsigned char PIE2 @ 0x092;
+"1320
+[; ;pic12f1822.h: 1320: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1822.h: 1323: typedef union {
+[; ;pic12f1822.h: 1324: struct {
+[; ;pic12f1822.h: 1325: unsigned :3;
+[; ;pic12f1822.h: 1326: unsigned BCL1IE :1;
+[; ;pic12f1822.h: 1327: unsigned EEIE :1;
+[; ;pic12f1822.h: 1328: unsigned C1IE :1;
+[; ;pic12f1822.h: 1329: unsigned :1;
+[; ;pic12f1822.h: 1330: unsigned OSFIE :1;
+[; ;pic12f1822.h: 1331: };
+[; ;pic12f1822.h: 1332: } PIE2bits_t;
+[; ;pic12f1822.h: 1333: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1822.h: 1357: extern volatile unsigned char OPTION_REG @ 0x095;
+"1359
+[; ;pic12f1822.h: 1359: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1822.h: 1362: typedef union {
+[; ;pic12f1822.h: 1363: struct {
+[; ;pic12f1822.h: 1364: unsigned PS0 :1;
+[; ;pic12f1822.h: 1365: unsigned PS1 :1;
+[; ;pic12f1822.h: 1366: unsigned PS2 :1;
+[; ;pic12f1822.h: 1367: unsigned PSA :1;
+[; ;pic12f1822.h: 1368: unsigned TMR0SE :1;
+[; ;pic12f1822.h: 1369: unsigned TMR0CS :1;
+[; ;pic12f1822.h: 1370: unsigned INTEDG :1;
+[; ;pic12f1822.h: 1371: unsigned nWPUEN :1;
+[; ;pic12f1822.h: 1372: };
+[; ;pic12f1822.h: 1373: struct {
+[; ;pic12f1822.h: 1374: unsigned PS :3;
+[; ;pic12f1822.h: 1375: unsigned :1;
+[; ;pic12f1822.h: 1376: unsigned T0SE :1;
+[; ;pic12f1822.h: 1377: unsigned T0CS :1;
+[; ;pic12f1822.h: 1378: };
+[; ;pic12f1822.h: 1379: } OPTION_REGbits_t;
+[; ;pic12f1822.h: 1380: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1822.h: 1439: extern volatile unsigned char PCON @ 0x096;
+"1441
+[; ;pic12f1822.h: 1441: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1822.h: 1444: typedef union {
+[; ;pic12f1822.h: 1445: struct {
+[; ;pic12f1822.h: 1446: unsigned nBOR :1;
+[; ;pic12f1822.h: 1447: unsigned nPOR :1;
+[; ;pic12f1822.h: 1448: unsigned nRI :1;
+[; ;pic12f1822.h: 1449: unsigned nRMCLR :1;
+[; ;pic12f1822.h: 1450: unsigned :2;
+[; ;pic12f1822.h: 1451: unsigned STKUNF :1;
+[; ;pic12f1822.h: 1452: unsigned STKOVF :1;
+[; ;pic12f1822.h: 1453: };
+[; ;pic12f1822.h: 1454: } PCONbits_t;
+[; ;pic12f1822.h: 1455: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1822.h: 1489: extern volatile unsigned char WDTCON @ 0x097;
+"1491
+[; ;pic12f1822.h: 1491: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1822.h: 1494: typedef union {
+[; ;pic12f1822.h: 1495: struct {
+[; ;pic12f1822.h: 1496: unsigned SWDTEN :1;
+[; ;pic12f1822.h: 1497: unsigned WDTPS0 :1;
+[; ;pic12f1822.h: 1498: unsigned WDTPS1 :1;
+[; ;pic12f1822.h: 1499: unsigned WDTPS2 :1;
+[; ;pic12f1822.h: 1500: unsigned WDTPS3 :1;
+[; ;pic12f1822.h: 1501: unsigned WDTPS4 :1;
+[; ;pic12f1822.h: 1502: };
+[; ;pic12f1822.h: 1503: struct {
+[; ;pic12f1822.h: 1504: unsigned :1;
+[; ;pic12f1822.h: 1505: unsigned WDTPS :5;
+[; ;pic12f1822.h: 1506: };
+[; ;pic12f1822.h: 1507: } WDTCONbits_t;
+[; ;pic12f1822.h: 1508: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1822.h: 1547: extern volatile unsigned char OSCTUNE @ 0x098;
+"1549
+[; ;pic12f1822.h: 1549: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1822.h: 1552: typedef union {
+[; ;pic12f1822.h: 1553: struct {
+[; ;pic12f1822.h: 1554: unsigned TUN0 :1;
+[; ;pic12f1822.h: 1555: unsigned TUN1 :1;
+[; ;pic12f1822.h: 1556: unsigned TUN2 :1;
+[; ;pic12f1822.h: 1557: unsigned TUN3 :1;
+[; ;pic12f1822.h: 1558: unsigned TUN4 :1;
+[; ;pic12f1822.h: 1559: unsigned TUN5 :1;
+[; ;pic12f1822.h: 1560: };
+[; ;pic12f1822.h: 1561: struct {
+[; ;pic12f1822.h: 1562: unsigned TUN :6;
+[; ;pic12f1822.h: 1563: };
+[; ;pic12f1822.h: 1564: } OSCTUNEbits_t;
+[; ;pic12f1822.h: 1565: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1822.h: 1604: extern volatile unsigned char OSCCON @ 0x099;
+"1606
+[; ;pic12f1822.h: 1606: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1822.h: 1609: typedef union {
+[; ;pic12f1822.h: 1610: struct {
+[; ;pic12f1822.h: 1611: unsigned SCS0 :1;
+[; ;pic12f1822.h: 1612: unsigned SCS1 :1;
+[; ;pic12f1822.h: 1613: unsigned :1;
+[; ;pic12f1822.h: 1614: unsigned IRCF0 :1;
+[; ;pic12f1822.h: 1615: unsigned IRCF1 :1;
+[; ;pic12f1822.h: 1616: unsigned IRCF2 :1;
+[; ;pic12f1822.h: 1617: unsigned IRCF3 :1;
+[; ;pic12f1822.h: 1618: unsigned SPLLEN :1;
+[; ;pic12f1822.h: 1619: };
+[; ;pic12f1822.h: 1620: struct {
+[; ;pic12f1822.h: 1621: unsigned SCS :2;
+[; ;pic12f1822.h: 1622: unsigned :1;
+[; ;pic12f1822.h: 1623: unsigned IRCF :4;
+[; ;pic12f1822.h: 1624: };
+[; ;pic12f1822.h: 1625: } OSCCONbits_t;
+[; ;pic12f1822.h: 1626: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1822.h: 1675: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1677
+[; ;pic12f1822.h: 1677: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1822.h: 1680: typedef union {
+[; ;pic12f1822.h: 1681: struct {
+[; ;pic12f1822.h: 1682: unsigned HFIOFS :1;
+[; ;pic12f1822.h: 1683: unsigned LFIOFR :1;
+[; ;pic12f1822.h: 1684: unsigned MFIOFR :1;
+[; ;pic12f1822.h: 1685: unsigned HFIOFL :1;
+[; ;pic12f1822.h: 1686: unsigned HFIOFR :1;
+[; ;pic12f1822.h: 1687: unsigned OSTS :1;
+[; ;pic12f1822.h: 1688: unsigned PLLR :1;
+[; ;pic12f1822.h: 1689: unsigned T1OSCR :1;
+[; ;pic12f1822.h: 1690: };
+[; ;pic12f1822.h: 1691: } OSCSTATbits_t;
+[; ;pic12f1822.h: 1692: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1822.h: 1736: extern volatile unsigned short ADRES @ 0x09B;
+"1738
+[; ;pic12f1822.h: 1738: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1822.h: 1742: extern volatile unsigned char ADRESL @ 0x09B;
+"1744
+[; ;pic12f1822.h: 1744: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1822.h: 1747: typedef union {
+[; ;pic12f1822.h: 1748: struct {
+[; ;pic12f1822.h: 1749: unsigned ADRESL :8;
+[; ;pic12f1822.h: 1750: };
+[; ;pic12f1822.h: 1751: } ADRESLbits_t;
+[; ;pic12f1822.h: 1752: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1822.h: 1761: extern volatile unsigned char ADRESH @ 0x09C;
+"1763
+[; ;pic12f1822.h: 1763: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1822.h: 1766: typedef union {
+[; ;pic12f1822.h: 1767: struct {
+[; ;pic12f1822.h: 1768: unsigned ADRESH :8;
+[; ;pic12f1822.h: 1769: };
+[; ;pic12f1822.h: 1770: } ADRESHbits_t;
+[; ;pic12f1822.h: 1771: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1822.h: 1780: extern volatile unsigned char ADCON0 @ 0x09D;
+"1782
+[; ;pic12f1822.h: 1782: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1822.h: 1785: typedef union {
+[; ;pic12f1822.h: 1786: struct {
+[; ;pic12f1822.h: 1787: unsigned ADON :1;
+[; ;pic12f1822.h: 1788: unsigned GO_nDONE :1;
+[; ;pic12f1822.h: 1789: unsigned CHS0 :1;
+[; ;pic12f1822.h: 1790: unsigned CHS1 :1;
+[; ;pic12f1822.h: 1791: unsigned CHS2 :1;
+[; ;pic12f1822.h: 1792: unsigned CHS3 :1;
+[; ;pic12f1822.h: 1793: unsigned CHS4 :1;
+[; ;pic12f1822.h: 1794: };
+[; ;pic12f1822.h: 1795: struct {
+[; ;pic12f1822.h: 1796: unsigned :1;
+[; ;pic12f1822.h: 1797: unsigned ADGO :1;
+[; ;pic12f1822.h: 1798: unsigned CHS :5;
+[; ;pic12f1822.h: 1799: };
+[; ;pic12f1822.h: 1800: struct {
+[; ;pic12f1822.h: 1801: unsigned :1;
+[; ;pic12f1822.h: 1802: unsigned GO :1;
+[; ;pic12f1822.h: 1803: };
+[; ;pic12f1822.h: 1804: struct {
+[; ;pic12f1822.h: 1805: unsigned :1;
+[; ;pic12f1822.h: 1806: unsigned nDONE :1;
+[; ;pic12f1822.h: 1807: };
+[; ;pic12f1822.h: 1808: } ADCON0bits_t;
+[; ;pic12f1822.h: 1809: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1822.h: 1868: extern volatile unsigned char ADCON1 @ 0x09E;
+"1870
+[; ;pic12f1822.h: 1870: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1822.h: 1873: typedef union {
+[; ;pic12f1822.h: 1874: struct {
+[; ;pic12f1822.h: 1875: unsigned ADPREF0 :1;
+[; ;pic12f1822.h: 1876: unsigned ADPREF1 :1;
+[; ;pic12f1822.h: 1877: unsigned :2;
+[; ;pic12f1822.h: 1878: unsigned ADCS0 :1;
+[; ;pic12f1822.h: 1879: unsigned ADCS1 :1;
+[; ;pic12f1822.h: 1880: unsigned ADCS2 :1;
+[; ;pic12f1822.h: 1881: unsigned ADFM :1;
+[; ;pic12f1822.h: 1882: };
+[; ;pic12f1822.h: 1883: struct {
+[; ;pic12f1822.h: 1884: unsigned ADPREF :2;
+[; ;pic12f1822.h: 1885: unsigned :2;
+[; ;pic12f1822.h: 1886: unsigned ADCS :3;
+[; ;pic12f1822.h: 1887: };
+[; ;pic12f1822.h: 1888: } ADCON1bits_t;
+[; ;pic12f1822.h: 1889: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1822.h: 1933: extern volatile unsigned char LATA @ 0x10C;
+"1935
+[; ;pic12f1822.h: 1935: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1822.h: 1938: typedef union {
+[; ;pic12f1822.h: 1939: struct {
+[; ;pic12f1822.h: 1940: unsigned LATA0 :1;
+[; ;pic12f1822.h: 1941: unsigned LATA1 :1;
+[; ;pic12f1822.h: 1942: unsigned LATA2 :1;
+[; ;pic12f1822.h: 1943: unsigned :1;
+[; ;pic12f1822.h: 1944: unsigned LATA4 :1;
+[; ;pic12f1822.h: 1945: unsigned LATA5 :1;
+[; ;pic12f1822.h: 1946: };
+[; ;pic12f1822.h: 1947: } LATAbits_t;
+[; ;pic12f1822.h: 1948: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1822.h: 1977: extern volatile unsigned char CM1CON0 @ 0x111;
+"1979
+[; ;pic12f1822.h: 1979: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1822.h: 1982: typedef union {
+[; ;pic12f1822.h: 1983: struct {
+[; ;pic12f1822.h: 1984: unsigned C1SYNC :1;
+[; ;pic12f1822.h: 1985: unsigned C1HYS :1;
+[; ;pic12f1822.h: 1986: unsigned C1SP :1;
+[; ;pic12f1822.h: 1987: unsigned :1;
+[; ;pic12f1822.h: 1988: unsigned C1POL :1;
+[; ;pic12f1822.h: 1989: unsigned C1OE :1;
+[; ;pic12f1822.h: 1990: unsigned C1OUT :1;
+[; ;pic12f1822.h: 1991: unsigned C1ON :1;
+[; ;pic12f1822.h: 1992: };
+[; ;pic12f1822.h: 1993: } CM1CON0bits_t;
+[; ;pic12f1822.h: 1994: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1822.h: 2033: extern volatile unsigned char CM1CON1 @ 0x112;
+"2035
+[; ;pic12f1822.h: 2035: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1822.h: 2038: typedef union {
+[; ;pic12f1822.h: 2039: struct {
+[; ;pic12f1822.h: 2040: unsigned C1NCH0 :1;
+[; ;pic12f1822.h: 2041: unsigned :3;
+[; ;pic12f1822.h: 2042: unsigned C1PCH0 :1;
+[; ;pic12f1822.h: 2043: unsigned C1PCH1 :1;
+[; ;pic12f1822.h: 2044: unsigned C1INTN :1;
+[; ;pic12f1822.h: 2045: unsigned C1INTP :1;
+[; ;pic12f1822.h: 2046: };
+[; ;pic12f1822.h: 2047: struct {
+[; ;pic12f1822.h: 2048: unsigned :4;
+[; ;pic12f1822.h: 2049: unsigned C1PCH :2;
+[; ;pic12f1822.h: 2050: };
+[; ;pic12f1822.h: 2051: } CM1CON1bits_t;
+[; ;pic12f1822.h: 2052: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1822.h: 2086: extern volatile unsigned char CMOUT @ 0x115;
+"2088
+[; ;pic12f1822.h: 2088: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1822.h: 2091: typedef union {
+[; ;pic12f1822.h: 2092: struct {
+[; ;pic12f1822.h: 2093: unsigned MC1OUT :1;
+[; ;pic12f1822.h: 2094: };
+[; ;pic12f1822.h: 2095: } CMOUTbits_t;
+[; ;pic12f1822.h: 2096: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1822.h: 2105: extern volatile unsigned char BORCON @ 0x116;
+"2107
+[; ;pic12f1822.h: 2107: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1822.h: 2110: typedef union {
+[; ;pic12f1822.h: 2111: struct {
+[; ;pic12f1822.h: 2112: unsigned BORRDY :1;
+[; ;pic12f1822.h: 2113: unsigned :6;
+[; ;pic12f1822.h: 2114: unsigned SBOREN :1;
+[; ;pic12f1822.h: 2115: };
+[; ;pic12f1822.h: 2116: } BORCONbits_t;
+[; ;pic12f1822.h: 2117: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1822.h: 2131: extern volatile unsigned char FVRCON @ 0x117;
+"2133
+[; ;pic12f1822.h: 2133: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1822.h: 2136: typedef union {
+[; ;pic12f1822.h: 2137: struct {
+[; ;pic12f1822.h: 2138: unsigned ADFVR0 :1;
+[; ;pic12f1822.h: 2139: unsigned ADFVR1 :1;
+[; ;pic12f1822.h: 2140: unsigned CDAFVR0 :1;
+[; ;pic12f1822.h: 2141: unsigned CDAFVR1 :1;
+[; ;pic12f1822.h: 2142: unsigned TSRNG :1;
+[; ;pic12f1822.h: 2143: unsigned TSEN :1;
+[; ;pic12f1822.h: 2144: unsigned FVRRDY :1;
+[; ;pic12f1822.h: 2145: unsigned FVREN :1;
+[; ;pic12f1822.h: 2146: };
+[; ;pic12f1822.h: 2147: struct {
+[; ;pic12f1822.h: 2148: unsigned ADFVR :2;
+[; ;pic12f1822.h: 2149: unsigned CDAFVR :2;
+[; ;pic12f1822.h: 2150: };
+[; ;pic12f1822.h: 2151: } FVRCONbits_t;
+[; ;pic12f1822.h: 2152: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1822.h: 2206: extern volatile unsigned char DACCON0 @ 0x118;
+"2208
+[; ;pic12f1822.h: 2208: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1822.h: 2211: typedef union {
+[; ;pic12f1822.h: 2212: struct {
+[; ;pic12f1822.h: 2213: unsigned :2;
+[; ;pic12f1822.h: 2214: unsigned DACPSS0 :1;
+[; ;pic12f1822.h: 2215: unsigned DACPSS1 :1;
+[; ;pic12f1822.h: 2216: unsigned :1;
+[; ;pic12f1822.h: 2217: unsigned DACOE :1;
+[; ;pic12f1822.h: 2218: unsigned DACLPS :1;
+[; ;pic12f1822.h: 2219: unsigned DACEN :1;
+[; ;pic12f1822.h: 2220: };
+[; ;pic12f1822.h: 2221: struct {
+[; ;pic12f1822.h: 2222: unsigned :2;
+[; ;pic12f1822.h: 2223: unsigned DACPSS :2;
+[; ;pic12f1822.h: 2224: };
+[; ;pic12f1822.h: 2225: } DACCON0bits_t;
+[; ;pic12f1822.h: 2226: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1822.h: 2260: extern volatile unsigned char DACCON1 @ 0x119;
+"2262
+[; ;pic12f1822.h: 2262: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1822.h: 2265: typedef union {
+[; ;pic12f1822.h: 2266: struct {
+[; ;pic12f1822.h: 2267: unsigned DACR0 :1;
+[; ;pic12f1822.h: 2268: unsigned DACR1 :1;
+[; ;pic12f1822.h: 2269: unsigned DACR2 :1;
+[; ;pic12f1822.h: 2270: unsigned DACR3 :1;
+[; ;pic12f1822.h: 2271: unsigned DACR4 :1;
+[; ;pic12f1822.h: 2272: };
+[; ;pic12f1822.h: 2273: struct {
+[; ;pic12f1822.h: 2274: unsigned DACR :5;
+[; ;pic12f1822.h: 2275: };
+[; ;pic12f1822.h: 2276: } DACCON1bits_t;
+[; ;pic12f1822.h: 2277: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1822.h: 2311: extern volatile unsigned char SRCON0 @ 0x11A;
+"2313
+[; ;pic12f1822.h: 2313: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1822.h: 2316: typedef union {
+[; ;pic12f1822.h: 2317: struct {
+[; ;pic12f1822.h: 2318: unsigned SRPR :1;
+[; ;pic12f1822.h: 2319: unsigned SRPS :1;
+[; ;pic12f1822.h: 2320: unsigned SRNQEN :1;
+[; ;pic12f1822.h: 2321: unsigned SRQEN :1;
+[; ;pic12f1822.h: 2322: unsigned SRCLK0 :1;
+[; ;pic12f1822.h: 2323: unsigned SRCLK1 :1;
+[; ;pic12f1822.h: 2324: unsigned SRCLK2 :1;
+[; ;pic12f1822.h: 2325: unsigned SRLEN :1;
+[; ;pic12f1822.h: 2326: };
+[; ;pic12f1822.h: 2327: struct {
+[; ;pic12f1822.h: 2328: unsigned :4;
+[; ;pic12f1822.h: 2329: unsigned SRCLK :3;
+[; ;pic12f1822.h: 2330: };
+[; ;pic12f1822.h: 2331: } SRCON0bits_t;
+[; ;pic12f1822.h: 2332: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1822.h: 2381: extern volatile unsigned char SRCON1 @ 0x11B;
+"2383
+[; ;pic12f1822.h: 2383: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1822.h: 2386: typedef union {
+[; ;pic12f1822.h: 2387: struct {
+[; ;pic12f1822.h: 2388: unsigned SRRC1E :1;
+[; ;pic12f1822.h: 2389: unsigned :1;
+[; ;pic12f1822.h: 2390: unsigned SRRCKE :1;
+[; ;pic12f1822.h: 2391: unsigned SRRPE :1;
+[; ;pic12f1822.h: 2392: unsigned SRSC1E :1;
+[; ;pic12f1822.h: 2393: unsigned :1;
+[; ;pic12f1822.h: 2394: unsigned SRSCKE :1;
+[; ;pic12f1822.h: 2395: unsigned SRSPE :1;
+[; ;pic12f1822.h: 2396: };
+[; ;pic12f1822.h: 2397: } SRCON1bits_t;
+[; ;pic12f1822.h: 2398: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1822.h: 2432: extern volatile unsigned char APFCON @ 0x11D;
+"2434
+[; ;pic12f1822.h: 2434: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1822.h: 2437: extern volatile unsigned char APFCON0 @ 0x11D;
+"2439
+[; ;pic12f1822.h: 2439: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1822.h: 2442: typedef union {
+[; ;pic12f1822.h: 2443: struct {
+[; ;pic12f1822.h: 2444: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2445: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2446: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2447: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2448: unsigned :1;
+[; ;pic12f1822.h: 2449: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2450: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2451: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2452: };
+[; ;pic12f1822.h: 2453: struct {
+[; ;pic12f1822.h: 2454: unsigned :5;
+[; ;pic12f1822.h: 2455: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2456: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2457: };
+[; ;pic12f1822.h: 2458: } APFCONbits_t;
+[; ;pic12f1822.h: 2459: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1822.h: 2507: typedef union {
+[; ;pic12f1822.h: 2508: struct {
+[; ;pic12f1822.h: 2509: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2510: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2511: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2512: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2513: unsigned :1;
+[; ;pic12f1822.h: 2514: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2515: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2516: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2517: };
+[; ;pic12f1822.h: 2518: struct {
+[; ;pic12f1822.h: 2519: unsigned :5;
+[; ;pic12f1822.h: 2520: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2521: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2522: };
+[; ;pic12f1822.h: 2523: } APFCON0bits_t;
+[; ;pic12f1822.h: 2524: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1822.h: 2573: extern volatile unsigned char ANSELA @ 0x18C;
+"2575
+[; ;pic12f1822.h: 2575: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1822.h: 2578: typedef union {
+[; ;pic12f1822.h: 2579: struct {
+[; ;pic12f1822.h: 2580: unsigned ANSA0 :1;
+[; ;pic12f1822.h: 2581: unsigned ANSA1 :1;
+[; ;pic12f1822.h: 2582: unsigned ANSA2 :1;
+[; ;pic12f1822.h: 2583: unsigned :1;
+[; ;pic12f1822.h: 2584: unsigned ANSA4 :1;
+[; ;pic12f1822.h: 2585: };
+[; ;pic12f1822.h: 2586: struct {
+[; ;pic12f1822.h: 2587: unsigned ANSELA :5;
+[; ;pic12f1822.h: 2588: };
+[; ;pic12f1822.h: 2589: } ANSELAbits_t;
+[; ;pic12f1822.h: 2590: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1822.h: 2619: extern volatile unsigned short EEADR @ 0x191;
+"2621
+[; ;pic12f1822.h: 2621: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1822.h: 2625: extern volatile unsigned char EEADRL @ 0x191;
+"2627
+[; ;pic12f1822.h: 2627: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1822.h: 2630: typedef union {
+[; ;pic12f1822.h: 2631: struct {
+[; ;pic12f1822.h: 2632: unsigned EEADRL :8;
+[; ;pic12f1822.h: 2633: };
+[; ;pic12f1822.h: 2634: } EEADRLbits_t;
+[; ;pic12f1822.h: 2635: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1822.h: 2644: extern volatile unsigned char EEADRH @ 0x192;
+"2646
+[; ;pic12f1822.h: 2646: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1822.h: 2649: typedef union {
+[; ;pic12f1822.h: 2650: struct {
+[; ;pic12f1822.h: 2651: unsigned EEADRH :7;
+[; ;pic12f1822.h: 2652: };
+[; ;pic12f1822.h: 2653: } EEADRHbits_t;
+[; ;pic12f1822.h: 2654: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1822.h: 2663: extern volatile unsigned short EEDAT @ 0x193;
+"2665
+[; ;pic12f1822.h: 2665: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1822.h: 2669: extern volatile unsigned char EEDATL @ 0x193;
+"2671
+[; ;pic12f1822.h: 2671: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1822.h: 2674: extern volatile unsigned char EEDATA @ 0x193;
+"2676
+[; ;pic12f1822.h: 2676: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1822.h: 2679: typedef union {
+[; ;pic12f1822.h: 2680: struct {
+[; ;pic12f1822.h: 2681: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2682: };
+[; ;pic12f1822.h: 2683: } EEDATLbits_t;
+[; ;pic12f1822.h: 2684: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1822.h: 2692: typedef union {
+[; ;pic12f1822.h: 2693: struct {
+[; ;pic12f1822.h: 2694: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2695: };
+[; ;pic12f1822.h: 2696: } EEDATAbits_t;
+[; ;pic12f1822.h: 2697: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1822.h: 2706: extern volatile unsigned char EEDATH @ 0x194;
+"2708
+[; ;pic12f1822.h: 2708: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1822.h: 2711: typedef union {
+[; ;pic12f1822.h: 2712: struct {
+[; ;pic12f1822.h: 2713: unsigned EEDATH :6;
+[; ;pic12f1822.h: 2714: };
+[; ;pic12f1822.h: 2715: } EEDATHbits_t;
+[; ;pic12f1822.h: 2716: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1822.h: 2725: extern volatile unsigned char EECON1 @ 0x195;
+"2727
+[; ;pic12f1822.h: 2727: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1822.h: 2730: typedef union {
+[; ;pic12f1822.h: 2731: struct {
+[; ;pic12f1822.h: 2732: unsigned RD :1;
+[; ;pic12f1822.h: 2733: unsigned WR :1;
+[; ;pic12f1822.h: 2734: unsigned WREN :1;
+[; ;pic12f1822.h: 2735: unsigned WRERR :1;
+[; ;pic12f1822.h: 2736: unsigned FREE :1;
+[; ;pic12f1822.h: 2737: unsigned LWLO :1;
+[; ;pic12f1822.h: 2738: unsigned CFGS :1;
+[; ;pic12f1822.h: 2739: unsigned EEPGD :1;
+[; ;pic12f1822.h: 2740: };
+[; ;pic12f1822.h: 2741: } EECON1bits_t;
+[; ;pic12f1822.h: 2742: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1822.h: 2786: extern volatile unsigned char EECON2 @ 0x196;
+"2788
+[; ;pic12f1822.h: 2788: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1822.h: 2791: typedef union {
+[; ;pic12f1822.h: 2792: struct {
+[; ;pic12f1822.h: 2793: unsigned EECON2 :8;
+[; ;pic12f1822.h: 2794: };
+[; ;pic12f1822.h: 2795: } EECON2bits_t;
+[; ;pic12f1822.h: 2796: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1822.h: 2805: extern volatile unsigned char RCREG @ 0x199;
+"2807
+[; ;pic12f1822.h: 2807: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1822.h: 2810: typedef union {
+[; ;pic12f1822.h: 2811: struct {
+[; ;pic12f1822.h: 2812: unsigned RCREG :8;
+[; ;pic12f1822.h: 2813: };
+[; ;pic12f1822.h: 2814: } RCREGbits_t;
+[; ;pic12f1822.h: 2815: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1822.h: 2824: extern volatile unsigned char TXREG @ 0x19A;
+"2826
+[; ;pic12f1822.h: 2826: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1822.h: 2829: typedef union {
+[; ;pic12f1822.h: 2830: struct {
+[; ;pic12f1822.h: 2831: unsigned TXREG :8;
+[; ;pic12f1822.h: 2832: };
+[; ;pic12f1822.h: 2833: } TXREGbits_t;
+[; ;pic12f1822.h: 2834: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1822.h: 2843: extern volatile unsigned char SPBRGL @ 0x19B;
+"2845
+[; ;pic12f1822.h: 2845: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1822.h: 2848: extern volatile unsigned char SPBRG @ 0x19B;
+"2850
+[; ;pic12f1822.h: 2850: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1822.h: 2853: typedef union {
+[; ;pic12f1822.h: 2854: struct {
+[; ;pic12f1822.h: 2855: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2856: };
+[; ;pic12f1822.h: 2857: } SPBRGLbits_t;
+[; ;pic12f1822.h: 2858: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1822.h: 2866: typedef union {
+[; ;pic12f1822.h: 2867: struct {
+[; ;pic12f1822.h: 2868: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2869: };
+[; ;pic12f1822.h: 2870: } SPBRGbits_t;
+[; ;pic12f1822.h: 2871: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1822.h: 2880: extern volatile unsigned char SPBRGH @ 0x19C;
+"2882
+[; ;pic12f1822.h: 2882: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1822.h: 2885: typedef union {
+[; ;pic12f1822.h: 2886: struct {
+[; ;pic12f1822.h: 2887: unsigned SPBRGH :8;
+[; ;pic12f1822.h: 2888: };
+[; ;pic12f1822.h: 2889: } SPBRGHbits_t;
+[; ;pic12f1822.h: 2890: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1822.h: 2899: extern volatile unsigned char RCSTA @ 0x19D;
+"2901
+[; ;pic12f1822.h: 2901: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1822.h: 2904: typedef union {
+[; ;pic12f1822.h: 2905: struct {
+[; ;pic12f1822.h: 2906: unsigned RX9D :1;
+[; ;pic12f1822.h: 2907: unsigned OERR :1;
+[; ;pic12f1822.h: 2908: unsigned FERR :1;
+[; ;pic12f1822.h: 2909: unsigned ADDEN :1;
+[; ;pic12f1822.h: 2910: unsigned CREN :1;
+[; ;pic12f1822.h: 2911: unsigned SREN :1;
+[; ;pic12f1822.h: 2912: unsigned RX9 :1;
+[; ;pic12f1822.h: 2913: unsigned SPEN :1;
+[; ;pic12f1822.h: 2914: };
+[; ;pic12f1822.h: 2915: } RCSTAbits_t;
+[; ;pic12f1822.h: 2916: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1822.h: 2960: extern volatile unsigned char TXSTA @ 0x19E;
+"2962
+[; ;pic12f1822.h: 2962: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1822.h: 2965: typedef union {
+[; ;pic12f1822.h: 2966: struct {
+[; ;pic12f1822.h: 2967: unsigned TX9D :1;
+[; ;pic12f1822.h: 2968: unsigned TRMT :1;
+[; ;pic12f1822.h: 2969: unsigned BRGH :1;
+[; ;pic12f1822.h: 2970: unsigned SENDB :1;
+[; ;pic12f1822.h: 2971: unsigned SYNC :1;
+[; ;pic12f1822.h: 2972: unsigned TXEN :1;
+[; ;pic12f1822.h: 2973: unsigned TX9 :1;
+[; ;pic12f1822.h: 2974: unsigned CSRC :1;
+[; ;pic12f1822.h: 2975: };
+[; ;pic12f1822.h: 2976: } TXSTAbits_t;
+[; ;pic12f1822.h: 2977: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1822.h: 3021: extern volatile unsigned char BAUDCON @ 0x19F;
+"3023
+[; ;pic12f1822.h: 3023: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1822.h: 3026: typedef union {
+[; ;pic12f1822.h: 3027: struct {
+[; ;pic12f1822.h: 3028: unsigned ABDEN :1;
+[; ;pic12f1822.h: 3029: unsigned WUE :1;
+[; ;pic12f1822.h: 3030: unsigned :1;
+[; ;pic12f1822.h: 3031: unsigned BRG16 :1;
+[; ;pic12f1822.h: 3032: unsigned SCKP :1;
+[; ;pic12f1822.h: 3033: unsigned :1;
+[; ;pic12f1822.h: 3034: unsigned RCIDL :1;
+[; ;pic12f1822.h: 3035: unsigned ABDOVF :1;
+[; ;pic12f1822.h: 3036: };
+[; ;pic12f1822.h: 3037: } BAUDCONbits_t;
+[; ;pic12f1822.h: 3038: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1822.h: 3072: extern volatile unsigned char WPUA @ 0x20C;
+"3074
+[; ;pic12f1822.h: 3074: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1822.h: 3077: typedef union {
+[; ;pic12f1822.h: 3078: struct {
+[; ;pic12f1822.h: 3079: unsigned WPUA0 :1;
+[; ;pic12f1822.h: 3080: unsigned WPUA1 :1;
+[; ;pic12f1822.h: 3081: unsigned WPUA2 :1;
+[; ;pic12f1822.h: 3082: unsigned WPUA3 :1;
+[; ;pic12f1822.h: 3083: unsigned WPUA4 :1;
+[; ;pic12f1822.h: 3084: unsigned WPUA5 :1;
+[; ;pic12f1822.h: 3085: };
+[; ;pic12f1822.h: 3086: struct {
+[; ;pic12f1822.h: 3087: unsigned WPUA :6;
+[; ;pic12f1822.h: 3088: };
+[; ;pic12f1822.h: 3089: } WPUAbits_t;
+[; ;pic12f1822.h: 3090: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1822.h: 3129: extern volatile unsigned char SSP1BUF @ 0x211;
+"3131
+[; ;pic12f1822.h: 3131: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3134: extern volatile unsigned char SSPBUF @ 0x211;
+"3136
+[; ;pic12f1822.h: 3136: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3139: typedef union {
+[; ;pic12f1822.h: 3140: struct {
+[; ;pic12f1822.h: 3141: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3142: };
+[; ;pic12f1822.h: 3143: } SSP1BUFbits_t;
+[; ;pic12f1822.h: 3144: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1822.h: 3152: typedef union {
+[; ;pic12f1822.h: 3153: struct {
+[; ;pic12f1822.h: 3154: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3155: };
+[; ;pic12f1822.h: 3156: } SSPBUFbits_t;
+[; ;pic12f1822.h: 3157: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1822.h: 3166: extern volatile unsigned char SSP1ADD @ 0x212;
+"3168
+[; ;pic12f1822.h: 3168: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3171: extern volatile unsigned char SSPADD @ 0x212;
+"3173
+[; ;pic12f1822.h: 3173: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3176: typedef union {
+[; ;pic12f1822.h: 3177: struct {
+[; ;pic12f1822.h: 3178: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3179: };
+[; ;pic12f1822.h: 3180: } SSP1ADDbits_t;
+[; ;pic12f1822.h: 3181: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1822.h: 3189: typedef union {
+[; ;pic12f1822.h: 3190: struct {
+[; ;pic12f1822.h: 3191: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3192: };
+[; ;pic12f1822.h: 3193: } SSPADDbits_t;
+[; ;pic12f1822.h: 3194: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1822.h: 3203: extern volatile unsigned char SSP1MSK @ 0x213;
+"3205
+[; ;pic12f1822.h: 3205: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3208: extern volatile unsigned char SSPMSK @ 0x213;
+"3210
+[; ;pic12f1822.h: 3210: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3213: typedef union {
+[; ;pic12f1822.h: 3214: struct {
+[; ;pic12f1822.h: 3215: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3216: };
+[; ;pic12f1822.h: 3217: } SSP1MSKbits_t;
+[; ;pic12f1822.h: 3218: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1822.h: 3226: typedef union {
+[; ;pic12f1822.h: 3227: struct {
+[; ;pic12f1822.h: 3228: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3229: };
+[; ;pic12f1822.h: 3230: } SSPMSKbits_t;
+[; ;pic12f1822.h: 3231: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1822.h: 3240: extern volatile unsigned char SSP1STAT @ 0x214;
+"3242
+[; ;pic12f1822.h: 3242: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3245: extern volatile unsigned char SSPSTAT @ 0x214;
+"3247
+[; ;pic12f1822.h: 3247: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3250: typedef union {
+[; ;pic12f1822.h: 3251: struct {
+[; ;pic12f1822.h: 3252: unsigned BF :1;
+[; ;pic12f1822.h: 3253: unsigned UA :1;
+[; ;pic12f1822.h: 3254: unsigned R_nW :1;
+[; ;pic12f1822.h: 3255: unsigned S :1;
+[; ;pic12f1822.h: 3256: unsigned P :1;
+[; ;pic12f1822.h: 3257: unsigned D_nA :1;
+[; ;pic12f1822.h: 3258: unsigned CKE :1;
+[; ;pic12f1822.h: 3259: unsigned SMP :1;
+[; ;pic12f1822.h: 3260: };
+[; ;pic12f1822.h: 3261: } SSP1STATbits_t;
+[; ;pic12f1822.h: 3262: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1822.h: 3305: typedef union {
+[; ;pic12f1822.h: 3306: struct {
+[; ;pic12f1822.h: 3307: unsigned BF :1;
+[; ;pic12f1822.h: 3308: unsigned UA :1;
+[; ;pic12f1822.h: 3309: unsigned R_nW :1;
+[; ;pic12f1822.h: 3310: unsigned S :1;
+[; ;pic12f1822.h: 3311: unsigned P :1;
+[; ;pic12f1822.h: 3312: unsigned D_nA :1;
+[; ;pic12f1822.h: 3313: unsigned CKE :1;
+[; ;pic12f1822.h: 3314: unsigned SMP :1;
+[; ;pic12f1822.h: 3315: };
+[; ;pic12f1822.h: 3316: } SSPSTATbits_t;
+[; ;pic12f1822.h: 3317: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1822.h: 3361: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3363
+[; ;pic12f1822.h: 3363: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3366: extern volatile unsigned char SSPCON1 @ 0x215;
+"3368
+[; ;pic12f1822.h: 3368: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3370: extern volatile unsigned char SSPCON @ 0x215;
+"3372
+[; ;pic12f1822.h: 3372: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1822.h: 3375: typedef union {
+[; ;pic12f1822.h: 3376: struct {
+[; ;pic12f1822.h: 3377: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3378: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3379: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3380: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3381: unsigned CKP :1;
+[; ;pic12f1822.h: 3382: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3383: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3384: unsigned WCOL :1;
+[; ;pic12f1822.h: 3385: };
+[; ;pic12f1822.h: 3386: struct {
+[; ;pic12f1822.h: 3387: unsigned SSPM :4;
+[; ;pic12f1822.h: 3388: };
+[; ;pic12f1822.h: 3389: } SSP1CON1bits_t;
+[; ;pic12f1822.h: 3390: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1822.h: 3438: typedef union {
+[; ;pic12f1822.h: 3439: struct {
+[; ;pic12f1822.h: 3440: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3441: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3442: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3443: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3444: unsigned CKP :1;
+[; ;pic12f1822.h: 3445: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3446: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3447: unsigned WCOL :1;
+[; ;pic12f1822.h: 3448: };
+[; ;pic12f1822.h: 3449: struct {
+[; ;pic12f1822.h: 3450: unsigned SSPM :4;
+[; ;pic12f1822.h: 3451: };
+[; ;pic12f1822.h: 3452: } SSPCON1bits_t;
+[; ;pic12f1822.h: 3453: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1822.h: 3500: typedef union {
+[; ;pic12f1822.h: 3501: struct {
+[; ;pic12f1822.h: 3502: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3503: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3504: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3505: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3506: unsigned CKP :1;
+[; ;pic12f1822.h: 3507: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3508: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3509: unsigned WCOL :1;
+[; ;pic12f1822.h: 3510: };
+[; ;pic12f1822.h: 3511: struct {
+[; ;pic12f1822.h: 3512: unsigned SSPM :4;
+[; ;pic12f1822.h: 3513: };
+[; ;pic12f1822.h: 3514: } SSPCONbits_t;
+[; ;pic12f1822.h: 3515: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1822.h: 3564: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3566
+[; ;pic12f1822.h: 3566: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3569: extern volatile unsigned char SSPCON2 @ 0x216;
+"3571
+[; ;pic12f1822.h: 3571: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3574: typedef union {
+[; ;pic12f1822.h: 3575: struct {
+[; ;pic12f1822.h: 3576: unsigned SEN :1;
+[; ;pic12f1822.h: 3577: unsigned RSEN :1;
+[; ;pic12f1822.h: 3578: unsigned PEN :1;
+[; ;pic12f1822.h: 3579: unsigned RCEN :1;
+[; ;pic12f1822.h: 3580: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3581: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3582: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3583: unsigned GCEN :1;
+[; ;pic12f1822.h: 3584: };
+[; ;pic12f1822.h: 3585: } SSP1CON2bits_t;
+[; ;pic12f1822.h: 3586: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1822.h: 3629: typedef union {
+[; ;pic12f1822.h: 3630: struct {
+[; ;pic12f1822.h: 3631: unsigned SEN :1;
+[; ;pic12f1822.h: 3632: unsigned RSEN :1;
+[; ;pic12f1822.h: 3633: unsigned PEN :1;
+[; ;pic12f1822.h: 3634: unsigned RCEN :1;
+[; ;pic12f1822.h: 3635: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3636: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3637: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3638: unsigned GCEN :1;
+[; ;pic12f1822.h: 3639: };
+[; ;pic12f1822.h: 3640: } SSPCON2bits_t;
+[; ;pic12f1822.h: 3641: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1822.h: 3685: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3687
+[; ;pic12f1822.h: 3687: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3690: extern volatile unsigned char SSPCON3 @ 0x217;
+"3692
+[; ;pic12f1822.h: 3692: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3695: typedef union {
+[; ;pic12f1822.h: 3696: struct {
+[; ;pic12f1822.h: 3697: unsigned DHEN :1;
+[; ;pic12f1822.h: 3698: unsigned AHEN :1;
+[; ;pic12f1822.h: 3699: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3700: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3701: unsigned BOEN :1;
+[; ;pic12f1822.h: 3702: unsigned SCIE :1;
+[; ;pic12f1822.h: 3703: unsigned PCIE :1;
+[; ;pic12f1822.h: 3704: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3705: };
+[; ;pic12f1822.h: 3706: } SSP1CON3bits_t;
+[; ;pic12f1822.h: 3707: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1822.h: 3750: typedef union {
+[; ;pic12f1822.h: 3751: struct {
+[; ;pic12f1822.h: 3752: unsigned DHEN :1;
+[; ;pic12f1822.h: 3753: unsigned AHEN :1;
+[; ;pic12f1822.h: 3754: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3755: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3756: unsigned BOEN :1;
+[; ;pic12f1822.h: 3757: unsigned SCIE :1;
+[; ;pic12f1822.h: 3758: unsigned PCIE :1;
+[; ;pic12f1822.h: 3759: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3760: };
+[; ;pic12f1822.h: 3761: } SSPCON3bits_t;
+[; ;pic12f1822.h: 3762: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1822.h: 3806: extern volatile unsigned char CCPR1L @ 0x291;
+"3808
+[; ;pic12f1822.h: 3808: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1822.h: 3811: typedef union {
+[; ;pic12f1822.h: 3812: struct {
+[; ;pic12f1822.h: 3813: unsigned CCPR1L :8;
+[; ;pic12f1822.h: 3814: };
+[; ;pic12f1822.h: 3815: } CCPR1Lbits_t;
+[; ;pic12f1822.h: 3816: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1822.h: 3825: extern volatile unsigned char CCPR1H @ 0x292;
+"3827
+[; ;pic12f1822.h: 3827: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1822.h: 3830: typedef union {
+[; ;pic12f1822.h: 3831: struct {
+[; ;pic12f1822.h: 3832: unsigned CCPR1H :8;
+[; ;pic12f1822.h: 3833: };
+[; ;pic12f1822.h: 3834: } CCPR1Hbits_t;
+[; ;pic12f1822.h: 3835: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1822.h: 3844: extern volatile unsigned char CCP1CON @ 0x293;
+"3846
+[; ;pic12f1822.h: 3846: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1822.h: 3849: typedef union {
+[; ;pic12f1822.h: 3850: struct {
+[; ;pic12f1822.h: 3851: unsigned CCP1M0 :1;
+[; ;pic12f1822.h: 3852: unsigned CCP1M1 :1;
+[; ;pic12f1822.h: 3853: unsigned CCP1M2 :1;
+[; ;pic12f1822.h: 3854: unsigned CCP1M3 :1;
+[; ;pic12f1822.h: 3855: unsigned DC1B0 :1;
+[; ;pic12f1822.h: 3856: unsigned DC1B1 :1;
+[; ;pic12f1822.h: 3857: unsigned P1M0 :1;
+[; ;pic12f1822.h: 3858: unsigned P1M1 :1;
+[; ;pic12f1822.h: 3859: };
+[; ;pic12f1822.h: 3860: struct {
+[; ;pic12f1822.h: 3861: unsigned CCP1M :4;
+[; ;pic12f1822.h: 3862: unsigned DC1B :2;
+[; ;pic12f1822.h: 3863: unsigned P1M :2;
+[; ;pic12f1822.h: 3864: };
+[; ;pic12f1822.h: 3865: } CCP1CONbits_t;
+[; ;pic12f1822.h: 3866: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1822.h: 3925: extern volatile unsigned char PWM1CON @ 0x294;
+"3927
+[; ;pic12f1822.h: 3927: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1822.h: 3930: typedef union {
+[; ;pic12f1822.h: 3931: struct {
+[; ;pic12f1822.h: 3932: unsigned P1DC0 :1;
+[; ;pic12f1822.h: 3933: unsigned P1DC1 :1;
+[; ;pic12f1822.h: 3934: unsigned P1DC2 :1;
+[; ;pic12f1822.h: 3935: unsigned P1DC3 :1;
+[; ;pic12f1822.h: 3936: unsigned P1DC4 :1;
+[; ;pic12f1822.h: 3937: unsigned P1DC5 :1;
+[; ;pic12f1822.h: 3938: unsigned P1DC6 :1;
+[; ;pic12f1822.h: 3939: unsigned P1RSEN :1;
+[; ;pic12f1822.h: 3940: };
+[; ;pic12f1822.h: 3941: struct {
+[; ;pic12f1822.h: 3942: unsigned P1DC :7;
+[; ;pic12f1822.h: 3943: };
+[; ;pic12f1822.h: 3944: } PWM1CONbits_t;
+[; ;pic12f1822.h: 3945: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1822.h: 3994: extern volatile unsigned char CCP1AS @ 0x295;
+"3996
+[; ;pic12f1822.h: 3996: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 3999: extern volatile unsigned char ECCP1AS @ 0x295;
+"4001
+[; ;pic12f1822.h: 4001: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 4004: typedef union {
+[; ;pic12f1822.h: 4005: struct {
+[; ;pic12f1822.h: 4006: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4007: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4008: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4009: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4010: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4011: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4012: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4013: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4014: };
+[; ;pic12f1822.h: 4015: struct {
+[; ;pic12f1822.h: 4016: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4017: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4018: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4019: };
+[; ;pic12f1822.h: 4020: } CCP1ASbits_t;
+[; ;pic12f1822.h: 4021: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4079: typedef union {
+[; ;pic12f1822.h: 4080: struct {
+[; ;pic12f1822.h: 4081: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4082: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4083: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4084: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4085: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4086: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4087: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4088: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4089: };
+[; ;pic12f1822.h: 4090: struct {
+[; ;pic12f1822.h: 4091: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4092: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4093: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4094: };
+[; ;pic12f1822.h: 4095: } ECCP1ASbits_t;
+[; ;pic12f1822.h: 4096: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4155: extern volatile unsigned char PSTR1CON @ 0x296;
+"4157
+[; ;pic12f1822.h: 4157: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1822.h: 4160: typedef union {
+[; ;pic12f1822.h: 4161: struct {
+[; ;pic12f1822.h: 4162: unsigned STR1A :1;
+[; ;pic12f1822.h: 4163: unsigned STR1B :1;
+[; ;pic12f1822.h: 4164: unsigned STR1C :1;
+[; ;pic12f1822.h: 4165: unsigned STR1D :1;
+[; ;pic12f1822.h: 4166: unsigned STR1SYNC :1;
+[; ;pic12f1822.h: 4167: };
+[; ;pic12f1822.h: 4168: } PSTR1CONbits_t;
+[; ;pic12f1822.h: 4169: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1822.h: 4198: extern volatile unsigned char IOCAP @ 0x391;
+"4200
+[; ;pic12f1822.h: 4200: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1822.h: 4203: typedef union {
+[; ;pic12f1822.h: 4204: struct {
+[; ;pic12f1822.h: 4205: unsigned IOCAP0 :1;
+[; ;pic12f1822.h: 4206: unsigned IOCAP1 :1;
+[; ;pic12f1822.h: 4207: unsigned IOCAP2 :1;
+[; ;pic12f1822.h: 4208: unsigned IOCAP3 :1;
+[; ;pic12f1822.h: 4209: unsigned IOCAP4 :1;
+[; ;pic12f1822.h: 4210: unsigned IOCAP5 :1;
+[; ;pic12f1822.h: 4211: };
+[; ;pic12f1822.h: 4212: struct {
+[; ;pic12f1822.h: 4213: unsigned IOCAP :6;
+[; ;pic12f1822.h: 4214: };
+[; ;pic12f1822.h: 4215: } IOCAPbits_t;
+[; ;pic12f1822.h: 4216: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1822.h: 4255: extern volatile unsigned char IOCAN @ 0x392;
+"4257
+[; ;pic12f1822.h: 4257: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1822.h: 4260: typedef union {
+[; ;pic12f1822.h: 4261: struct {
+[; ;pic12f1822.h: 4262: unsigned IOCAN0 :1;
+[; ;pic12f1822.h: 4263: unsigned IOCAN1 :1;
+[; ;pic12f1822.h: 4264: unsigned IOCAN2 :1;
+[; ;pic12f1822.h: 4265: unsigned IOCAN3 :1;
+[; ;pic12f1822.h: 4266: unsigned IOCAN4 :1;
+[; ;pic12f1822.h: 4267: unsigned IOCAN5 :1;
+[; ;pic12f1822.h: 4268: };
+[; ;pic12f1822.h: 4269: struct {
+[; ;pic12f1822.h: 4270: unsigned IOCAN :6;
+[; ;pic12f1822.h: 4271: };
+[; ;pic12f1822.h: 4272: } IOCANbits_t;
+[; ;pic12f1822.h: 4273: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1822.h: 4312: extern volatile unsigned char IOCAF @ 0x393;
+"4314
+[; ;pic12f1822.h: 4314: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1822.h: 4317: typedef union {
+[; ;pic12f1822.h: 4318: struct {
+[; ;pic12f1822.h: 4319: unsigned IOCAF0 :1;
+[; ;pic12f1822.h: 4320: unsigned IOCAF1 :1;
+[; ;pic12f1822.h: 4321: unsigned IOCAF2 :1;
+[; ;pic12f1822.h: 4322: unsigned IOCAF3 :1;
+[; ;pic12f1822.h: 4323: unsigned IOCAF4 :1;
+[; ;pic12f1822.h: 4324: unsigned IOCAF5 :1;
+[; ;pic12f1822.h: 4325: };
+[; ;pic12f1822.h: 4326: struct {
+[; ;pic12f1822.h: 4327: unsigned IOCAF :6;
+[; ;pic12f1822.h: 4328: };
+[; ;pic12f1822.h: 4329: } IOCAFbits_t;
+[; ;pic12f1822.h: 4330: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1822.h: 4369: extern volatile unsigned char CLKRCON @ 0x39A;
+"4371
+[; ;pic12f1822.h: 4371: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1822.h: 4374: typedef union {
+[; ;pic12f1822.h: 4375: struct {
+[; ;pic12f1822.h: 4376: unsigned CLKRDIV0 :1;
+[; ;pic12f1822.h: 4377: unsigned CLKRDIV1 :1;
+[; ;pic12f1822.h: 4378: unsigned CLKRDIV2 :1;
+[; ;pic12f1822.h: 4379: unsigned CLKRDC0 :1;
+[; ;pic12f1822.h: 4380: unsigned CLKRDC1 :1;
+[; ;pic12f1822.h: 4381: unsigned CLKRSLR :1;
+[; ;pic12f1822.h: 4382: unsigned CLKROE :1;
+[; ;pic12f1822.h: 4383: unsigned CLKREN :1;
+[; ;pic12f1822.h: 4384: };
+[; ;pic12f1822.h: 4385: struct {
+[; ;pic12f1822.h: 4386: unsigned CLKRDIV :3;
+[; ;pic12f1822.h: 4387: unsigned CLKRDC :2;
+[; ;pic12f1822.h: 4388: };
+[; ;pic12f1822.h: 4389: } CLKRCONbits_t;
+[; ;pic12f1822.h: 4390: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1822.h: 4444: extern volatile unsigned char MDCON @ 0x39C;
+"4446
+[; ;pic12f1822.h: 4446: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1822.h: 4449: typedef union {
+[; ;pic12f1822.h: 4450: struct {
+[; ;pic12f1822.h: 4451: unsigned MDBIT :1;
+[; ;pic12f1822.h: 4452: unsigned :2;
+[; ;pic12f1822.h: 4453: unsigned MDOUT :1;
+[; ;pic12f1822.h: 4454: unsigned MDOPOL :1;
+[; ;pic12f1822.h: 4455: unsigned MDSLR :1;
+[; ;pic12f1822.h: 4456: unsigned MDOE :1;
+[; ;pic12f1822.h: 4457: unsigned MDEN :1;
+[; ;pic12f1822.h: 4458: };
+[; ;pic12f1822.h: 4459: } MDCONbits_t;
+[; ;pic12f1822.h: 4460: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1822.h: 4494: extern volatile unsigned char MDSRC @ 0x39D;
+"4496
+[; ;pic12f1822.h: 4496: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1822.h: 4499: typedef union {
+[; ;pic12f1822.h: 4500: struct {
+[; ;pic12f1822.h: 4501: unsigned MDMS0 :1;
+[; ;pic12f1822.h: 4502: unsigned MDMS1 :1;
+[; ;pic12f1822.h: 4503: unsigned MDMS2 :1;
+[; ;pic12f1822.h: 4504: unsigned MDMS3 :1;
+[; ;pic12f1822.h: 4505: unsigned :3;
+[; ;pic12f1822.h: 4506: unsigned MDMSODIS :1;
+[; ;pic12f1822.h: 4507: };
+[; ;pic12f1822.h: 4508: struct {
+[; ;pic12f1822.h: 4509: unsigned MDMS :4;
+[; ;pic12f1822.h: 4510: };
+[; ;pic12f1822.h: 4511: } MDSRCbits_t;
+[; ;pic12f1822.h: 4512: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1822.h: 4546: extern volatile unsigned char MDCARL @ 0x39E;
+"4548
+[; ;pic12f1822.h: 4548: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1822.h: 4551: typedef union {
+[; ;pic12f1822.h: 4552: struct {
+[; ;pic12f1822.h: 4553: unsigned MDCL0 :1;
+[; ;pic12f1822.h: 4554: unsigned MDCL1 :1;
+[; ;pic12f1822.h: 4555: unsigned MDCL2 :1;
+[; ;pic12f1822.h: 4556: unsigned MDCL3 :1;
+[; ;pic12f1822.h: 4557: unsigned :1;
+[; ;pic12f1822.h: 4558: unsigned MDCLSYNC :1;
+[; ;pic12f1822.h: 4559: unsigned MDCLPOL :1;
+[; ;pic12f1822.h: 4560: unsigned MDCLODIS :1;
+[; ;pic12f1822.h: 4561: };
+[; ;pic12f1822.h: 4562: struct {
+[; ;pic12f1822.h: 4563: unsigned MDCL :4;
+[; ;pic12f1822.h: 4564: };
+[; ;pic12f1822.h: 4565: } MDCARLbits_t;
+[; ;pic12f1822.h: 4566: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1822.h: 4610: extern volatile unsigned char MDCARH @ 0x39F;
+"4612
+[; ;pic12f1822.h: 4612: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1822.h: 4615: typedef union {
+[; ;pic12f1822.h: 4616: struct {
+[; ;pic12f1822.h: 4617: unsigned MDCH0 :1;
+[; ;pic12f1822.h: 4618: unsigned MDCH1 :1;
+[; ;pic12f1822.h: 4619: unsigned MDCH2 :1;
+[; ;pic12f1822.h: 4620: unsigned MDCH3 :1;
+[; ;pic12f1822.h: 4621: unsigned :1;
+[; ;pic12f1822.h: 4622: unsigned MDCHSYNC :1;
+[; ;pic12f1822.h: 4623: unsigned MDCHPOL :1;
+[; ;pic12f1822.h: 4624: unsigned MDCHODIS :1;
+[; ;pic12f1822.h: 4625: };
+[; ;pic12f1822.h: 4626: struct {
+[; ;pic12f1822.h: 4627: unsigned MDCH :4;
+[; ;pic12f1822.h: 4628: };
+[; ;pic12f1822.h: 4629: } MDCARHbits_t;
+[; ;pic12f1822.h: 4630: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1822.h: 4674: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4676
+[; ;pic12f1822.h: 4676: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1822.h: 4679: typedef union {
+[; ;pic12f1822.h: 4680: struct {
+[; ;pic12f1822.h: 4681: unsigned C_SHAD :1;
+[; ;pic12f1822.h: 4682: unsigned DC_SHAD :1;
+[; ;pic12f1822.h: 4683: unsigned Z_SHAD :1;
+[; ;pic12f1822.h: 4684: };
+[; ;pic12f1822.h: 4685: } STATUS_SHADbits_t;
+[; ;pic12f1822.h: 4686: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1822.h: 4705: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4707
+[; ;pic12f1822.h: 4707: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1822.h: 4710: typedef union {
+[; ;pic12f1822.h: 4711: struct {
+[; ;pic12f1822.h: 4712: unsigned WREG_SHAD :8;
+[; ;pic12f1822.h: 4713: };
+[; ;pic12f1822.h: 4714: } WREG_SHADbits_t;
+[; ;pic12f1822.h: 4715: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1822.h: 4724: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4726
+[; ;pic12f1822.h: 4726: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1822.h: 4729: typedef union {
+[; ;pic12f1822.h: 4730: struct {
+[; ;pic12f1822.h: 4731: unsigned BSR_SHAD :5;
+[; ;pic12f1822.h: 4732: };
+[; ;pic12f1822.h: 4733: } BSR_SHADbits_t;
+[; ;pic12f1822.h: 4734: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1822.h: 4743: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4745
+[; ;pic12f1822.h: 4745: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1822.h: 4748: typedef union {
+[; ;pic12f1822.h: 4749: struct {
+[; ;pic12f1822.h: 4750: unsigned PCLATH_SHAD :7;
+[; ;pic12f1822.h: 4751: };
+[; ;pic12f1822.h: 4752: } PCLATH_SHADbits_t;
+[; ;pic12f1822.h: 4753: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1822.h: 4762: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4764
+[; ;pic12f1822.h: 4764: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1822.h: 4767: typedef union {
+[; ;pic12f1822.h: 4768: struct {
+[; ;pic12f1822.h: 4769: unsigned FSR0L_SHAD :8;
+[; ;pic12f1822.h: 4770: };
+[; ;pic12f1822.h: 4771: } FSR0L_SHADbits_t;
+[; ;pic12f1822.h: 4772: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1822.h: 4781: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4783
+[; ;pic12f1822.h: 4783: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1822.h: 4786: typedef union {
+[; ;pic12f1822.h: 4787: struct {
+[; ;pic12f1822.h: 4788: unsigned FSR0H_SHAD :8;
+[; ;pic12f1822.h: 4789: };
+[; ;pic12f1822.h: 4790: } FSR0H_SHADbits_t;
+[; ;pic12f1822.h: 4791: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1822.h: 4800: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4802
+[; ;pic12f1822.h: 4802: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1822.h: 4805: typedef union {
+[; ;pic12f1822.h: 4806: struct {
+[; ;pic12f1822.h: 4807: unsigned FSR1L_SHAD :8;
+[; ;pic12f1822.h: 4808: };
+[; ;pic12f1822.h: 4809: } FSR1L_SHADbits_t;
+[; ;pic12f1822.h: 4810: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1822.h: 4819: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4821
+[; ;pic12f1822.h: 4821: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1822.h: 4824: typedef union {
+[; ;pic12f1822.h: 4825: struct {
+[; ;pic12f1822.h: 4826: unsigned FSR1H_SHAD :8;
+[; ;pic12f1822.h: 4827: };
+[; ;pic12f1822.h: 4828: } FSR1H_SHADbits_t;
+[; ;pic12f1822.h: 4829: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1822.h: 4838: extern volatile unsigned char STKPTR @ 0xFED;
+"4840
+[; ;pic12f1822.h: 4840: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1822.h: 4843: typedef union {
+[; ;pic12f1822.h: 4844: struct {
+[; ;pic12f1822.h: 4845: unsigned STKPTR :5;
+[; ;pic12f1822.h: 4846: };
+[; ;pic12f1822.h: 4847: } STKPTRbits_t;
+[; ;pic12f1822.h: 4848: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1822.h: 4857: extern volatile unsigned char TOSL @ 0xFEE;
+"4859
+[; ;pic12f1822.h: 4859: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1822.h: 4862: typedef union {
+[; ;pic12f1822.h: 4863: struct {
+[; ;pic12f1822.h: 4864: unsigned TOSL :8;
+[; ;pic12f1822.h: 4865: };
+[; ;pic12f1822.h: 4866: } TOSLbits_t;
+[; ;pic12f1822.h: 4867: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1822.h: 4876: extern volatile unsigned char TOSH @ 0xFEF;
+"4878
+[; ;pic12f1822.h: 4878: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1822.h: 4881: typedef union {
+[; ;pic12f1822.h: 4882: struct {
+[; ;pic12f1822.h: 4883: unsigned TOSH :7;
+[; ;pic12f1822.h: 4884: };
+[; ;pic12f1822.h: 4885: } TOSHbits_t;
+[; ;pic12f1822.h: 4886: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1822.h: 4901: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1822.h: 4903: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1822.h: 4905: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1822.h: 4907: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1822.h: 4909: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1822.h: 4911: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1822.h: 4913: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1822.h: 4915: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1822.h: 4917: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1822.h: 4919: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1822.h: 4921: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1822.h: 4923: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1822.h: 4925: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1822.h: 4927: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 4929: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1822.h: 4931: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1822.h: 4933: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1822.h: 4935: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1822.h: 4937: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1822.h: 4939: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1822.h: 4941: extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4943: extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4945: extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 4947: extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4949: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1822.h: 4951: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1822.h: 4953: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1822.h: 4955: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1822.h: 4957: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1822.h: 4959: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1822.h: 4961: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1822.h: 4963: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1822.h: 4965: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1822.h: 4967: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1822.h: 4969: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1822.h: 4971: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1822.h: 4973: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1822.h: 4975: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1822.h: 4977: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1822.h: 4979: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1822.h: 4981: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1822.h: 4983: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1822.h: 4985: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1822.h: 4987: extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4989: extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4991: extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4993: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1822.h: 4995: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1822.h: 4997: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1822.h: 4999: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1822.h: 5001: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1822.h: 5003: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1822.h: 5005: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1822.h: 5007: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1822.h: 5009: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1822.h: 5011: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1822.h: 5013: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1822.h: 5015: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1822.h: 5017: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1822.h: 5019: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1822.h: 5021: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1822.h: 5023: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1822.h: 5025: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1822.h: 5027: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1822.h: 5029: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1822.h: 5031: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1822.h: 5033: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1822.h: 5035: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1822.h: 5037: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1822.h: 5039: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1822.h: 5041: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1822.h: 5043: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1822.h: 5045: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1822.h: 5047: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1822.h: 5049: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1822.h: 5051: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1822.h: 5053: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1822.h: 5055: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1822.h: 5057: extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5059: extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5061: extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5063: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1822.h: 5065: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1822.h: 5067: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1822.h: 5069: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1822.h: 5071: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1822.h: 5073: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1822.h: 5075: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1822.h: 5077: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1822.h: 5079: extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5081: extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5083: extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5085: extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5087: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1822.h: 5089: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1822.h: 5091: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1822.h: 5093: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1822.h: 5095: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1822.h: 5097: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1822.h: 5099: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1822.h: 5101: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1822.h: 5103: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1822.h: 5105: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1822.h: 5107: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1822.h: 5109: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1822.h: 5111: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1822.h: 5113: extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5115: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1822.h: 5117: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1822.h: 5119: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1822.h: 5121: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1822.h: 5123: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1822.h: 5125: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1822.h: 5127: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1822.h: 5129: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1822.h: 5131: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1822.h: 5133: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1822.h: 5135: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1822.h: 5137: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1822.h: 5139: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1822.h: 5141: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1822.h: 5143: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1822.h: 5145: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1822.h: 5147: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1822.h: 5149: extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5151: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1822.h: 5153: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1822.h: 5155: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1822.h: 5157: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1822.h: 5159: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1822.h: 5161: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5163: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5165: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1822.h: 5167: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1822.h: 5169: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1822.h: 5171: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1822.h: 5173: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1822.h: 5175: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1822.h: 5177: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1822.h: 5179: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1822.h: 5181: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1822.h: 5183: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1822.h: 5185: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1822.h: 5187: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1822.h: 5189: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1822.h: 5191: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1822.h: 5193: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1822.h: 5195: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1822.h: 5197: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1822.h: 5199: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1822.h: 5201: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1822.h: 5203: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1822.h: 5205: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1822.h: 5207: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1822.h: 5209: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1822.h: 5211: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1822.h: 5213: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1822.h: 5215: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1822.h: 5217: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1822.h: 5219: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1822.h: 5221: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1822.h: 5223: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1822.h: 5225: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1822.h: 5227: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1822.h: 5229: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1822.h: 5231: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1822.h: 5233: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1822.h: 5235: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1822.h: 5237: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1822.h: 5239: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1822.h: 5241: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1822.h: 5243: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1822.h: 5245: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1822.h: 5247: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1822.h: 5249: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1822.h: 5251: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1822.h: 5253: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1822.h: 5255: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1822.h: 5257: extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5259: extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5261: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1822.h: 5263: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1822.h: 5265: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1822.h: 5267: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1822.h: 5269: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1822.h: 5271: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1822.h: 5273: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1822.h: 5275: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1822.h: 5277: extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5279: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1822.h: 5281: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1822.h: 5283: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1822.h: 5285: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1822.h: 5287: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1822.h: 5289: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1822.h: 5291: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1822.h: 5293: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1822.h: 5295: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1822.h: 5297: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1822.h: 5299: extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5301: extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5303: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1822.h: 5305: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1822.h: 5307: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1822.h: 5309: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1822.h: 5311: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1822.h: 5313: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1822.h: 5315: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1822.h: 5317: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1822.h: 5319: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1822.h: 5321: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1822.h: 5323: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1822.h: 5325: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1822.h: 5327: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1822.h: 5329: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1822.h: 5331: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1822.h: 5333: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1822.h: 5335: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1822.h: 5337: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1822.h: 5339: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1822.h: 5341: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1822.h: 5343: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1822.h: 5345: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1822.h: 5347: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1822.h: 5349: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1822.h: 5351: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1822.h: 5353: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1822.h: 5355: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5357: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5359: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5361: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5363: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5365: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5367: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1822.h: 5369: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1822.h: 5371: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1822.h: 5373: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1822.h: 5375: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1822.h: 5377: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1822.h: 5379: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1822.h: 5381: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1822.h: 5383: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1822.h: 5385: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1822.h: 5387: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1822.h: 5389: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1822.h: 5391: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1822.h: 5393: extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5395: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1822.h: 5397: extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5399: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1822.h: 5401: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1822.h: 5403: extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5405: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1822.h: 5407: extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5409: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5411: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5413: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1822.h: 5415: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1822.h: 5417: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1822.h: 5419: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1822.h: 5421: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1822.h: 5423: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1822.h: 5425: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1822.h: 5427: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1822.h: 5429: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1822.h: 5431: extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5433: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1822.h: 5435: extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5437: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1822.h: 5439: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1822.h: 5441: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1822.h: 5443: extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5445: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1822.h: 5447: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1822.h: 5449: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1822.h: 5451: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1822.h: 5453: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1822.h: 5455: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1822.h: 5457: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1822.h: 5459: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5461: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1822.h: 5463: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1822.h: 5465: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1822.h: 5467: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1822.h: 5469: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1822.h: 5471: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1822.h: 5473: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1822.h: 5475: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1822.h: 5477: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5479: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1822.h: 5481: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1822.h: 5483: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1822.h: 5485: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1822.h: 5487: extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+[; ;pic12f1822.h: 5489: extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+[; ;pic12f1822.h: 5491: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1822.h: 5493: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1822.h: 5495: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1822.h: 5497: extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5499: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5501: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5503: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5505: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5507: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1822.h: 5509: extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5511: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1822.h: 5513: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1822.h: 5515: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5517: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5519: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1822.h: 5521: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1822.h: 5523: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1822.h: 5525: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1822.h: 5527: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1822.h: 5529: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1822.h: 5531: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1822.h: 5533: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1822.h: 5535: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1822.h: 5537: extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5539: extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5541: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1822.h: 5543: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1822.h: 5545: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1822.h: 5547: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1822.h: 5549: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1822.h: 5551: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1822.h: 5553: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5555: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5557: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5559: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5561: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1822.h: 5563: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1822.h: 5565: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1822.h: 5567: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1822.h: 5569: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1822.h: 5571: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1822.h: 5573: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1822.h: 5575: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1822.h: 5577: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1822.h: 5579: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1822.h: 5581: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1822.h: 5583: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1822.h: 5585: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1822.h: 5587: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1822.h: 5589: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1822.h: 5591: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1822.h: 5593: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1822.h: 5595: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1822.h: 5597: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1822.h: 5599: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1822.h: 5601: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1822.h: 5603: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1822.h: 5605: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1822.h: 5607: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1822.h: 5609: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1822.h: 5611: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1822.h: 5613: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1822.h: 5615: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1822.h: 5617: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1822.h: 5619: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1822.h: 5621: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1822.h: 5623: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1822.h: 5625: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1822.h: 5627: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1822.h: 5629: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1822.h: 5631: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1822.h: 5633: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1822.h: 5635: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1822.h: 5637: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1822.h: 5639: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1822.h: 5641: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1822.h: 5643: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1822.h: 5645: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1822.h: 5647: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1822.h: 5649: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1822.h: 5651: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1822.h: 5653: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1822.h: 5655: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1822.h: 5657: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1822.h: 5659: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1822.h: 5661: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1822.h: 5663: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1822.h: 5665: extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5667: extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5669: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1822.h: 5671: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1822.h: 5673: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1822.h: 5675: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1822.h: 5677: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1822.h: 5679: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1822.h: 5681: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+"37 configuration_bits.c
+[p x FOSC=INTOSC ]
+"38
+[p x WDTE=SWDTEN ]
+"39
+[p x PWRTE=OFF ]
+"40
+[p x MCLRE=OFF ]
+"41
+[p x CP=OFF ]
+"42
+[p x CPD=OFF ]
+"43
+[p x BOREN=ON ]
+"44
+[p x CLKOUTEN=OFF ]
+"45
+[p x IESO=OFF ]
+"46
+[p x FCMEN=ON ]
+"49
+[p x WRT=OFF ]
+"50
+[p x PLLEN=ON ]
+"51
+[p x STVREN=ON ]
+"52
+[p x BORV=LO ]
+"53
+[p x LVP=ON ]

diff --git a/build/XC8_12F1822/production/configuration_bits.p1.d b/build/XC8_12F1822/production/configuration_bits.p1.d
new file mode 100644 (file)
index 0000000..1a51f9b
--- /dev/null
+++ b/build/XC8_12F1822/production/configuration_bits.p1.d
@@ -0,0 +1,3 @@
+ build/XC8_12F1822/production/configuration_bits.d  \
+ build/XC8_12F1822/production/configuration_bits.p1:  \
+ configuration_bits.c 
\ No newline at end of file

diff --git a/build/XC8_12F1822/production/configuration_bits.pre b/build/XC8_12F1822/production/configuration_bits.pre
new file mode 100644 (file)
index 0000000..f5eac0d
--- /dev/null
+++ b/build/XC8_12F1822/production/configuration_bits.pre
@@ -0,0 +1,2851 @@
+
+# 1 "configuration_bits.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1822.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+struct {
+unsigned AN0 :1;
+unsigned AN1 :1;
+unsigned AN2 :1;
+unsigned :1;
+unsigned AN3 :1;
+};
+struct {
+unsigned CPS0 :1;
+unsigned CPS1 :1;
+unsigned CPS2 :1;
+unsigned :1;
+unsigned CPS3 :1;
+};
+struct {
+unsigned C1INP :1;
+unsigned C1IN0N :1;
+unsigned C1OUT :1;
+unsigned :1;
+unsigned C1IN1N :1;
+};
+struct {
+unsigned DACOUT :1;
+unsigned SRI :1;
+unsigned SRQ :1;
+unsigned :2;
+unsigned SRNQ :1;
+};
+struct {
+unsigned :1;
+unsigned SCK :1;
+unsigned T0CKI :1;
+unsigned :1;
+unsigned T1OSO :1;
+unsigned T1CKI :1;
+};
+struct {
+unsigned :1;
+unsigned SCL :1;
+unsigned SDA :1;
+unsigned nMCLR :1;
+unsigned CLKR :1;
+unsigned T1OSI :1;
+};
+struct {
+unsigned MDOUT :1;
+unsigned MDMIN :1;
+unsigned MDCIN1 :1;
+unsigned :1;
+unsigned MDCIN2 :1;
+};
+struct {
+unsigned :2;
+unsigned SDI :1;
+unsigned :1;
+unsigned OSC2 :1;
+unsigned OSC1 :1;
+};
+struct {
+unsigned :2;
+unsigned FLT0 :1;
+unsigned :1;
+unsigned CLKOUT :1;
+unsigned CLKIN :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 698
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 759
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 798
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 817
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 842
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 861
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 932
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 1008
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 1027
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 1046
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 1116
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 1175
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 1208
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1257
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1318
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1357
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1439
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1489
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1547
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1604
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1675
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1736
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1761
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1780
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+struct {
+unsigned :1;
+unsigned nDONE :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1868
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1933
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1977
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 2033
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned :4;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 2086
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 2105
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :6;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 2131
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 2206
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2260
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2311
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2381
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2432
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2507
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2573
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2619
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2644
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2663
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2692
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2706
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2725
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2786
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2805
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2824
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2843
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2866
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2880
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2899
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2960
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 3021
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 3072
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 3129
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 3152
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 3166
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 3189
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 3203
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3226
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3240
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3305
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3361
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3438
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3500
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3564
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3629
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3685
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3750
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3806
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3825
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3844
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3925
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3994
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 4079
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 4155
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned STR1C :1;
+unsigned STR1D :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 4198
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4255
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4312
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4369
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4444
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4494
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4546
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4610
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4674
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4705
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4724
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4743
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4762
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4781
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4800
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4819
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4838
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4857
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4876
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4901
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+
+extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+
+# 37 "configuration_bits.c"
+#pragma config FOSC = INTOSC
+#pragma config WDTE = SWDTEN
+#pragma config PWRTE = OFF
+#pragma config MCLRE = OFF
+#pragma config CP = OFF
+#pragma config CPD = OFF
+#pragma config BOREN = ON
+#pragma config CLKOUTEN = OFF
+#pragma config IESO = OFF
+#pragma config FCMEN = ON
+
+
+#pragma config WRT = OFF
+#pragma config PLLEN = ON
+#pragma config STVREN = ON
+#pragma config BORV = LO
+#pragma config LVP = ON
+

diff --git a/build/XC8_12F1822/production/interrupts.p1 b/build/XC8_12F1822/production/interrupts.p1
new file mode 100644 (file)
index 0000000..f4b2926
--- /dev/null
+++ b/build/XC8_12F1822/production/interrupts.p1
@@ -0,0 +1,2173 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[s S72 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S72 . TMR1IE TMR2IE CCP1IE SSP1IE TXIE RCIE ADIE TMR1GIE ]
+[u S71 `S72 1 ]
+[n S71 . . ]
+"1274 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[v _PIE1bits `VS71 ~T0 @X0 0 e@145 ]
+[s S41 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S41 . TMR1IF TMR2IF CCP1IF SSP1IF TXIF RCIF ADIF TMR1GIF ]
+[u S40 `S41 1 ]
+[n S40 . . ]
+"715
+[v _PIR1bits `VS40 ~T0 @X0 0 e@17 ]
+"17 user.h
+[v _msg_sendnext `(v ~T0 @X0 0 ef ]
+"19
+[v _msg_recvnext `(v ~T0 @X0 0 ef ]
+[; ;pic12f1822.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[; ;pic12f1822.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1822.h: 49: typedef union {
+[; ;pic12f1822.h: 50: struct {
+[; ;pic12f1822.h: 51: unsigned INDF0 :8;
+[; ;pic12f1822.h: 52: };
+[; ;pic12f1822.h: 53: } INDF0bits_t;
+[; ;pic12f1822.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1822.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1822.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1822.h: 68: typedef union {
+[; ;pic12f1822.h: 69: struct {
+[; ;pic12f1822.h: 70: unsigned INDF1 :8;
+[; ;pic12f1822.h: 71: };
+[; ;pic12f1822.h: 72: } INDF1bits_t;
+[; ;pic12f1822.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1822.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1822.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1822.h: 87: typedef union {
+[; ;pic12f1822.h: 88: struct {
+[; ;pic12f1822.h: 89: unsigned PCL :8;
+[; ;pic12f1822.h: 90: };
+[; ;pic12f1822.h: 91: } PCLbits_t;
+[; ;pic12f1822.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1822.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1822.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1822.h: 106: typedef union {
+[; ;pic12f1822.h: 107: struct {
+[; ;pic12f1822.h: 108: unsigned C :1;
+[; ;pic12f1822.h: 109: unsigned DC :1;
+[; ;pic12f1822.h: 110: unsigned Z :1;
+[; ;pic12f1822.h: 111: unsigned nPD :1;
+[; ;pic12f1822.h: 112: unsigned nTO :1;
+[; ;pic12f1822.h: 113: };
+[; ;pic12f1822.h: 114: struct {
+[; ;pic12f1822.h: 115: unsigned CARRY :1;
+[; ;pic12f1822.h: 116: };
+[; ;pic12f1822.h: 117: struct {
+[; ;pic12f1822.h: 118: unsigned :2;
+[; ;pic12f1822.h: 119: unsigned ZERO :1;
+[; ;pic12f1822.h: 120: };
+[; ;pic12f1822.h: 121: } STATUSbits_t;
+[; ;pic12f1822.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1822.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1822.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1822.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1822.h: 169: typedef union {
+[; ;pic12f1822.h: 170: struct {
+[; ;pic12f1822.h: 171: unsigned FSR0L :8;
+[; ;pic12f1822.h: 172: };
+[; ;pic12f1822.h: 173: } FSR0Lbits_t;
+[; ;pic12f1822.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1822.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1822.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1822.h: 188: typedef union {
+[; ;pic12f1822.h: 189: struct {
+[; ;pic12f1822.h: 190: unsigned FSR0H :8;
+[; ;pic12f1822.h: 191: };
+[; ;pic12f1822.h: 192: } FSR0Hbits_t;
+[; ;pic12f1822.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1822.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1822.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1822.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1822.h: 210: typedef union {
+[; ;pic12f1822.h: 211: struct {
+[; ;pic12f1822.h: 212: unsigned FSR1L :8;
+[; ;pic12f1822.h: 213: };
+[; ;pic12f1822.h: 214: } FSR1Lbits_t;
+[; ;pic12f1822.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1822.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1822.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1822.h: 229: typedef union {
+[; ;pic12f1822.h: 230: struct {
+[; ;pic12f1822.h: 231: unsigned FSR1H :8;
+[; ;pic12f1822.h: 232: };
+[; ;pic12f1822.h: 233: } FSR1Hbits_t;
+[; ;pic12f1822.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1822.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1822.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1822.h: 248: typedef union {
+[; ;pic12f1822.h: 249: struct {
+[; ;pic12f1822.h: 250: unsigned BSR0 :1;
+[; ;pic12f1822.h: 251: unsigned BSR1 :1;
+[; ;pic12f1822.h: 252: unsigned BSR2 :1;
+[; ;pic12f1822.h: 253: unsigned BSR3 :1;
+[; ;pic12f1822.h: 254: unsigned BSR4 :1;
+[; ;pic12f1822.h: 255: };
+[; ;pic12f1822.h: 256: struct {
+[; ;pic12f1822.h: 257: unsigned BSR :5;
+[; ;pic12f1822.h: 258: };
+[; ;pic12f1822.h: 259: } BSRbits_t;
+[; ;pic12f1822.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1822.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1822.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1822.h: 299: typedef union {
+[; ;pic12f1822.h: 300: struct {
+[; ;pic12f1822.h: 301: unsigned WREG0 :8;
+[; ;pic12f1822.h: 302: };
+[; ;pic12f1822.h: 303: } WREGbits_t;
+[; ;pic12f1822.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1822.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1822.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1822.h: 318: typedef union {
+[; ;pic12f1822.h: 319: struct {
+[; ;pic12f1822.h: 320: unsigned PCLATH :7;
+[; ;pic12f1822.h: 321: };
+[; ;pic12f1822.h: 322: } PCLATHbits_t;
+[; ;pic12f1822.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1822.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1822.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1822.h: 337: typedef union {
+[; ;pic12f1822.h: 338: struct {
+[; ;pic12f1822.h: 339: unsigned IOCIF :1;
+[; ;pic12f1822.h: 340: unsigned INTF :1;
+[; ;pic12f1822.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1822.h: 342: unsigned IOCIE :1;
+[; ;pic12f1822.h: 343: unsigned INTE :1;
+[; ;pic12f1822.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1822.h: 345: unsigned PEIE :1;
+[; ;pic12f1822.h: 346: unsigned GIE :1;
+[; ;pic12f1822.h: 347: };
+[; ;pic12f1822.h: 348: struct {
+[; ;pic12f1822.h: 349: unsigned :2;
+[; ;pic12f1822.h: 350: unsigned T0IF :1;
+[; ;pic12f1822.h: 351: unsigned :2;
+[; ;pic12f1822.h: 352: unsigned T0IE :1;
+[; ;pic12f1822.h: 353: };
+[; ;pic12f1822.h: 354: } INTCONbits_t;
+[; ;pic12f1822.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1822.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1822.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1822.h: 414: typedef union {
+[; ;pic12f1822.h: 415: struct {
+[; ;pic12f1822.h: 416: unsigned RA0 :1;
+[; ;pic12f1822.h: 417: unsigned RA1 :1;
+[; ;pic12f1822.h: 418: unsigned RA2 :1;
+[; ;pic12f1822.h: 419: unsigned RA3 :1;
+[; ;pic12f1822.h: 420: unsigned RA4 :1;
+[; ;pic12f1822.h: 421: unsigned RA5 :1;
+[; ;pic12f1822.h: 422: };
+[; ;pic12f1822.h: 423: struct {
+[; ;pic12f1822.h: 424: unsigned AN0 :1;
+[; ;pic12f1822.h: 425: unsigned AN1 :1;
+[; ;pic12f1822.h: 426: unsigned AN2 :1;
+[; ;pic12f1822.h: 427: unsigned :1;
+[; ;pic12f1822.h: 428: unsigned AN3 :1;
+[; ;pic12f1822.h: 429: };
+[; ;pic12f1822.h: 430: struct {
+[; ;pic12f1822.h: 431: unsigned CPS0 :1;
+[; ;pic12f1822.h: 432: unsigned CPS1 :1;
+[; ;pic12f1822.h: 433: unsigned CPS2 :1;
+[; ;pic12f1822.h: 434: unsigned :1;
+[; ;pic12f1822.h: 435: unsigned CPS3 :1;
+[; ;pic12f1822.h: 436: };
+[; ;pic12f1822.h: 437: struct {
+[; ;pic12f1822.h: 438: unsigned C1INP :1;
+[; ;pic12f1822.h: 439: unsigned C1IN0N :1;
+[; ;pic12f1822.h: 440: unsigned C1OUT :1;
+[; ;pic12f1822.h: 441: unsigned :1;
+[; ;pic12f1822.h: 442: unsigned C1IN1N :1;
+[; ;pic12f1822.h: 443: };
+[; ;pic12f1822.h: 444: struct {
+[; ;pic12f1822.h: 445: unsigned DACOUT :1;
+[; ;pic12f1822.h: 446: unsigned SRI :1;
+[; ;pic12f1822.h: 447: unsigned SRQ :1;
+[; ;pic12f1822.h: 448: unsigned :2;
+[; ;pic12f1822.h: 449: unsigned SRNQ :1;
+[; ;pic12f1822.h: 450: };
+[; ;pic12f1822.h: 451: struct {
+[; ;pic12f1822.h: 452: unsigned :1;
+[; ;pic12f1822.h: 453: unsigned SCK :1;
+[; ;pic12f1822.h: 454: unsigned T0CKI :1;
+[; ;pic12f1822.h: 455: unsigned :1;
+[; ;pic12f1822.h: 456: unsigned T1OSO :1;
+[; ;pic12f1822.h: 457: unsigned T1CKI :1;
+[; ;pic12f1822.h: 458: };
+[; ;pic12f1822.h: 459: struct {
+[; ;pic12f1822.h: 460: unsigned :1;
+[; ;pic12f1822.h: 461: unsigned SCL :1;
+[; ;pic12f1822.h: 462: unsigned SDA :1;
+[; ;pic12f1822.h: 463: unsigned nMCLR :1;
+[; ;pic12f1822.h: 464: unsigned CLKR :1;
+[; ;pic12f1822.h: 465: unsigned T1OSI :1;
+[; ;pic12f1822.h: 466: };
+[; ;pic12f1822.h: 467: struct {
+[; ;pic12f1822.h: 468: unsigned MDOUT :1;
+[; ;pic12f1822.h: 469: unsigned MDMIN :1;
+[; ;pic12f1822.h: 470: unsigned MDCIN1 :1;
+[; ;pic12f1822.h: 471: unsigned :1;
+[; ;pic12f1822.h: 472: unsigned MDCIN2 :1;
+[; ;pic12f1822.h: 473: };
+[; ;pic12f1822.h: 474: struct {
+[; ;pic12f1822.h: 475: unsigned :2;
+[; ;pic12f1822.h: 476: unsigned SDI :1;
+[; ;pic12f1822.h: 477: unsigned :1;
+[; ;pic12f1822.h: 478: unsigned OSC2 :1;
+[; ;pic12f1822.h: 479: unsigned OSC1 :1;
+[; ;pic12f1822.h: 480: };
+[; ;pic12f1822.h: 481: struct {
+[; ;pic12f1822.h: 482: unsigned :2;
+[; ;pic12f1822.h: 483: unsigned FLT0 :1;
+[; ;pic12f1822.h: 484: unsigned :1;
+[; ;pic12f1822.h: 485: unsigned CLKOUT :1;
+[; ;pic12f1822.h: 486: unsigned CLKIN :1;
+[; ;pic12f1822.h: 487: };
+[; ;pic12f1822.h: 488: } PORTAbits_t;
+[; ;pic12f1822.h: 489: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1822.h: 698: extern volatile unsigned char PIR1 @ 0x011;
+"700
+[; ;pic12f1822.h: 700: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1822.h: 703: typedef union {
+[; ;pic12f1822.h: 704: struct {
+[; ;pic12f1822.h: 705: unsigned TMR1IF :1;
+[; ;pic12f1822.h: 706: unsigned TMR2IF :1;
+[; ;pic12f1822.h: 707: unsigned CCP1IF :1;
+[; ;pic12f1822.h: 708: unsigned SSP1IF :1;
+[; ;pic12f1822.h: 709: unsigned TXIF :1;
+[; ;pic12f1822.h: 710: unsigned RCIF :1;
+[; ;pic12f1822.h: 711: unsigned ADIF :1;
+[; ;pic12f1822.h: 712: unsigned TMR1GIF :1;
+[; ;pic12f1822.h: 713: };
+[; ;pic12f1822.h: 714: } PIR1bits_t;
+[; ;pic12f1822.h: 715: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1822.h: 759: extern volatile unsigned char PIR2 @ 0x012;
+"761
+[; ;pic12f1822.h: 761: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1822.h: 764: typedef union {
+[; ;pic12f1822.h: 765: struct {
+[; ;pic12f1822.h: 766: unsigned :3;
+[; ;pic12f1822.h: 767: unsigned BCL1IF :1;
+[; ;pic12f1822.h: 768: unsigned EEIF :1;
+[; ;pic12f1822.h: 769: unsigned C1IF :1;
+[; ;pic12f1822.h: 770: unsigned :1;
+[; ;pic12f1822.h: 771: unsigned OSFIF :1;
+[; ;pic12f1822.h: 772: };
+[; ;pic12f1822.h: 773: } PIR2bits_t;
+[; ;pic12f1822.h: 774: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1822.h: 798: extern volatile unsigned char TMR0 @ 0x015;
+"800
+[; ;pic12f1822.h: 800: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1822.h: 803: typedef union {
+[; ;pic12f1822.h: 804: struct {
+[; ;pic12f1822.h: 805: unsigned TMR0 :8;
+[; ;pic12f1822.h: 806: };
+[; ;pic12f1822.h: 807: } TMR0bits_t;
+[; ;pic12f1822.h: 808: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1822.h: 817: extern volatile unsigned short TMR1 @ 0x016;
+"819
+[; ;pic12f1822.h: 819: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1822.h: 823: extern volatile unsigned char TMR1L @ 0x016;
+"825
+[; ;pic12f1822.h: 825: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1822.h: 828: typedef union {
+[; ;pic12f1822.h: 829: struct {
+[; ;pic12f1822.h: 830: unsigned TMR1L :8;
+[; ;pic12f1822.h: 831: };
+[; ;pic12f1822.h: 832: } TMR1Lbits_t;
+[; ;pic12f1822.h: 833: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1822.h: 842: extern volatile unsigned char TMR1H @ 0x017;
+"844
+[; ;pic12f1822.h: 844: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1822.h: 847: typedef union {
+[; ;pic12f1822.h: 848: struct {
+[; ;pic12f1822.h: 849: unsigned TMR1H :8;
+[; ;pic12f1822.h: 850: };
+[; ;pic12f1822.h: 851: } TMR1Hbits_t;
+[; ;pic12f1822.h: 852: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1822.h: 861: extern volatile unsigned char T1CON @ 0x018;
+"863
+[; ;pic12f1822.h: 863: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1822.h: 866: typedef union {
+[; ;pic12f1822.h: 867: struct {
+[; ;pic12f1822.h: 868: unsigned TMR1ON :1;
+[; ;pic12f1822.h: 869: unsigned :1;
+[; ;pic12f1822.h: 870: unsigned nT1SYNC :1;
+[; ;pic12f1822.h: 871: unsigned T1OSCEN :1;
+[; ;pic12f1822.h: 872: unsigned T1CKPS0 :1;
+[; ;pic12f1822.h: 873: unsigned T1CKPS1 :1;
+[; ;pic12f1822.h: 874: unsigned TMR1CS0 :1;
+[; ;pic12f1822.h: 875: unsigned TMR1CS1 :1;
+[; ;pic12f1822.h: 876: };
+[; ;pic12f1822.h: 877: struct {
+[; ;pic12f1822.h: 878: unsigned :4;
+[; ;pic12f1822.h: 879: unsigned T1CKPS :2;
+[; ;pic12f1822.h: 880: unsigned TMR1CS :2;
+[; ;pic12f1822.h: 881: };
+[; ;pic12f1822.h: 882: } T1CONbits_t;
+[; ;pic12f1822.h: 883: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1822.h: 932: extern volatile unsigned char T1GCON @ 0x019;
+"934
+[; ;pic12f1822.h: 934: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1822.h: 937: typedef union {
+[; ;pic12f1822.h: 938: struct {
+[; ;pic12f1822.h: 939: unsigned T1GSS0 :1;
+[; ;pic12f1822.h: 940: unsigned T1GSS1 :1;
+[; ;pic12f1822.h: 941: unsigned T1GVAL :1;
+[; ;pic12f1822.h: 942: unsigned T1GGO_nDONE :1;
+[; ;pic12f1822.h: 943: unsigned T1GSPM :1;
+[; ;pic12f1822.h: 944: unsigned T1GTM :1;
+[; ;pic12f1822.h: 945: unsigned T1GPOL :1;
+[; ;pic12f1822.h: 946: unsigned TMR1GE :1;
+[; ;pic12f1822.h: 947: };
+[; ;pic12f1822.h: 948: struct {
+[; ;pic12f1822.h: 949: unsigned T1GSS :2;
+[; ;pic12f1822.h: 950: unsigned :1;
+[; ;pic12f1822.h: 951: unsigned T1GGO :1;
+[; ;pic12f1822.h: 952: };
+[; ;pic12f1822.h: 953: } T1GCONbits_t;
+[; ;pic12f1822.h: 954: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1822.h: 1008: extern volatile unsigned char TMR2 @ 0x01A;
+"1010
+[; ;pic12f1822.h: 1010: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1822.h: 1013: typedef union {
+[; ;pic12f1822.h: 1014: struct {
+[; ;pic12f1822.h: 1015: unsigned TMR2 :8;
+[; ;pic12f1822.h: 1016: };
+[; ;pic12f1822.h: 1017: } TMR2bits_t;
+[; ;pic12f1822.h: 1018: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1822.h: 1027: extern volatile unsigned char PR2 @ 0x01B;
+"1029
+[; ;pic12f1822.h: 1029: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1822.h: 1032: typedef union {
+[; ;pic12f1822.h: 1033: struct {
+[; ;pic12f1822.h: 1034: unsigned PR2 :8;
+[; ;pic12f1822.h: 1035: };
+[; ;pic12f1822.h: 1036: } PR2bits_t;
+[; ;pic12f1822.h: 1037: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1822.h: 1046: extern volatile unsigned char T2CON @ 0x01C;
+"1048
+[; ;pic12f1822.h: 1048: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1822.h: 1051: typedef union {
+[; ;pic12f1822.h: 1052: struct {
+[; ;pic12f1822.h: 1053: unsigned T2CKPS0 :1;
+[; ;pic12f1822.h: 1054: unsigned T2CKPS1 :1;
+[; ;pic12f1822.h: 1055: unsigned TMR2ON :1;
+[; ;pic12f1822.h: 1056: unsigned T2OUTPS0 :1;
+[; ;pic12f1822.h: 1057: unsigned T2OUTPS1 :1;
+[; ;pic12f1822.h: 1058: unsigned T2OUTPS2 :1;
+[; ;pic12f1822.h: 1059: unsigned T2OUTPS3 :1;
+[; ;pic12f1822.h: 1060: };
+[; ;pic12f1822.h: 1061: struct {
+[; ;pic12f1822.h: 1062: unsigned T2CKPS :2;
+[; ;pic12f1822.h: 1063: unsigned :1;
+[; ;pic12f1822.h: 1064: unsigned T2OUTPS :4;
+[; ;pic12f1822.h: 1065: };
+[; ;pic12f1822.h: 1066: } T2CONbits_t;
+[; ;pic12f1822.h: 1067: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1822.h: 1116: extern volatile unsigned char CPSCON0 @ 0x01E;
+"1118
+[; ;pic12f1822.h: 1118: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1822.h: 1121: typedef union {
+[; ;pic12f1822.h: 1122: struct {
+[; ;pic12f1822.h: 1123: unsigned T0XCS :1;
+[; ;pic12f1822.h: 1124: unsigned CPSOUT :1;
+[; ;pic12f1822.h: 1125: unsigned CPSRNG0 :1;
+[; ;pic12f1822.h: 1126: unsigned CPSRNG1 :1;
+[; ;pic12f1822.h: 1127: unsigned :2;
+[; ;pic12f1822.h: 1128: unsigned CPSRM :1;
+[; ;pic12f1822.h: 1129: unsigned CPSON :1;
+[; ;pic12f1822.h: 1130: };
+[; ;pic12f1822.h: 1131: struct {
+[; ;pic12f1822.h: 1132: unsigned :2;
+[; ;pic12f1822.h: 1133: unsigned CPSRNG :2;
+[; ;pic12f1822.h: 1134: };
+[; ;pic12f1822.h: 1135: } CPSCON0bits_t;
+[; ;pic12f1822.h: 1136: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1822.h: 1175: extern volatile unsigned char CPSCON1 @ 0x01F;
+"1177
+[; ;pic12f1822.h: 1177: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1822.h: 1180: typedef union {
+[; ;pic12f1822.h: 1181: struct {
+[; ;pic12f1822.h: 1182: unsigned CPSCH0 :1;
+[; ;pic12f1822.h: 1183: unsigned CPSCH1 :1;
+[; ;pic12f1822.h: 1184: };
+[; ;pic12f1822.h: 1185: struct {
+[; ;pic12f1822.h: 1186: unsigned CPSCH :2;
+[; ;pic12f1822.h: 1187: };
+[; ;pic12f1822.h: 1188: } CPSCON1bits_t;
+[; ;pic12f1822.h: 1189: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1822.h: 1208: extern volatile unsigned char TRISA @ 0x08C;
+"1210
+[; ;pic12f1822.h: 1210: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1822.h: 1213: typedef union {
+[; ;pic12f1822.h: 1214: struct {
+[; ;pic12f1822.h: 1215: unsigned TRISA0 :1;
+[; ;pic12f1822.h: 1216: unsigned TRISA1 :1;
+[; ;pic12f1822.h: 1217: unsigned TRISA2 :1;
+[; ;pic12f1822.h: 1218: unsigned TRISA3 :1;
+[; ;pic12f1822.h: 1219: unsigned TRISA4 :1;
+[; ;pic12f1822.h: 1220: unsigned TRISA5 :1;
+[; ;pic12f1822.h: 1221: };
+[; ;pic12f1822.h: 1222: } TRISAbits_t;
+[; ;pic12f1822.h: 1223: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1822.h: 1257: extern volatile unsigned char PIE1 @ 0x091;
+"1259
+[; ;pic12f1822.h: 1259: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1822.h: 1262: typedef union {
+[; ;pic12f1822.h: 1263: struct {
+[; ;pic12f1822.h: 1264: unsigned TMR1IE :1;
+[; ;pic12f1822.h: 1265: unsigned TMR2IE :1;
+[; ;pic12f1822.h: 1266: unsigned CCP1IE :1;
+[; ;pic12f1822.h: 1267: unsigned SSP1IE :1;
+[; ;pic12f1822.h: 1268: unsigned TXIE :1;
+[; ;pic12f1822.h: 1269: unsigned RCIE :1;
+[; ;pic12f1822.h: 1270: unsigned ADIE :1;
+[; ;pic12f1822.h: 1271: unsigned TMR1GIE :1;
+[; ;pic12f1822.h: 1272: };
+[; ;pic12f1822.h: 1273: } PIE1bits_t;
+[; ;pic12f1822.h: 1274: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1822.h: 1318: extern volatile unsigned char PIE2 @ 0x092;
+"1320
+[; ;pic12f1822.h: 1320: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1822.h: 1323: typedef union {
+[; ;pic12f1822.h: 1324: struct {
+[; ;pic12f1822.h: 1325: unsigned :3;
+[; ;pic12f1822.h: 1326: unsigned BCL1IE :1;
+[; ;pic12f1822.h: 1327: unsigned EEIE :1;
+[; ;pic12f1822.h: 1328: unsigned C1IE :1;
+[; ;pic12f1822.h: 1329: unsigned :1;
+[; ;pic12f1822.h: 1330: unsigned OSFIE :1;
+[; ;pic12f1822.h: 1331: };
+[; ;pic12f1822.h: 1332: } PIE2bits_t;
+[; ;pic12f1822.h: 1333: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1822.h: 1357: extern volatile unsigned char OPTION_REG @ 0x095;
+"1359
+[; ;pic12f1822.h: 1359: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1822.h: 1362: typedef union {
+[; ;pic12f1822.h: 1363: struct {
+[; ;pic12f1822.h: 1364: unsigned PS0 :1;
+[; ;pic12f1822.h: 1365: unsigned PS1 :1;
+[; ;pic12f1822.h: 1366: unsigned PS2 :1;
+[; ;pic12f1822.h: 1367: unsigned PSA :1;
+[; ;pic12f1822.h: 1368: unsigned TMR0SE :1;
+[; ;pic12f1822.h: 1369: unsigned TMR0CS :1;
+[; ;pic12f1822.h: 1370: unsigned INTEDG :1;
+[; ;pic12f1822.h: 1371: unsigned nWPUEN :1;
+[; ;pic12f1822.h: 1372: };
+[; ;pic12f1822.h: 1373: struct {
+[; ;pic12f1822.h: 1374: unsigned PS :3;
+[; ;pic12f1822.h: 1375: unsigned :1;
+[; ;pic12f1822.h: 1376: unsigned T0SE :1;
+[; ;pic12f1822.h: 1377: unsigned T0CS :1;
+[; ;pic12f1822.h: 1378: };
+[; ;pic12f1822.h: 1379: } OPTION_REGbits_t;
+[; ;pic12f1822.h: 1380: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1822.h: 1439: extern volatile unsigned char PCON @ 0x096;
+"1441
+[; ;pic12f1822.h: 1441: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1822.h: 1444: typedef union {
+[; ;pic12f1822.h: 1445: struct {
+[; ;pic12f1822.h: 1446: unsigned nBOR :1;
+[; ;pic12f1822.h: 1447: unsigned nPOR :1;
+[; ;pic12f1822.h: 1448: unsigned nRI :1;
+[; ;pic12f1822.h: 1449: unsigned nRMCLR :1;
+[; ;pic12f1822.h: 1450: unsigned :2;
+[; ;pic12f1822.h: 1451: unsigned STKUNF :1;
+[; ;pic12f1822.h: 1452: unsigned STKOVF :1;
+[; ;pic12f1822.h: 1453: };
+[; ;pic12f1822.h: 1454: } PCONbits_t;
+[; ;pic12f1822.h: 1455: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1822.h: 1489: extern volatile unsigned char WDTCON @ 0x097;
+"1491
+[; ;pic12f1822.h: 1491: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1822.h: 1494: typedef union {
+[; ;pic12f1822.h: 1495: struct {
+[; ;pic12f1822.h: 1496: unsigned SWDTEN :1;
+[; ;pic12f1822.h: 1497: unsigned WDTPS0 :1;
+[; ;pic12f1822.h: 1498: unsigned WDTPS1 :1;
+[; ;pic12f1822.h: 1499: unsigned WDTPS2 :1;
+[; ;pic12f1822.h: 1500: unsigned WDTPS3 :1;
+[; ;pic12f1822.h: 1501: unsigned WDTPS4 :1;
+[; ;pic12f1822.h: 1502: };
+[; ;pic12f1822.h: 1503: struct {
+[; ;pic12f1822.h: 1504: unsigned :1;
+[; ;pic12f1822.h: 1505: unsigned WDTPS :5;
+[; ;pic12f1822.h: 1506: };
+[; ;pic12f1822.h: 1507: } WDTCONbits_t;
+[; ;pic12f1822.h: 1508: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1822.h: 1547: extern volatile unsigned char OSCTUNE @ 0x098;
+"1549
+[; ;pic12f1822.h: 1549: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1822.h: 1552: typedef union {
+[; ;pic12f1822.h: 1553: struct {
+[; ;pic12f1822.h: 1554: unsigned TUN0 :1;
+[; ;pic12f1822.h: 1555: unsigned TUN1 :1;
+[; ;pic12f1822.h: 1556: unsigned TUN2 :1;
+[; ;pic12f1822.h: 1557: unsigned TUN3 :1;
+[; ;pic12f1822.h: 1558: unsigned TUN4 :1;
+[; ;pic12f1822.h: 1559: unsigned TUN5 :1;
+[; ;pic12f1822.h: 1560: };
+[; ;pic12f1822.h: 1561: struct {
+[; ;pic12f1822.h: 1562: unsigned TUN :6;
+[; ;pic12f1822.h: 1563: };
+[; ;pic12f1822.h: 1564: } OSCTUNEbits_t;
+[; ;pic12f1822.h: 1565: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1822.h: 1604: extern volatile unsigned char OSCCON @ 0x099;
+"1606
+[; ;pic12f1822.h: 1606: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1822.h: 1609: typedef union {
+[; ;pic12f1822.h: 1610: struct {
+[; ;pic12f1822.h: 1611: unsigned SCS0 :1;
+[; ;pic12f1822.h: 1612: unsigned SCS1 :1;
+[; ;pic12f1822.h: 1613: unsigned :1;
+[; ;pic12f1822.h: 1614: unsigned IRCF0 :1;
+[; ;pic12f1822.h: 1615: unsigned IRCF1 :1;
+[; ;pic12f1822.h: 1616: unsigned IRCF2 :1;
+[; ;pic12f1822.h: 1617: unsigned IRCF3 :1;
+[; ;pic12f1822.h: 1618: unsigned SPLLEN :1;
+[; ;pic12f1822.h: 1619: };
+[; ;pic12f1822.h: 1620: struct {
+[; ;pic12f1822.h: 1621: unsigned SCS :2;
+[; ;pic12f1822.h: 1622: unsigned :1;
+[; ;pic12f1822.h: 1623: unsigned IRCF :4;
+[; ;pic12f1822.h: 1624: };
+[; ;pic12f1822.h: 1625: } OSCCONbits_t;
+[; ;pic12f1822.h: 1626: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1822.h: 1675: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1677
+[; ;pic12f1822.h: 1677: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1822.h: 1680: typedef union {
+[; ;pic12f1822.h: 1681: struct {
+[; ;pic12f1822.h: 1682: unsigned HFIOFS :1;
+[; ;pic12f1822.h: 1683: unsigned LFIOFR :1;
+[; ;pic12f1822.h: 1684: unsigned MFIOFR :1;
+[; ;pic12f1822.h: 1685: unsigned HFIOFL :1;
+[; ;pic12f1822.h: 1686: unsigned HFIOFR :1;
+[; ;pic12f1822.h: 1687: unsigned OSTS :1;
+[; ;pic12f1822.h: 1688: unsigned PLLR :1;
+[; ;pic12f1822.h: 1689: unsigned T1OSCR :1;
+[; ;pic12f1822.h: 1690: };
+[; ;pic12f1822.h: 1691: } OSCSTATbits_t;
+[; ;pic12f1822.h: 1692: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1822.h: 1736: extern volatile unsigned short ADRES @ 0x09B;
+"1738
+[; ;pic12f1822.h: 1738: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1822.h: 1742: extern volatile unsigned char ADRESL @ 0x09B;
+"1744
+[; ;pic12f1822.h: 1744: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1822.h: 1747: typedef union {
+[; ;pic12f1822.h: 1748: struct {
+[; ;pic12f1822.h: 1749: unsigned ADRESL :8;
+[; ;pic12f1822.h: 1750: };
+[; ;pic12f1822.h: 1751: } ADRESLbits_t;
+[; ;pic12f1822.h: 1752: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1822.h: 1761: extern volatile unsigned char ADRESH @ 0x09C;
+"1763
+[; ;pic12f1822.h: 1763: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1822.h: 1766: typedef union {
+[; ;pic12f1822.h: 1767: struct {
+[; ;pic12f1822.h: 1768: unsigned ADRESH :8;
+[; ;pic12f1822.h: 1769: };
+[; ;pic12f1822.h: 1770: } ADRESHbits_t;
+[; ;pic12f1822.h: 1771: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1822.h: 1780: extern volatile unsigned char ADCON0 @ 0x09D;
+"1782
+[; ;pic12f1822.h: 1782: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1822.h: 1785: typedef union {
+[; ;pic12f1822.h: 1786: struct {
+[; ;pic12f1822.h: 1787: unsigned ADON :1;
+[; ;pic12f1822.h: 1788: unsigned GO_nDONE :1;
+[; ;pic12f1822.h: 1789: unsigned CHS0 :1;
+[; ;pic12f1822.h: 1790: unsigned CHS1 :1;
+[; ;pic12f1822.h: 1791: unsigned CHS2 :1;
+[; ;pic12f1822.h: 1792: unsigned CHS3 :1;
+[; ;pic12f1822.h: 1793: unsigned CHS4 :1;
+[; ;pic12f1822.h: 1794: };
+[; ;pic12f1822.h: 1795: struct {
+[; ;pic12f1822.h: 1796: unsigned :1;
+[; ;pic12f1822.h: 1797: unsigned ADGO :1;
+[; ;pic12f1822.h: 1798: unsigned CHS :5;
+[; ;pic12f1822.h: 1799: };
+[; ;pic12f1822.h: 1800: struct {
+[; ;pic12f1822.h: 1801: unsigned :1;
+[; ;pic12f1822.h: 1802: unsigned GO :1;
+[; ;pic12f1822.h: 1803: };
+[; ;pic12f1822.h: 1804: struct {
+[; ;pic12f1822.h: 1805: unsigned :1;
+[; ;pic12f1822.h: 1806: unsigned nDONE :1;
+[; ;pic12f1822.h: 1807: };
+[; ;pic12f1822.h: 1808: } ADCON0bits_t;
+[; ;pic12f1822.h: 1809: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1822.h: 1868: extern volatile unsigned char ADCON1 @ 0x09E;
+"1870
+[; ;pic12f1822.h: 1870: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1822.h: 1873: typedef union {
+[; ;pic12f1822.h: 1874: struct {
+[; ;pic12f1822.h: 1875: unsigned ADPREF0 :1;
+[; ;pic12f1822.h: 1876: unsigned ADPREF1 :1;
+[; ;pic12f1822.h: 1877: unsigned :2;
+[; ;pic12f1822.h: 1878: unsigned ADCS0 :1;
+[; ;pic12f1822.h: 1879: unsigned ADCS1 :1;
+[; ;pic12f1822.h: 1880: unsigned ADCS2 :1;
+[; ;pic12f1822.h: 1881: unsigned ADFM :1;
+[; ;pic12f1822.h: 1882: };
+[; ;pic12f1822.h: 1883: struct {
+[; ;pic12f1822.h: 1884: unsigned ADPREF :2;
+[; ;pic12f1822.h: 1885: unsigned :2;
+[; ;pic12f1822.h: 1886: unsigned ADCS :3;
+[; ;pic12f1822.h: 1887: };
+[; ;pic12f1822.h: 1888: } ADCON1bits_t;
+[; ;pic12f1822.h: 1889: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1822.h: 1933: extern volatile unsigned char LATA @ 0x10C;
+"1935
+[; ;pic12f1822.h: 1935: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1822.h: 1938: typedef union {
+[; ;pic12f1822.h: 1939: struct {
+[; ;pic12f1822.h: 1940: unsigned LATA0 :1;
+[; ;pic12f1822.h: 1941: unsigned LATA1 :1;
+[; ;pic12f1822.h: 1942: unsigned LATA2 :1;
+[; ;pic12f1822.h: 1943: unsigned :1;
+[; ;pic12f1822.h: 1944: unsigned LATA4 :1;
+[; ;pic12f1822.h: 1945: unsigned LATA5 :1;
+[; ;pic12f1822.h: 1946: };
+[; ;pic12f1822.h: 1947: } LATAbits_t;
+[; ;pic12f1822.h: 1948: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1822.h: 1977: extern volatile unsigned char CM1CON0 @ 0x111;
+"1979
+[; ;pic12f1822.h: 1979: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1822.h: 1982: typedef union {
+[; ;pic12f1822.h: 1983: struct {
+[; ;pic12f1822.h: 1984: unsigned C1SYNC :1;
+[; ;pic12f1822.h: 1985: unsigned C1HYS :1;
+[; ;pic12f1822.h: 1986: unsigned C1SP :1;
+[; ;pic12f1822.h: 1987: unsigned :1;
+[; ;pic12f1822.h: 1988: unsigned C1POL :1;
+[; ;pic12f1822.h: 1989: unsigned C1OE :1;
+[; ;pic12f1822.h: 1990: unsigned C1OUT :1;
+[; ;pic12f1822.h: 1991: unsigned C1ON :1;
+[; ;pic12f1822.h: 1992: };
+[; ;pic12f1822.h: 1993: } CM1CON0bits_t;
+[; ;pic12f1822.h: 1994: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1822.h: 2033: extern volatile unsigned char CM1CON1 @ 0x112;
+"2035
+[; ;pic12f1822.h: 2035: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1822.h: 2038: typedef union {
+[; ;pic12f1822.h: 2039: struct {
+[; ;pic12f1822.h: 2040: unsigned C1NCH0 :1;
+[; ;pic12f1822.h: 2041: unsigned :3;
+[; ;pic12f1822.h: 2042: unsigned C1PCH0 :1;
+[; ;pic12f1822.h: 2043: unsigned C1PCH1 :1;
+[; ;pic12f1822.h: 2044: unsigned C1INTN :1;
+[; ;pic12f1822.h: 2045: unsigned C1INTP :1;
+[; ;pic12f1822.h: 2046: };
+[; ;pic12f1822.h: 2047: struct {
+[; ;pic12f1822.h: 2048: unsigned :4;
+[; ;pic12f1822.h: 2049: unsigned C1PCH :2;
+[; ;pic12f1822.h: 2050: };
+[; ;pic12f1822.h: 2051: } CM1CON1bits_t;
+[; ;pic12f1822.h: 2052: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1822.h: 2086: extern volatile unsigned char CMOUT @ 0x115;
+"2088
+[; ;pic12f1822.h: 2088: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1822.h: 2091: typedef union {
+[; ;pic12f1822.h: 2092: struct {
+[; ;pic12f1822.h: 2093: unsigned MC1OUT :1;
+[; ;pic12f1822.h: 2094: };
+[; ;pic12f1822.h: 2095: } CMOUTbits_t;
+[; ;pic12f1822.h: 2096: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1822.h: 2105: extern volatile unsigned char BORCON @ 0x116;
+"2107
+[; ;pic12f1822.h: 2107: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1822.h: 2110: typedef union {
+[; ;pic12f1822.h: 2111: struct {
+[; ;pic12f1822.h: 2112: unsigned BORRDY :1;
+[; ;pic12f1822.h: 2113: unsigned :6;
+[; ;pic12f1822.h: 2114: unsigned SBOREN :1;
+[; ;pic12f1822.h: 2115: };
+[; ;pic12f1822.h: 2116: } BORCONbits_t;
+[; ;pic12f1822.h: 2117: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1822.h: 2131: extern volatile unsigned char FVRCON @ 0x117;
+"2133
+[; ;pic12f1822.h: 2133: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1822.h: 2136: typedef union {
+[; ;pic12f1822.h: 2137: struct {
+[; ;pic12f1822.h: 2138: unsigned ADFVR0 :1;
+[; ;pic12f1822.h: 2139: unsigned ADFVR1 :1;
+[; ;pic12f1822.h: 2140: unsigned CDAFVR0 :1;
+[; ;pic12f1822.h: 2141: unsigned CDAFVR1 :1;
+[; ;pic12f1822.h: 2142: unsigned TSRNG :1;
+[; ;pic12f1822.h: 2143: unsigned TSEN :1;
+[; ;pic12f1822.h: 2144: unsigned FVRRDY :1;
+[; ;pic12f1822.h: 2145: unsigned FVREN :1;
+[; ;pic12f1822.h: 2146: };
+[; ;pic12f1822.h: 2147: struct {
+[; ;pic12f1822.h: 2148: unsigned ADFVR :2;
+[; ;pic12f1822.h: 2149: unsigned CDAFVR :2;
+[; ;pic12f1822.h: 2150: };
+[; ;pic12f1822.h: 2151: } FVRCONbits_t;
+[; ;pic12f1822.h: 2152: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1822.h: 2206: extern volatile unsigned char DACCON0 @ 0x118;
+"2208
+[; ;pic12f1822.h: 2208: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1822.h: 2211: typedef union {
+[; ;pic12f1822.h: 2212: struct {
+[; ;pic12f1822.h: 2213: unsigned :2;
+[; ;pic12f1822.h: 2214: unsigned DACPSS0 :1;
+[; ;pic12f1822.h: 2215: unsigned DACPSS1 :1;
+[; ;pic12f1822.h: 2216: unsigned :1;
+[; ;pic12f1822.h: 2217: unsigned DACOE :1;
+[; ;pic12f1822.h: 2218: unsigned DACLPS :1;
+[; ;pic12f1822.h: 2219: unsigned DACEN :1;
+[; ;pic12f1822.h: 2220: };
+[; ;pic12f1822.h: 2221: struct {
+[; ;pic12f1822.h: 2222: unsigned :2;
+[; ;pic12f1822.h: 2223: unsigned DACPSS :2;
+[; ;pic12f1822.h: 2224: };
+[; ;pic12f1822.h: 2225: } DACCON0bits_t;
+[; ;pic12f1822.h: 2226: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1822.h: 2260: extern volatile unsigned char DACCON1 @ 0x119;
+"2262
+[; ;pic12f1822.h: 2262: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1822.h: 2265: typedef union {
+[; ;pic12f1822.h: 2266: struct {
+[; ;pic12f1822.h: 2267: unsigned DACR0 :1;
+[; ;pic12f1822.h: 2268: unsigned DACR1 :1;
+[; ;pic12f1822.h: 2269: unsigned DACR2 :1;
+[; ;pic12f1822.h: 2270: unsigned DACR3 :1;
+[; ;pic12f1822.h: 2271: unsigned DACR4 :1;
+[; ;pic12f1822.h: 2272: };
+[; ;pic12f1822.h: 2273: struct {
+[; ;pic12f1822.h: 2274: unsigned DACR :5;
+[; ;pic12f1822.h: 2275: };
+[; ;pic12f1822.h: 2276: } DACCON1bits_t;
+[; ;pic12f1822.h: 2277: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1822.h: 2311: extern volatile unsigned char SRCON0 @ 0x11A;
+"2313
+[; ;pic12f1822.h: 2313: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1822.h: 2316: typedef union {
+[; ;pic12f1822.h: 2317: struct {
+[; ;pic12f1822.h: 2318: unsigned SRPR :1;
+[; ;pic12f1822.h: 2319: unsigned SRPS :1;
+[; ;pic12f1822.h: 2320: unsigned SRNQEN :1;
+[; ;pic12f1822.h: 2321: unsigned SRQEN :1;
+[; ;pic12f1822.h: 2322: unsigned SRCLK0 :1;
+[; ;pic12f1822.h: 2323: unsigned SRCLK1 :1;
+[; ;pic12f1822.h: 2324: unsigned SRCLK2 :1;
+[; ;pic12f1822.h: 2325: unsigned SRLEN :1;
+[; ;pic12f1822.h: 2326: };
+[; ;pic12f1822.h: 2327: struct {
+[; ;pic12f1822.h: 2328: unsigned :4;
+[; ;pic12f1822.h: 2329: unsigned SRCLK :3;
+[; ;pic12f1822.h: 2330: };
+[; ;pic12f1822.h: 2331: } SRCON0bits_t;
+[; ;pic12f1822.h: 2332: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1822.h: 2381: extern volatile unsigned char SRCON1 @ 0x11B;
+"2383
+[; ;pic12f1822.h: 2383: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1822.h: 2386: typedef union {
+[; ;pic12f1822.h: 2387: struct {
+[; ;pic12f1822.h: 2388: unsigned SRRC1E :1;
+[; ;pic12f1822.h: 2389: unsigned :1;
+[; ;pic12f1822.h: 2390: unsigned SRRCKE :1;
+[; ;pic12f1822.h: 2391: unsigned SRRPE :1;
+[; ;pic12f1822.h: 2392: unsigned SRSC1E :1;
+[; ;pic12f1822.h: 2393: unsigned :1;
+[; ;pic12f1822.h: 2394: unsigned SRSCKE :1;
+[; ;pic12f1822.h: 2395: unsigned SRSPE :1;
+[; ;pic12f1822.h: 2396: };
+[; ;pic12f1822.h: 2397: } SRCON1bits_t;
+[; ;pic12f1822.h: 2398: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1822.h: 2432: extern volatile unsigned char APFCON @ 0x11D;
+"2434
+[; ;pic12f1822.h: 2434: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1822.h: 2437: extern volatile unsigned char APFCON0 @ 0x11D;
+"2439
+[; ;pic12f1822.h: 2439: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1822.h: 2442: typedef union {
+[; ;pic12f1822.h: 2443: struct {
+[; ;pic12f1822.h: 2444: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2445: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2446: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2447: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2448: unsigned :1;
+[; ;pic12f1822.h: 2449: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2450: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2451: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2452: };
+[; ;pic12f1822.h: 2453: struct {
+[; ;pic12f1822.h: 2454: unsigned :5;
+[; ;pic12f1822.h: 2455: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2456: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2457: };
+[; ;pic12f1822.h: 2458: } APFCONbits_t;
+[; ;pic12f1822.h: 2459: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1822.h: 2507: typedef union {
+[; ;pic12f1822.h: 2508: struct {
+[; ;pic12f1822.h: 2509: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2510: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2511: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2512: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2513: unsigned :1;
+[; ;pic12f1822.h: 2514: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2515: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2516: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2517: };
+[; ;pic12f1822.h: 2518: struct {
+[; ;pic12f1822.h: 2519: unsigned :5;
+[; ;pic12f1822.h: 2520: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2521: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2522: };
+[; ;pic12f1822.h: 2523: } APFCON0bits_t;
+[; ;pic12f1822.h: 2524: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1822.h: 2573: extern volatile unsigned char ANSELA @ 0x18C;
+"2575
+[; ;pic12f1822.h: 2575: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1822.h: 2578: typedef union {
+[; ;pic12f1822.h: 2579: struct {
+[; ;pic12f1822.h: 2580: unsigned ANSA0 :1;
+[; ;pic12f1822.h: 2581: unsigned ANSA1 :1;
+[; ;pic12f1822.h: 2582: unsigned ANSA2 :1;
+[; ;pic12f1822.h: 2583: unsigned :1;
+[; ;pic12f1822.h: 2584: unsigned ANSA4 :1;
+[; ;pic12f1822.h: 2585: };
+[; ;pic12f1822.h: 2586: struct {
+[; ;pic12f1822.h: 2587: unsigned ANSELA :5;
+[; ;pic12f1822.h: 2588: };
+[; ;pic12f1822.h: 2589: } ANSELAbits_t;
+[; ;pic12f1822.h: 2590: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1822.h: 2619: extern volatile unsigned short EEADR @ 0x191;
+"2621
+[; ;pic12f1822.h: 2621: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1822.h: 2625: extern volatile unsigned char EEADRL @ 0x191;
+"2627
+[; ;pic12f1822.h: 2627: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1822.h: 2630: typedef union {
+[; ;pic12f1822.h: 2631: struct {
+[; ;pic12f1822.h: 2632: unsigned EEADRL :8;
+[; ;pic12f1822.h: 2633: };
+[; ;pic12f1822.h: 2634: } EEADRLbits_t;
+[; ;pic12f1822.h: 2635: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1822.h: 2644: extern volatile unsigned char EEADRH @ 0x192;
+"2646
+[; ;pic12f1822.h: 2646: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1822.h: 2649: typedef union {
+[; ;pic12f1822.h: 2650: struct {
+[; ;pic12f1822.h: 2651: unsigned EEADRH :7;
+[; ;pic12f1822.h: 2652: };
+[; ;pic12f1822.h: 2653: } EEADRHbits_t;
+[; ;pic12f1822.h: 2654: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1822.h: 2663: extern volatile unsigned short EEDAT @ 0x193;
+"2665
+[; ;pic12f1822.h: 2665: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1822.h: 2669: extern volatile unsigned char EEDATL @ 0x193;
+"2671
+[; ;pic12f1822.h: 2671: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1822.h: 2674: extern volatile unsigned char EEDATA @ 0x193;
+"2676
+[; ;pic12f1822.h: 2676: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1822.h: 2679: typedef union {
+[; ;pic12f1822.h: 2680: struct {
+[; ;pic12f1822.h: 2681: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2682: };
+[; ;pic12f1822.h: 2683: } EEDATLbits_t;
+[; ;pic12f1822.h: 2684: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1822.h: 2692: typedef union {
+[; ;pic12f1822.h: 2693: struct {
+[; ;pic12f1822.h: 2694: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2695: };
+[; ;pic12f1822.h: 2696: } EEDATAbits_t;
+[; ;pic12f1822.h: 2697: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1822.h: 2706: extern volatile unsigned char EEDATH @ 0x194;
+"2708
+[; ;pic12f1822.h: 2708: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1822.h: 2711: typedef union {
+[; ;pic12f1822.h: 2712: struct {
+[; ;pic12f1822.h: 2713: unsigned EEDATH :6;
+[; ;pic12f1822.h: 2714: };
+[; ;pic12f1822.h: 2715: } EEDATHbits_t;
+[; ;pic12f1822.h: 2716: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1822.h: 2725: extern volatile unsigned char EECON1 @ 0x195;
+"2727
+[; ;pic12f1822.h: 2727: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1822.h: 2730: typedef union {
+[; ;pic12f1822.h: 2731: struct {
+[; ;pic12f1822.h: 2732: unsigned RD :1;
+[; ;pic12f1822.h: 2733: unsigned WR :1;
+[; ;pic12f1822.h: 2734: unsigned WREN :1;
+[; ;pic12f1822.h: 2735: unsigned WRERR :1;
+[; ;pic12f1822.h: 2736: unsigned FREE :1;
+[; ;pic12f1822.h: 2737: unsigned LWLO :1;
+[; ;pic12f1822.h: 2738: unsigned CFGS :1;
+[; ;pic12f1822.h: 2739: unsigned EEPGD :1;
+[; ;pic12f1822.h: 2740: };
+[; ;pic12f1822.h: 2741: } EECON1bits_t;
+[; ;pic12f1822.h: 2742: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1822.h: 2786: extern volatile unsigned char EECON2 @ 0x196;
+"2788
+[; ;pic12f1822.h: 2788: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1822.h: 2791: typedef union {
+[; ;pic12f1822.h: 2792: struct {
+[; ;pic12f1822.h: 2793: unsigned EECON2 :8;
+[; ;pic12f1822.h: 2794: };
+[; ;pic12f1822.h: 2795: } EECON2bits_t;
+[; ;pic12f1822.h: 2796: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1822.h: 2805: extern volatile unsigned char RCREG @ 0x199;
+"2807
+[; ;pic12f1822.h: 2807: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1822.h: 2810: typedef union {
+[; ;pic12f1822.h: 2811: struct {
+[; ;pic12f1822.h: 2812: unsigned RCREG :8;
+[; ;pic12f1822.h: 2813: };
+[; ;pic12f1822.h: 2814: } RCREGbits_t;
+[; ;pic12f1822.h: 2815: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1822.h: 2824: extern volatile unsigned char TXREG @ 0x19A;
+"2826
+[; ;pic12f1822.h: 2826: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1822.h: 2829: typedef union {
+[; ;pic12f1822.h: 2830: struct {
+[; ;pic12f1822.h: 2831: unsigned TXREG :8;
+[; ;pic12f1822.h: 2832: };
+[; ;pic12f1822.h: 2833: } TXREGbits_t;
+[; ;pic12f1822.h: 2834: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1822.h: 2843: extern volatile unsigned char SPBRGL @ 0x19B;
+"2845
+[; ;pic12f1822.h: 2845: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1822.h: 2848: extern volatile unsigned char SPBRG @ 0x19B;
+"2850
+[; ;pic12f1822.h: 2850: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1822.h: 2853: typedef union {
+[; ;pic12f1822.h: 2854: struct {
+[; ;pic12f1822.h: 2855: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2856: };
+[; ;pic12f1822.h: 2857: } SPBRGLbits_t;
+[; ;pic12f1822.h: 2858: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1822.h: 2866: typedef union {
+[; ;pic12f1822.h: 2867: struct {
+[; ;pic12f1822.h: 2868: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2869: };
+[; ;pic12f1822.h: 2870: } SPBRGbits_t;
+[; ;pic12f1822.h: 2871: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1822.h: 2880: extern volatile unsigned char SPBRGH @ 0x19C;
+"2882
+[; ;pic12f1822.h: 2882: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1822.h: 2885: typedef union {
+[; ;pic12f1822.h: 2886: struct {
+[; ;pic12f1822.h: 2887: unsigned SPBRGH :8;
+[; ;pic12f1822.h: 2888: };
+[; ;pic12f1822.h: 2889: } SPBRGHbits_t;
+[; ;pic12f1822.h: 2890: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1822.h: 2899: extern volatile unsigned char RCSTA @ 0x19D;
+"2901
+[; ;pic12f1822.h: 2901: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1822.h: 2904: typedef union {
+[; ;pic12f1822.h: 2905: struct {
+[; ;pic12f1822.h: 2906: unsigned RX9D :1;
+[; ;pic12f1822.h: 2907: unsigned OERR :1;
+[; ;pic12f1822.h: 2908: unsigned FERR :1;
+[; ;pic12f1822.h: 2909: unsigned ADDEN :1;
+[; ;pic12f1822.h: 2910: unsigned CREN :1;
+[; ;pic12f1822.h: 2911: unsigned SREN :1;
+[; ;pic12f1822.h: 2912: unsigned RX9 :1;
+[; ;pic12f1822.h: 2913: unsigned SPEN :1;
+[; ;pic12f1822.h: 2914: };
+[; ;pic12f1822.h: 2915: } RCSTAbits_t;
+[; ;pic12f1822.h: 2916: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1822.h: 2960: extern volatile unsigned char TXSTA @ 0x19E;
+"2962
+[; ;pic12f1822.h: 2962: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1822.h: 2965: typedef union {
+[; ;pic12f1822.h: 2966: struct {
+[; ;pic12f1822.h: 2967: unsigned TX9D :1;
+[; ;pic12f1822.h: 2968: unsigned TRMT :1;
+[; ;pic12f1822.h: 2969: unsigned BRGH :1;
+[; ;pic12f1822.h: 2970: unsigned SENDB :1;
+[; ;pic12f1822.h: 2971: unsigned SYNC :1;
+[; ;pic12f1822.h: 2972: unsigned TXEN :1;
+[; ;pic12f1822.h: 2973: unsigned TX9 :1;
+[; ;pic12f1822.h: 2974: unsigned CSRC :1;
+[; ;pic12f1822.h: 2975: };
+[; ;pic12f1822.h: 2976: } TXSTAbits_t;
+[; ;pic12f1822.h: 2977: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1822.h: 3021: extern volatile unsigned char BAUDCON @ 0x19F;
+"3023
+[; ;pic12f1822.h: 3023: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1822.h: 3026: typedef union {
+[; ;pic12f1822.h: 3027: struct {
+[; ;pic12f1822.h: 3028: unsigned ABDEN :1;
+[; ;pic12f1822.h: 3029: unsigned WUE :1;
+[; ;pic12f1822.h: 3030: unsigned :1;
+[; ;pic12f1822.h: 3031: unsigned BRG16 :1;
+[; ;pic12f1822.h: 3032: unsigned SCKP :1;
+[; ;pic12f1822.h: 3033: unsigned :1;
+[; ;pic12f1822.h: 3034: unsigned RCIDL :1;
+[; ;pic12f1822.h: 3035: unsigned ABDOVF :1;
+[; ;pic12f1822.h: 3036: };
+[; ;pic12f1822.h: 3037: } BAUDCONbits_t;
+[; ;pic12f1822.h: 3038: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1822.h: 3072: extern volatile unsigned char WPUA @ 0x20C;
+"3074
+[; ;pic12f1822.h: 3074: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1822.h: 3077: typedef union {
+[; ;pic12f1822.h: 3078: struct {
+[; ;pic12f1822.h: 3079: unsigned WPUA0 :1;
+[; ;pic12f1822.h: 3080: unsigned WPUA1 :1;
+[; ;pic12f1822.h: 3081: unsigned WPUA2 :1;
+[; ;pic12f1822.h: 3082: unsigned WPUA3 :1;
+[; ;pic12f1822.h: 3083: unsigned WPUA4 :1;
+[; ;pic12f1822.h: 3084: unsigned WPUA5 :1;
+[; ;pic12f1822.h: 3085: };
+[; ;pic12f1822.h: 3086: struct {
+[; ;pic12f1822.h: 3087: unsigned WPUA :6;
+[; ;pic12f1822.h: 3088: };
+[; ;pic12f1822.h: 3089: } WPUAbits_t;
+[; ;pic12f1822.h: 3090: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1822.h: 3129: extern volatile unsigned char SSP1BUF @ 0x211;
+"3131
+[; ;pic12f1822.h: 3131: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3134: extern volatile unsigned char SSPBUF @ 0x211;
+"3136
+[; ;pic12f1822.h: 3136: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3139: typedef union {
+[; ;pic12f1822.h: 3140: struct {
+[; ;pic12f1822.h: 3141: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3142: };
+[; ;pic12f1822.h: 3143: } SSP1BUFbits_t;
+[; ;pic12f1822.h: 3144: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1822.h: 3152: typedef union {
+[; ;pic12f1822.h: 3153: struct {
+[; ;pic12f1822.h: 3154: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3155: };
+[; ;pic12f1822.h: 3156: } SSPBUFbits_t;
+[; ;pic12f1822.h: 3157: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1822.h: 3166: extern volatile unsigned char SSP1ADD @ 0x212;
+"3168
+[; ;pic12f1822.h: 3168: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3171: extern volatile unsigned char SSPADD @ 0x212;
+"3173
+[; ;pic12f1822.h: 3173: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3176: typedef union {
+[; ;pic12f1822.h: 3177: struct {
+[; ;pic12f1822.h: 3178: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3179: };
+[; ;pic12f1822.h: 3180: } SSP1ADDbits_t;
+[; ;pic12f1822.h: 3181: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1822.h: 3189: typedef union {
+[; ;pic12f1822.h: 3190: struct {
+[; ;pic12f1822.h: 3191: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3192: };
+[; ;pic12f1822.h: 3193: } SSPADDbits_t;
+[; ;pic12f1822.h: 3194: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1822.h: 3203: extern volatile unsigned char SSP1MSK @ 0x213;
+"3205
+[; ;pic12f1822.h: 3205: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3208: extern volatile unsigned char SSPMSK @ 0x213;
+"3210
+[; ;pic12f1822.h: 3210: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3213: typedef union {
+[; ;pic12f1822.h: 3214: struct {
+[; ;pic12f1822.h: 3215: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3216: };
+[; ;pic12f1822.h: 3217: } SSP1MSKbits_t;
+[; ;pic12f1822.h: 3218: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1822.h: 3226: typedef union {
+[; ;pic12f1822.h: 3227: struct {
+[; ;pic12f1822.h: 3228: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3229: };
+[; ;pic12f1822.h: 3230: } SSPMSKbits_t;
+[; ;pic12f1822.h: 3231: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1822.h: 3240: extern volatile unsigned char SSP1STAT @ 0x214;
+"3242
+[; ;pic12f1822.h: 3242: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3245: extern volatile unsigned char SSPSTAT @ 0x214;
+"3247
+[; ;pic12f1822.h: 3247: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3250: typedef union {
+[; ;pic12f1822.h: 3251: struct {
+[; ;pic12f1822.h: 3252: unsigned BF :1;
+[; ;pic12f1822.h: 3253: unsigned UA :1;
+[; ;pic12f1822.h: 3254: unsigned R_nW :1;
+[; ;pic12f1822.h: 3255: unsigned S :1;
+[; ;pic12f1822.h: 3256: unsigned P :1;
+[; ;pic12f1822.h: 3257: unsigned D_nA :1;
+[; ;pic12f1822.h: 3258: unsigned CKE :1;
+[; ;pic12f1822.h: 3259: unsigned SMP :1;
+[; ;pic12f1822.h: 3260: };
+[; ;pic12f1822.h: 3261: } SSP1STATbits_t;
+[; ;pic12f1822.h: 3262: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1822.h: 3305: typedef union {
+[; ;pic12f1822.h: 3306: struct {
+[; ;pic12f1822.h: 3307: unsigned BF :1;
+[; ;pic12f1822.h: 3308: unsigned UA :1;
+[; ;pic12f1822.h: 3309: unsigned R_nW :1;
+[; ;pic12f1822.h: 3310: unsigned S :1;
+[; ;pic12f1822.h: 3311: unsigned P :1;
+[; ;pic12f1822.h: 3312: unsigned D_nA :1;
+[; ;pic12f1822.h: 3313: unsigned CKE :1;
+[; ;pic12f1822.h: 3314: unsigned SMP :1;
+[; ;pic12f1822.h: 3315: };
+[; ;pic12f1822.h: 3316: } SSPSTATbits_t;
+[; ;pic12f1822.h: 3317: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1822.h: 3361: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3363
+[; ;pic12f1822.h: 3363: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3366: extern volatile unsigned char SSPCON1 @ 0x215;
+"3368
+[; ;pic12f1822.h: 3368: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3370: extern volatile unsigned char SSPCON @ 0x215;
+"3372
+[; ;pic12f1822.h: 3372: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1822.h: 3375: typedef union {
+[; ;pic12f1822.h: 3376: struct {
+[; ;pic12f1822.h: 3377: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3378: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3379: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3380: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3381: unsigned CKP :1;
+[; ;pic12f1822.h: 3382: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3383: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3384: unsigned WCOL :1;
+[; ;pic12f1822.h: 3385: };
+[; ;pic12f1822.h: 3386: struct {
+[; ;pic12f1822.h: 3387: unsigned SSPM :4;
+[; ;pic12f1822.h: 3388: };
+[; ;pic12f1822.h: 3389: } SSP1CON1bits_t;
+[; ;pic12f1822.h: 3390: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1822.h: 3438: typedef union {
+[; ;pic12f1822.h: 3439: struct {
+[; ;pic12f1822.h: 3440: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3441: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3442: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3443: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3444: unsigned CKP :1;
+[; ;pic12f1822.h: 3445: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3446: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3447: unsigned WCOL :1;
+[; ;pic12f1822.h: 3448: };
+[; ;pic12f1822.h: 3449: struct {
+[; ;pic12f1822.h: 3450: unsigned SSPM :4;
+[; ;pic12f1822.h: 3451: };
+[; ;pic12f1822.h: 3452: } SSPCON1bits_t;
+[; ;pic12f1822.h: 3453: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1822.h: 3500: typedef union {
+[; ;pic12f1822.h: 3501: struct {
+[; ;pic12f1822.h: 3502: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3503: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3504: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3505: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3506: unsigned CKP :1;
+[; ;pic12f1822.h: 3507: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3508: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3509: unsigned WCOL :1;
+[; ;pic12f1822.h: 3510: };
+[; ;pic12f1822.h: 3511: struct {
+[; ;pic12f1822.h: 3512: unsigned SSPM :4;
+[; ;pic12f1822.h: 3513: };
+[; ;pic12f1822.h: 3514: } SSPCONbits_t;
+[; ;pic12f1822.h: 3515: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1822.h: 3564: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3566
+[; ;pic12f1822.h: 3566: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3569: extern volatile unsigned char SSPCON2 @ 0x216;
+"3571
+[; ;pic12f1822.h: 3571: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3574: typedef union {
+[; ;pic12f1822.h: 3575: struct {
+[; ;pic12f1822.h: 3576: unsigned SEN :1;
+[; ;pic12f1822.h: 3577: unsigned RSEN :1;
+[; ;pic12f1822.h: 3578: unsigned PEN :1;
+[; ;pic12f1822.h: 3579: unsigned RCEN :1;
+[; ;pic12f1822.h: 3580: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3581: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3582: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3583: unsigned GCEN :1;
+[; ;pic12f1822.h: 3584: };
+[; ;pic12f1822.h: 3585: } SSP1CON2bits_t;
+[; ;pic12f1822.h: 3586: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1822.h: 3629: typedef union {
+[; ;pic12f1822.h: 3630: struct {
+[; ;pic12f1822.h: 3631: unsigned SEN :1;
+[; ;pic12f1822.h: 3632: unsigned RSEN :1;
+[; ;pic12f1822.h: 3633: unsigned PEN :1;
+[; ;pic12f1822.h: 3634: unsigned RCEN :1;
+[; ;pic12f1822.h: 3635: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3636: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3637: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3638: unsigned GCEN :1;
+[; ;pic12f1822.h: 3639: };
+[; ;pic12f1822.h: 3640: } SSPCON2bits_t;
+[; ;pic12f1822.h: 3641: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1822.h: 3685: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3687
+[; ;pic12f1822.h: 3687: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3690: extern volatile unsigned char SSPCON3 @ 0x217;
+"3692
+[; ;pic12f1822.h: 3692: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3695: typedef union {
+[; ;pic12f1822.h: 3696: struct {
+[; ;pic12f1822.h: 3697: unsigned DHEN :1;
+[; ;pic12f1822.h: 3698: unsigned AHEN :1;
+[; ;pic12f1822.h: 3699: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3700: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3701: unsigned BOEN :1;
+[; ;pic12f1822.h: 3702: unsigned SCIE :1;
+[; ;pic12f1822.h: 3703: unsigned PCIE :1;
+[; ;pic12f1822.h: 3704: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3705: };
+[; ;pic12f1822.h: 3706: } SSP1CON3bits_t;
+[; ;pic12f1822.h: 3707: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1822.h: 3750: typedef union {
+[; ;pic12f1822.h: 3751: struct {
+[; ;pic12f1822.h: 3752: unsigned DHEN :1;
+[; ;pic12f1822.h: 3753: unsigned AHEN :1;
+[; ;pic12f1822.h: 3754: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3755: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3756: unsigned BOEN :1;
+[; ;pic12f1822.h: 3757: unsigned SCIE :1;
+[; ;pic12f1822.h: 3758: unsigned PCIE :1;
+[; ;pic12f1822.h: 3759: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3760: };
+[; ;pic12f1822.h: 3761: } SSPCON3bits_t;
+[; ;pic12f1822.h: 3762: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1822.h: 3806: extern volatile unsigned char CCPR1L @ 0x291;
+"3808
+[; ;pic12f1822.h: 3808: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1822.h: 3811: typedef union {
+[; ;pic12f1822.h: 3812: struct {
+[; ;pic12f1822.h: 3813: unsigned CCPR1L :8;
+[; ;pic12f1822.h: 3814: };
+[; ;pic12f1822.h: 3815: } CCPR1Lbits_t;
+[; ;pic12f1822.h: 3816: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1822.h: 3825: extern volatile unsigned char CCPR1H @ 0x292;
+"3827
+[; ;pic12f1822.h: 3827: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1822.h: 3830: typedef union {
+[; ;pic12f1822.h: 3831: struct {
+[; ;pic12f1822.h: 3832: unsigned CCPR1H :8;
+[; ;pic12f1822.h: 3833: };
+[; ;pic12f1822.h: 3834: } CCPR1Hbits_t;
+[; ;pic12f1822.h: 3835: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1822.h: 3844: extern volatile unsigned char CCP1CON @ 0x293;
+"3846
+[; ;pic12f1822.h: 3846: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1822.h: 3849: typedef union {
+[; ;pic12f1822.h: 3850: struct {
+[; ;pic12f1822.h: 3851: unsigned CCP1M0 :1;
+[; ;pic12f1822.h: 3852: unsigned CCP1M1 :1;
+[; ;pic12f1822.h: 3853: unsigned CCP1M2 :1;
+[; ;pic12f1822.h: 3854: unsigned CCP1M3 :1;
+[; ;pic12f1822.h: 3855: unsigned DC1B0 :1;
+[; ;pic12f1822.h: 3856: unsigned DC1B1 :1;
+[; ;pic12f1822.h: 3857: unsigned P1M0 :1;
+[; ;pic12f1822.h: 3858: unsigned P1M1 :1;
+[; ;pic12f1822.h: 3859: };
+[; ;pic12f1822.h: 3860: struct {
+[; ;pic12f1822.h: 3861: unsigned CCP1M :4;
+[; ;pic12f1822.h: 3862: unsigned DC1B :2;
+[; ;pic12f1822.h: 3863: unsigned P1M :2;
+[; ;pic12f1822.h: 3864: };
+[; ;pic12f1822.h: 3865: } CCP1CONbits_t;
+[; ;pic12f1822.h: 3866: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1822.h: 3925: extern volatile unsigned char PWM1CON @ 0x294;
+"3927
+[; ;pic12f1822.h: 3927: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1822.h: 3930: typedef union {
+[; ;pic12f1822.h: 3931: struct {
+[; ;pic12f1822.h: 3932: unsigned P1DC0 :1;
+[; ;pic12f1822.h: 3933: unsigned P1DC1 :1;
+[; ;pic12f1822.h: 3934: unsigned P1DC2 :1;
+[; ;pic12f1822.h: 3935: unsigned P1DC3 :1;
+[; ;pic12f1822.h: 3936: unsigned P1DC4 :1;
+[; ;pic12f1822.h: 3937: unsigned P1DC5 :1;
+[; ;pic12f1822.h: 3938: unsigned P1DC6 :1;
+[; ;pic12f1822.h: 3939: unsigned P1RSEN :1;
+[; ;pic12f1822.h: 3940: };
+[; ;pic12f1822.h: 3941: struct {
+[; ;pic12f1822.h: 3942: unsigned P1DC :7;
+[; ;pic12f1822.h: 3943: };
+[; ;pic12f1822.h: 3944: } PWM1CONbits_t;
+[; ;pic12f1822.h: 3945: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1822.h: 3994: extern volatile unsigned char CCP1AS @ 0x295;
+"3996
+[; ;pic12f1822.h: 3996: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 3999: extern volatile unsigned char ECCP1AS @ 0x295;
+"4001
+[; ;pic12f1822.h: 4001: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 4004: typedef union {
+[; ;pic12f1822.h: 4005: struct {
+[; ;pic12f1822.h: 4006: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4007: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4008: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4009: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4010: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4011: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4012: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4013: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4014: };
+[; ;pic12f1822.h: 4015: struct {
+[; ;pic12f1822.h: 4016: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4017: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4018: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4019: };
+[; ;pic12f1822.h: 4020: } CCP1ASbits_t;
+[; ;pic12f1822.h: 4021: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4079: typedef union {
+[; ;pic12f1822.h: 4080: struct {
+[; ;pic12f1822.h: 4081: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4082: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4083: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4084: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4085: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4086: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4087: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4088: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4089: };
+[; ;pic12f1822.h: 4090: struct {
+[; ;pic12f1822.h: 4091: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4092: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4093: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4094: };
+[; ;pic12f1822.h: 4095: } ECCP1ASbits_t;
+[; ;pic12f1822.h: 4096: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4155: extern volatile unsigned char PSTR1CON @ 0x296;
+"4157
+[; ;pic12f1822.h: 4157: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1822.h: 4160: typedef union {
+[; ;pic12f1822.h: 4161: struct {
+[; ;pic12f1822.h: 4162: unsigned STR1A :1;
+[; ;pic12f1822.h: 4163: unsigned STR1B :1;
+[; ;pic12f1822.h: 4164: unsigned STR1C :1;
+[; ;pic12f1822.h: 4165: unsigned STR1D :1;
+[; ;pic12f1822.h: 4166: unsigned STR1SYNC :1;
+[; ;pic12f1822.h: 4167: };
+[; ;pic12f1822.h: 4168: } PSTR1CONbits_t;
+[; ;pic12f1822.h: 4169: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1822.h: 4198: extern volatile unsigned char IOCAP @ 0x391;
+"4200
+[; ;pic12f1822.h: 4200: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1822.h: 4203: typedef union {
+[; ;pic12f1822.h: 4204: struct {
+[; ;pic12f1822.h: 4205: unsigned IOCAP0 :1;
+[; ;pic12f1822.h: 4206: unsigned IOCAP1 :1;
+[; ;pic12f1822.h: 4207: unsigned IOCAP2 :1;
+[; ;pic12f1822.h: 4208: unsigned IOCAP3 :1;
+[; ;pic12f1822.h: 4209: unsigned IOCAP4 :1;
+[; ;pic12f1822.h: 4210: unsigned IOCAP5 :1;
+[; ;pic12f1822.h: 4211: };
+[; ;pic12f1822.h: 4212: struct {
+[; ;pic12f1822.h: 4213: unsigned IOCAP :6;
+[; ;pic12f1822.h: 4214: };
+[; ;pic12f1822.h: 4215: } IOCAPbits_t;
+[; ;pic12f1822.h: 4216: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1822.h: 4255: extern volatile unsigned char IOCAN @ 0x392;
+"4257
+[; ;pic12f1822.h: 4257: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1822.h: 4260: typedef union {
+[; ;pic12f1822.h: 4261: struct {
+[; ;pic12f1822.h: 4262: unsigned IOCAN0 :1;
+[; ;pic12f1822.h: 4263: unsigned IOCAN1 :1;
+[; ;pic12f1822.h: 4264: unsigned IOCAN2 :1;
+[; ;pic12f1822.h: 4265: unsigned IOCAN3 :1;
+[; ;pic12f1822.h: 4266: unsigned IOCAN4 :1;
+[; ;pic12f1822.h: 4267: unsigned IOCAN5 :1;
+[; ;pic12f1822.h: 4268: };
+[; ;pic12f1822.h: 4269: struct {
+[; ;pic12f1822.h: 4270: unsigned IOCAN :6;
+[; ;pic12f1822.h: 4271: };
+[; ;pic12f1822.h: 4272: } IOCANbits_t;
+[; ;pic12f1822.h: 4273: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1822.h: 4312: extern volatile unsigned char IOCAF @ 0x393;
+"4314
+[; ;pic12f1822.h: 4314: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1822.h: 4317: typedef union {
+[; ;pic12f1822.h: 4318: struct {
+[; ;pic12f1822.h: 4319: unsigned IOCAF0 :1;
+[; ;pic12f1822.h: 4320: unsigned IOCAF1 :1;
+[; ;pic12f1822.h: 4321: unsigned IOCAF2 :1;
+[; ;pic12f1822.h: 4322: unsigned IOCAF3 :1;
+[; ;pic12f1822.h: 4323: unsigned IOCAF4 :1;
+[; ;pic12f1822.h: 4324: unsigned IOCAF5 :1;
+[; ;pic12f1822.h: 4325: };
+[; ;pic12f1822.h: 4326: struct {
+[; ;pic12f1822.h: 4327: unsigned IOCAF :6;
+[; ;pic12f1822.h: 4328: };
+[; ;pic12f1822.h: 4329: } IOCAFbits_t;
+[; ;pic12f1822.h: 4330: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1822.h: 4369: extern volatile unsigned char CLKRCON @ 0x39A;
+"4371
+[; ;pic12f1822.h: 4371: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1822.h: 4374: typedef union {
+[; ;pic12f1822.h: 4375: struct {
+[; ;pic12f1822.h: 4376: unsigned CLKRDIV0 :1;
+[; ;pic12f1822.h: 4377: unsigned CLKRDIV1 :1;
+[; ;pic12f1822.h: 4378: unsigned CLKRDIV2 :1;
+[; ;pic12f1822.h: 4379: unsigned CLKRDC0 :1;
+[; ;pic12f1822.h: 4380: unsigned CLKRDC1 :1;
+[; ;pic12f1822.h: 4381: unsigned CLKRSLR :1;
+[; ;pic12f1822.h: 4382: unsigned CLKROE :1;
+[; ;pic12f1822.h: 4383: unsigned CLKREN :1;
+[; ;pic12f1822.h: 4384: };
+[; ;pic12f1822.h: 4385: struct {
+[; ;pic12f1822.h: 4386: unsigned CLKRDIV :3;
+[; ;pic12f1822.h: 4387: unsigned CLKRDC :2;
+[; ;pic12f1822.h: 4388: };
+[; ;pic12f1822.h: 4389: } CLKRCONbits_t;
+[; ;pic12f1822.h: 4390: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1822.h: 4444: extern volatile unsigned char MDCON @ 0x39C;
+"4446
+[; ;pic12f1822.h: 4446: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1822.h: 4449: typedef union {
+[; ;pic12f1822.h: 4450: struct {
+[; ;pic12f1822.h: 4451: unsigned MDBIT :1;
+[; ;pic12f1822.h: 4452: unsigned :2;
+[; ;pic12f1822.h: 4453: unsigned MDOUT :1;
+[; ;pic12f1822.h: 4454: unsigned MDOPOL :1;
+[; ;pic12f1822.h: 4455: unsigned MDSLR :1;
+[; ;pic12f1822.h: 4456: unsigned MDOE :1;
+[; ;pic12f1822.h: 4457: unsigned MDEN :1;
+[; ;pic12f1822.h: 4458: };
+[; ;pic12f1822.h: 4459: } MDCONbits_t;
+[; ;pic12f1822.h: 4460: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1822.h: 4494: extern volatile unsigned char MDSRC @ 0x39D;
+"4496
+[; ;pic12f1822.h: 4496: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1822.h: 4499: typedef union {
+[; ;pic12f1822.h: 4500: struct {
+[; ;pic12f1822.h: 4501: unsigned MDMS0 :1;
+[; ;pic12f1822.h: 4502: unsigned MDMS1 :1;
+[; ;pic12f1822.h: 4503: unsigned MDMS2 :1;
+[; ;pic12f1822.h: 4504: unsigned MDMS3 :1;
+[; ;pic12f1822.h: 4505: unsigned :3;
+[; ;pic12f1822.h: 4506: unsigned MDMSODIS :1;
+[; ;pic12f1822.h: 4507: };
+[; ;pic12f1822.h: 4508: struct {
+[; ;pic12f1822.h: 4509: unsigned MDMS :4;
+[; ;pic12f1822.h: 4510: };
+[; ;pic12f1822.h: 4511: } MDSRCbits_t;
+[; ;pic12f1822.h: 4512: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1822.h: 4546: extern volatile unsigned char MDCARL @ 0x39E;
+"4548
+[; ;pic12f1822.h: 4548: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1822.h: 4551: typedef union {
+[; ;pic12f1822.h: 4552: struct {
+[; ;pic12f1822.h: 4553: unsigned MDCL0 :1;
+[; ;pic12f1822.h: 4554: unsigned MDCL1 :1;
+[; ;pic12f1822.h: 4555: unsigned MDCL2 :1;
+[; ;pic12f1822.h: 4556: unsigned MDCL3 :1;
+[; ;pic12f1822.h: 4557: unsigned :1;
+[; ;pic12f1822.h: 4558: unsigned MDCLSYNC :1;
+[; ;pic12f1822.h: 4559: unsigned MDCLPOL :1;
+[; ;pic12f1822.h: 4560: unsigned MDCLODIS :1;
+[; ;pic12f1822.h: 4561: };
+[; ;pic12f1822.h: 4562: struct {
+[; ;pic12f1822.h: 4563: unsigned MDCL :4;
+[; ;pic12f1822.h: 4564: };
+[; ;pic12f1822.h: 4565: } MDCARLbits_t;
+[; ;pic12f1822.h: 4566: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1822.h: 4610: extern volatile unsigned char MDCARH @ 0x39F;
+"4612
+[; ;pic12f1822.h: 4612: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1822.h: 4615: typedef union {
+[; ;pic12f1822.h: 4616: struct {
+[; ;pic12f1822.h: 4617: unsigned MDCH0 :1;
+[; ;pic12f1822.h: 4618: unsigned MDCH1 :1;
+[; ;pic12f1822.h: 4619: unsigned MDCH2 :1;
+[; ;pic12f1822.h: 4620: unsigned MDCH3 :1;
+[; ;pic12f1822.h: 4621: unsigned :1;
+[; ;pic12f1822.h: 4622: unsigned MDCHSYNC :1;
+[; ;pic12f1822.h: 4623: unsigned MDCHPOL :1;
+[; ;pic12f1822.h: 4624: unsigned MDCHODIS :1;
+[; ;pic12f1822.h: 4625: };
+[; ;pic12f1822.h: 4626: struct {
+[; ;pic12f1822.h: 4627: unsigned MDCH :4;
+[; ;pic12f1822.h: 4628: };
+[; ;pic12f1822.h: 4629: } MDCARHbits_t;
+[; ;pic12f1822.h: 4630: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1822.h: 4674: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4676
+[; ;pic12f1822.h: 4676: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1822.h: 4679: typedef union {
+[; ;pic12f1822.h: 4680: struct {
+[; ;pic12f1822.h: 4681: unsigned C_SHAD :1;
+[; ;pic12f1822.h: 4682: unsigned DC_SHAD :1;
+[; ;pic12f1822.h: 4683: unsigned Z_SHAD :1;
+[; ;pic12f1822.h: 4684: };
+[; ;pic12f1822.h: 4685: } STATUS_SHADbits_t;
+[; ;pic12f1822.h: 4686: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1822.h: 4705: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4707
+[; ;pic12f1822.h: 4707: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1822.h: 4710: typedef union {
+[; ;pic12f1822.h: 4711: struct {
+[; ;pic12f1822.h: 4712: unsigned WREG_SHAD :8;
+[; ;pic12f1822.h: 4713: };
+[; ;pic12f1822.h: 4714: } WREG_SHADbits_t;
+[; ;pic12f1822.h: 4715: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1822.h: 4724: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4726
+[; ;pic12f1822.h: 4726: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1822.h: 4729: typedef union {
+[; ;pic12f1822.h: 4730: struct {
+[; ;pic12f1822.h: 4731: unsigned BSR_SHAD :5;
+[; ;pic12f1822.h: 4732: };
+[; ;pic12f1822.h: 4733: } BSR_SHADbits_t;
+[; ;pic12f1822.h: 4734: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1822.h: 4743: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4745
+[; ;pic12f1822.h: 4745: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1822.h: 4748: typedef union {
+[; ;pic12f1822.h: 4749: struct {
+[; ;pic12f1822.h: 4750: unsigned PCLATH_SHAD :7;
+[; ;pic12f1822.h: 4751: };
+[; ;pic12f1822.h: 4752: } PCLATH_SHADbits_t;
+[; ;pic12f1822.h: 4753: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1822.h: 4762: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4764
+[; ;pic12f1822.h: 4764: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1822.h: 4767: typedef union {
+[; ;pic12f1822.h: 4768: struct {
+[; ;pic12f1822.h: 4769: unsigned FSR0L_SHAD :8;
+[; ;pic12f1822.h: 4770: };
+[; ;pic12f1822.h: 4771: } FSR0L_SHADbits_t;
+[; ;pic12f1822.h: 4772: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1822.h: 4781: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4783
+[; ;pic12f1822.h: 4783: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1822.h: 4786: typedef union {
+[; ;pic12f1822.h: 4787: struct {
+[; ;pic12f1822.h: 4788: unsigned FSR0H_SHAD :8;
+[; ;pic12f1822.h: 4789: };
+[; ;pic12f1822.h: 4790: } FSR0H_SHADbits_t;
+[; ;pic12f1822.h: 4791: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1822.h: 4800: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4802
+[; ;pic12f1822.h: 4802: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1822.h: 4805: typedef union {
+[; ;pic12f1822.h: 4806: struct {
+[; ;pic12f1822.h: 4807: unsigned FSR1L_SHAD :8;
+[; ;pic12f1822.h: 4808: };
+[; ;pic12f1822.h: 4809: } FSR1L_SHADbits_t;
+[; ;pic12f1822.h: 4810: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1822.h: 4819: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4821
+[; ;pic12f1822.h: 4821: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1822.h: 4824: typedef union {
+[; ;pic12f1822.h: 4825: struct {
+[; ;pic12f1822.h: 4826: unsigned FSR1H_SHAD :8;
+[; ;pic12f1822.h: 4827: };
+[; ;pic12f1822.h: 4828: } FSR1H_SHADbits_t;
+[; ;pic12f1822.h: 4829: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1822.h: 4838: extern volatile unsigned char STKPTR @ 0xFED;
+"4840
+[; ;pic12f1822.h: 4840: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1822.h: 4843: typedef union {
+[; ;pic12f1822.h: 4844: struct {
+[; ;pic12f1822.h: 4845: unsigned STKPTR :5;
+[; ;pic12f1822.h: 4846: };
+[; ;pic12f1822.h: 4847: } STKPTRbits_t;
+[; ;pic12f1822.h: 4848: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1822.h: 4857: extern volatile unsigned char TOSL @ 0xFEE;
+"4859
+[; ;pic12f1822.h: 4859: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1822.h: 4862: typedef union {
+[; ;pic12f1822.h: 4863: struct {
+[; ;pic12f1822.h: 4864: unsigned TOSL :8;
+[; ;pic12f1822.h: 4865: };
+[; ;pic12f1822.h: 4866: } TOSLbits_t;
+[; ;pic12f1822.h: 4867: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1822.h: 4876: extern volatile unsigned char TOSH @ 0xFEF;
+"4878
+[; ;pic12f1822.h: 4878: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1822.h: 4881: typedef union {
+[; ;pic12f1822.h: 4882: struct {
+[; ;pic12f1822.h: 4883: unsigned TOSH :7;
+[; ;pic12f1822.h: 4884: };
+[; ;pic12f1822.h: 4885: } TOSHbits_t;
+[; ;pic12f1822.h: 4886: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1822.h: 4901: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1822.h: 4903: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1822.h: 4905: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1822.h: 4907: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1822.h: 4909: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1822.h: 4911: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1822.h: 4913: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1822.h: 4915: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1822.h: 4917: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1822.h: 4919: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1822.h: 4921: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1822.h: 4923: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1822.h: 4925: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1822.h: 4927: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 4929: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1822.h: 4931: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1822.h: 4933: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1822.h: 4935: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1822.h: 4937: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1822.h: 4939: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1822.h: 4941: extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4943: extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4945: extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 4947: extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4949: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1822.h: 4951: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1822.h: 4953: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1822.h: 4955: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1822.h: 4957: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1822.h: 4959: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1822.h: 4961: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1822.h: 4963: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1822.h: 4965: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1822.h: 4967: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1822.h: 4969: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1822.h: 4971: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1822.h: 4973: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1822.h: 4975: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1822.h: 4977: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1822.h: 4979: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1822.h: 4981: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1822.h: 4983: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1822.h: 4985: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1822.h: 4987: extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4989: extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4991: extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4993: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1822.h: 4995: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1822.h: 4997: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1822.h: 4999: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1822.h: 5001: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1822.h: 5003: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1822.h: 5005: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1822.h: 5007: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1822.h: 5009: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1822.h: 5011: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1822.h: 5013: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1822.h: 5015: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1822.h: 5017: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1822.h: 5019: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1822.h: 5021: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1822.h: 5023: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1822.h: 5025: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1822.h: 5027: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1822.h: 5029: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1822.h: 5031: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1822.h: 5033: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1822.h: 5035: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1822.h: 5037: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1822.h: 5039: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1822.h: 5041: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1822.h: 5043: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1822.h: 5045: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1822.h: 5047: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1822.h: 5049: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1822.h: 5051: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1822.h: 5053: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1822.h: 5055: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1822.h: 5057: extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5059: extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5061: extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5063: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1822.h: 5065: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1822.h: 5067: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1822.h: 5069: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1822.h: 5071: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1822.h: 5073: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1822.h: 5075: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1822.h: 5077: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1822.h: 5079: extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5081: extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5083: extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5085: extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5087: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1822.h: 5089: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1822.h: 5091: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1822.h: 5093: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1822.h: 5095: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1822.h: 5097: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1822.h: 5099: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1822.h: 5101: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1822.h: 5103: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1822.h: 5105: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1822.h: 5107: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1822.h: 5109: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1822.h: 5111: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1822.h: 5113: extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5115: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1822.h: 5117: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1822.h: 5119: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1822.h: 5121: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1822.h: 5123: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1822.h: 5125: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1822.h: 5127: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1822.h: 5129: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1822.h: 5131: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1822.h: 5133: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1822.h: 5135: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1822.h: 5137: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1822.h: 5139: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1822.h: 5141: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1822.h: 5143: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1822.h: 5145: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1822.h: 5147: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1822.h: 5149: extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5151: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1822.h: 5153: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1822.h: 5155: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1822.h: 5157: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1822.h: 5159: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1822.h: 5161: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5163: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5165: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1822.h: 5167: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1822.h: 5169: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1822.h: 5171: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1822.h: 5173: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1822.h: 5175: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1822.h: 5177: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1822.h: 5179: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1822.h: 5181: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1822.h: 5183: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1822.h: 5185: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1822.h: 5187: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1822.h: 5189: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1822.h: 5191: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1822.h: 5193: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1822.h: 5195: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1822.h: 5197: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1822.h: 5199: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1822.h: 5201: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1822.h: 5203: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1822.h: 5205: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1822.h: 5207: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1822.h: 5209: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1822.h: 5211: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1822.h: 5213: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1822.h: 5215: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1822.h: 5217: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1822.h: 5219: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1822.h: 5221: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1822.h: 5223: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1822.h: 5225: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1822.h: 5227: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1822.h: 5229: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1822.h: 5231: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1822.h: 5233: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1822.h: 5235: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1822.h: 5237: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1822.h: 5239: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1822.h: 5241: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1822.h: 5243: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1822.h: 5245: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1822.h: 5247: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1822.h: 5249: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1822.h: 5251: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1822.h: 5253: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1822.h: 5255: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1822.h: 5257: extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5259: extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5261: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1822.h: 5263: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1822.h: 5265: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1822.h: 5267: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1822.h: 5269: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1822.h: 5271: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1822.h: 5273: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1822.h: 5275: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1822.h: 5277: extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5279: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1822.h: 5281: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1822.h: 5283: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1822.h: 5285: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1822.h: 5287: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1822.h: 5289: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1822.h: 5291: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1822.h: 5293: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1822.h: 5295: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1822.h: 5297: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1822.h: 5299: extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5301: extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5303: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1822.h: 5305: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1822.h: 5307: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1822.h: 5309: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1822.h: 5311: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1822.h: 5313: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1822.h: 5315: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1822.h: 5317: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1822.h: 5319: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1822.h: 5321: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1822.h: 5323: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1822.h: 5325: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1822.h: 5327: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1822.h: 5329: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1822.h: 5331: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1822.h: 5333: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1822.h: 5335: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1822.h: 5337: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1822.h: 5339: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1822.h: 5341: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1822.h: 5343: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1822.h: 5345: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1822.h: 5347: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1822.h: 5349: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1822.h: 5351: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1822.h: 5353: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1822.h: 5355: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5357: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5359: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5361: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5363: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5365: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5367: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1822.h: 5369: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1822.h: 5371: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1822.h: 5373: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1822.h: 5375: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1822.h: 5377: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1822.h: 5379: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1822.h: 5381: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1822.h: 5383: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1822.h: 5385: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1822.h: 5387: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1822.h: 5389: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1822.h: 5391: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1822.h: 5393: extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5395: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1822.h: 5397: extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5399: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1822.h: 5401: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1822.h: 5403: extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5405: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1822.h: 5407: extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5409: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5411: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5413: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1822.h: 5415: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1822.h: 5417: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1822.h: 5419: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1822.h: 5421: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1822.h: 5423: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1822.h: 5425: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1822.h: 5427: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1822.h: 5429: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1822.h: 5431: extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5433: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1822.h: 5435: extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5437: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1822.h: 5439: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1822.h: 5441: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1822.h: 5443: extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5445: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1822.h: 5447: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1822.h: 5449: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1822.h: 5451: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1822.h: 5453: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1822.h: 5455: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1822.h: 5457: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1822.h: 5459: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5461: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1822.h: 5463: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1822.h: 5465: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1822.h: 5467: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1822.h: 5469: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1822.h: 5471: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1822.h: 5473: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1822.h: 5475: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1822.h: 5477: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5479: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1822.h: 5481: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1822.h: 5483: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1822.h: 5485: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1822.h: 5487: extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+[; ;pic12f1822.h: 5489: extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+[; ;pic12f1822.h: 5491: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1822.h: 5493: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1822.h: 5495: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1822.h: 5497: extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5499: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5501: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5503: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5505: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5507: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1822.h: 5509: extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5511: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1822.h: 5513: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1822.h: 5515: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5517: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5519: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1822.h: 5521: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1822.h: 5523: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1822.h: 5525: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1822.h: 5527: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1822.h: 5529: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1822.h: 5531: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1822.h: 5533: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1822.h: 5535: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1822.h: 5537: extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5539: extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5541: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1822.h: 5543: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1822.h: 5545: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1822.h: 5547: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1822.h: 5549: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1822.h: 5551: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1822.h: 5553: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5555: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5557: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5559: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5561: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1822.h: 5563: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1822.h: 5565: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1822.h: 5567: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1822.h: 5569: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1822.h: 5571: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1822.h: 5573: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1822.h: 5575: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1822.h: 5577: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1822.h: 5579: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1822.h: 5581: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1822.h: 5583: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1822.h: 5585: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1822.h: 5587: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1822.h: 5589: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1822.h: 5591: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1822.h: 5593: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1822.h: 5595: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1822.h: 5597: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1822.h: 5599: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1822.h: 5601: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1822.h: 5603: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1822.h: 5605: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1822.h: 5607: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1822.h: 5609: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1822.h: 5611: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1822.h: 5613: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1822.h: 5615: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1822.h: 5617: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1822.h: 5619: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1822.h: 5621: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1822.h: 5623: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1822.h: 5625: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1822.h: 5627: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1822.h: 5629: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1822.h: 5631: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1822.h: 5633: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1822.h: 5635: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1822.h: 5637: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1822.h: 5639: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1822.h: 5641: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1822.h: 5643: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1822.h: 5645: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1822.h: 5647: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1822.h: 5649: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1822.h: 5651: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1822.h: 5653: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1822.h: 5655: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1822.h: 5657: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1822.h: 5659: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1822.h: 5661: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1822.h: 5663: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1822.h: 5665: extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5667: extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5669: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1822.h: 5671: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1822.h: 5673: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1822.h: 5675: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1822.h: 5677: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1822.h: 5679: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1822.h: 5681: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+[; ;user.h: 13: void InitApp(void);
+[; ;user.h: 14: bool msg_empty(void);
+[; ;user.h: 15: void msg_write(const char *msg);
+[; ;user.h: 16: void msg_writebyte(const char msg);
+[; ;user.h: 17: void msg_sendnext(void);
+[; ;user.h: 18: void tohex(char val[3], char i);
+[; ;user.h: 19: void msg_recvnext(void);
+[; ;user.h: 20: bool msg_recvready(void);
+[; ;user.h: 21: char msg_recv(void);
+[; ;user.h: 22: void putch(char);
+[; ;user.h: 24: void int_disable(void);
+[; ;user.h: 25: void int_enable(void);
+"25 interrupts.c
+[v F2213 `(v ~T0 @X0 1 tf ]
+[v _isr `IF2213 ~T0 @X0 1 e ]
+{
+[; ;interrupts.c: 24: void interrupt isr(void)
+[; ;interrupts.c: 25: {
+[e :U _isr ]
+[f ]
+[; ;interrupts.c: 31: if (PIE1bits.TXIE && PIR1bits.TXIF)
+"31
+[e $ ! && != -> . . _PIE1bits 0 4 `i -> -> -> 0 `i `Vuc `i != -> . . _PIR1bits 0 4 `i -> -> -> 0 `i `Vuc `i 267  ]
+[; ;interrupts.c: 32: msg_sendnext();
+"32
+[e ( _msg_sendnext ..  ]
+[e :U 267 ]
+[; ;interrupts.c: 34: if (PIE1bits.RCIE && PIR1bits.RCIF)
+"34
+[e $ ! && != -> . . _PIE1bits 0 5 `i -> -> -> 0 `i `Vuc `i != -> . . _PIR1bits 0 5 `i -> -> -> 0 `i `Vuc `i 268  ]
+[; ;interrupts.c: 35: msg_recvnext();
+"35
+[e ( _msg_recvnext ..  ]
+[e :U 268 ]
+[; ;interrupts.c: 57: }
+"57
+[e :UE 266 ]
+}

diff --git a/build/XC8_12F1822/production/interrupts.p1.d b/build/XC8_12F1822/production/interrupts.p1.d
new file mode 100644 (file)
index 0000000..192e73b
--- /dev/null
+++ b/build/XC8_12F1822/production/interrupts.p1.d
@@ -0,0 +1,4 @@
+ build/XC8_12F1822/production/interrupts.d  \
+ build/XC8_12F1822/production/interrupts.p1:  \
+ interrupts.c  \
+user.h 
\ No newline at end of file

diff --git a/build/XC8_12F1822/production/interrupts.pre b/build/XC8_12F1822/production/interrupts.pre
new file mode 100644 (file)
index 0000000..a5f18c4
--- /dev/null
+++ b/build/XC8_12F1822/production/interrupts.pre
@@ -0,0 +1,2953 @@
+
+# 1 "interrupts.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1822.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+struct {
+unsigned AN0 :1;
+unsigned AN1 :1;
+unsigned AN2 :1;
+unsigned :1;
+unsigned AN3 :1;
+};
+struct {
+unsigned CPS0 :1;
+unsigned CPS1 :1;
+unsigned CPS2 :1;
+unsigned :1;
+unsigned CPS3 :1;
+};
+struct {
+unsigned C1INP :1;
+unsigned C1IN0N :1;
+unsigned C1OUT :1;
+unsigned :1;
+unsigned C1IN1N :1;
+};
+struct {
+unsigned DACOUT :1;
+unsigned SRI :1;
+unsigned SRQ :1;
+unsigned :2;
+unsigned SRNQ :1;
+};
+struct {
+unsigned :1;
+unsigned SCK :1;
+unsigned T0CKI :1;
+unsigned :1;
+unsigned T1OSO :1;
+unsigned T1CKI :1;
+};
+struct {
+unsigned :1;
+unsigned SCL :1;
+unsigned SDA :1;
+unsigned nMCLR :1;
+unsigned CLKR :1;
+unsigned T1OSI :1;
+};
+struct {
+unsigned MDOUT :1;
+unsigned MDMIN :1;
+unsigned MDCIN1 :1;
+unsigned :1;
+unsigned MDCIN2 :1;
+};
+struct {
+unsigned :2;
+unsigned SDI :1;
+unsigned :1;
+unsigned OSC2 :1;
+unsigned OSC1 :1;
+};
+struct {
+unsigned :2;
+unsigned FLT0 :1;
+unsigned :1;
+unsigned CLKOUT :1;
+unsigned CLKIN :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 698
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 759
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 798
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 817
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 842
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 861
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 932
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 1008
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 1027
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 1046
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 1116
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 1175
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 1208
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1257
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1318
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1357
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1439
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1489
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1547
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1604
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1675
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1736
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1761
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1780
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+struct {
+unsigned :1;
+unsigned nDONE :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1868
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1933
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1977
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 2033
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned :4;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 2086
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 2105
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :6;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 2131
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 2206
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2260
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2311
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2381
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2432
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2507
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2573
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2619
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2644
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2663
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2692
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2706
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2725
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2786
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2805
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2824
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2843
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2866
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2880
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2899
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2960
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 3021
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 3072
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 3129
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 3152
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 3166
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 3189
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 3203
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3226
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3240
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3305
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3361
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3438
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3500
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3564
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3629
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3685
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3750
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3806
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3825
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3844
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3925
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3994
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 4079
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 4155
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned STR1C :1;
+unsigned STR1D :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 4198
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4255
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4312
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4369
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4444
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4494
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4546
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4610
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4674
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4705
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4724
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4743
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4762
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4781
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4800
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4819
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4838
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4857
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4876
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4901
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+
+extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 13 "user.h"
+void InitApp(void);
+bool msg_empty(void);
+void msg_write(const char *msg);
+void msg_writebyte(const char msg);
+void msg_sendnext(void);
+void tohex(char val[3], char i);
+void msg_recvnext(void);
+bool msg_recvready(void);
+char msg_recv(void);
+void putch(char);
+
+void int_disable(void);
+void int_enable(void);
+
+# 24 "interrupts.c"
+void interrupt isr(void)
+{
+
+# 31
+if (PIE1bits.TXIE && PIR1bits.TXIF)
+msg_sendnext();
+
+if (PIE1bits.RCIE && PIR1bits.RCIF)
+msg_recvnext();
+
+# 57
+}
+

diff --git a/build/XC8_12F1822/production/main.p1 b/build/XC8_12F1822/production/main.p1
new file mode 100644 (file)
index 0000000..d13ba6a
--- /dev/null
+++ b/build/XC8_12F1822/production/main.p1
@@ -0,0 +1,5562 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[p mainexit ]
+"31 system.h
+[v _ConfigureOscillator `(v ~T0 @X0 0 ef ]
+"13 user.h
+[v _InitApp `(v ~T0 @X0 0 ef ]
+"19 onewire.h
+[v _OW_start `(v ~T0 @X0 0 ef ]
+"15 user.h
+[v _msg_write `(v ~T0 @X0 0 ef1`*Cuc ]
+[s S70 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S70 . TRISA0 TRISA1 TRISA2 TRISA3 TRISA4 TRISA5 ]
+[u S69 `S70 1 ]
+[n S69 . . ]
+"1223 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[v _TRISAbits `VS69 ~T0 @X0 0 e@140 ]
+[s S30 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S30 . RA0 RA1 RA2 RA3 RA4 RA5 ]
+[s S31 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S31 . AN0 AN1 AN2 . AN3 ]
+[s S32 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S32 . CPS0 CPS1 CPS2 . CPS3 ]
+[s S33 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S33 . C1INP C1IN0N C1OUT . C1IN1N ]
+[s S34 :1 `uc 1 :1 `uc 1 :1 `uc 1 :2 `uc 1 :1 `uc 1 ]
+[n S34 . DACOUT SRI SRQ . SRNQ ]
+[s S35 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S35 . . SCK T0CKI . T1OSO T1CKI ]
+[s S36 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S36 . . SCL SDA nMCLR CLKR T1OSI ]
+[s S37 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S37 . MDOUT MDMIN MDCIN1 . MDCIN2 ]
+[s S38 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S38 . . SDI . OSC2 OSC1 ]
+[s S39 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S39 . . FLT0 . CLKOUT CLKIN ]
+[u S29 `S30 1 `S31 1 `S32 1 `S33 1 `S34 1 `S35 1 `S36 1 `S37 1 `S38 1 `S39 1 ]
+[n S29 . . . . . . . . . . . ]
+"489
+[v _PORTAbits `VS29 ~T0 @X0 0 e@12 ]
+"14 user.h
+[v _msg_empty `(uc ~T0 @X0 0 ef ]
+"20
+[v _msg_recvready `(uc ~T0 @X0 0 ef ]
+"21
+[v _msg_recv `(uc ~T0 @X0 0 ef ]
+"24
+[v _int_disable `(v ~T0 @X0 0 ef ]
+"11 onewire.h
+[v _OW_reset `(uc ~T0 @X0 0 ef ]
+"25 user.h
+[v _int_enable `(v ~T0 @X0 0 ef ]
+"17 onewire.h
+[v _OW_search_init `(v ~T0 @X0 0 ef ]
+"18 user.h
+[v _tohex `(v ~T0 @X0 0 ef2`*uc`uc ]
+"32 onewire.h
+[v _romid `uc ~T0 @X0 -> 0 `x e ]
+"18
+[v _OW_search `(uc ~T0 @X0 0 ef ]
+"21
+[v _OW_identify `(v ~T0 @X0 0 ef ]
+"22
+[v _OW_parasite `(uc ~T0 @X0 0 ef ]
+"23
+[v _OW_read_block `(v ~T0 @X0 0 ef3`uc`*uc`uc ]
+"24
+[v _OW_convert `(v ~T0 @X0 0 ef ]
+"27
+[v F3636 `(v ~T0 @X0 1 tf ]
+[v _drive_OW_low `TF3636 ~T0 @X0 0 e ]
+"28
+[v F3639 `(v ~T0 @X0 1 tf ]
+[v _drive_OW_high `TF3639 ~T0 @X0 0 e ]
+"29
+[v F3642 `(v ~T0 @X0 1 tf ]
+[v _float_OW `TF3642 ~T0 @X0 0 e ]
+"28 /opt/microchip/xc8/v1.12/include/pic.h
+[v __nop `(v ~T0 @X0 0 ef ]
+[p i __nop ]
+"30 onewire.h
+[v F3645 `(uc ~T0 @X0 1 tf ]
+[v _read_OW `TF3645 ~T0 @X0 0 e ]
+"16 user.h
+[v _msg_writebyte `(v ~T0 @X0 0 ef1`Cuc ]
+[s S72 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S72 . TMR1IE TMR2IE CCP1IE SSP1IE TXIE RCIE ADIE TMR1GIE ]
+[u S71 `S72 1 ]
+[n S71 . . ]
+"1274 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[v _PIE1bits `VS71 ~T0 @X0 0 e@145 ]
+"2824
+[v _TXREG `Vuc ~T0 @X0 0 e@410 ]
+[s S162 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S162 . RX9D OERR FERR ADDEN CREN SREN RX9 SPEN ]
+[u S161 `S162 1 ]
+[n S161 . . ]
+"2916
+[v _RCSTAbits `VS161 ~T0 @X0 0 e@413 ]
+"2805
+[v _RCREG `Vuc ~T0 @X0 0 e@409 ]
+[s S41 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S41 . TMR1IF TMR2IF CCP1IF SSP1IF TXIF RCIF ADIF TMR1GIF ]
+[u S40 `S41 1 ]
+[n S40 . . ]
+"715
+[v _PIR1bits `VS40 ~T0 @X0 0 e@17 ]
+[s S27 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S27 . IOCIF INTF TMR0IF IOCIE INTE TMR0IE PEIE GIE ]
+[s S28 :2 `uc 1 :1 `uc 1 :2 `uc 1 :1 `uc 1 ]
+[n S28 . . T0IF . T0IE ]
+[u S26 `S27 1 `S28 1 ]
+[n S26 . . . ]
+"355
+[v _INTCONbits `VS26 ~T0 @X0 0 e@11 ]
+[; ;pic12f1822.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[; ;pic12f1822.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1822.h: 49: typedef union {
+[; ;pic12f1822.h: 50: struct {
+[; ;pic12f1822.h: 51: unsigned INDF0 :8;
+[; ;pic12f1822.h: 52: };
+[; ;pic12f1822.h: 53: } INDF0bits_t;
+[; ;pic12f1822.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1822.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1822.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1822.h: 68: typedef union {
+[; ;pic12f1822.h: 69: struct {
+[; ;pic12f1822.h: 70: unsigned INDF1 :8;
+[; ;pic12f1822.h: 71: };
+[; ;pic12f1822.h: 72: } INDF1bits_t;
+[; ;pic12f1822.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1822.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1822.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1822.h: 87: typedef union {
+[; ;pic12f1822.h: 88: struct {
+[; ;pic12f1822.h: 89: unsigned PCL :8;
+[; ;pic12f1822.h: 90: };
+[; ;pic12f1822.h: 91: } PCLbits_t;
+[; ;pic12f1822.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1822.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1822.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1822.h: 106: typedef union {
+[; ;pic12f1822.h: 107: struct {
+[; ;pic12f1822.h: 108: unsigned C :1;
+[; ;pic12f1822.h: 109: unsigned DC :1;
+[; ;pic12f1822.h: 110: unsigned Z :1;
+[; ;pic12f1822.h: 111: unsigned nPD :1;
+[; ;pic12f1822.h: 112: unsigned nTO :1;
+[; ;pic12f1822.h: 113: };
+[; ;pic12f1822.h: 114: struct {
+[; ;pic12f1822.h: 115: unsigned CARRY :1;
+[; ;pic12f1822.h: 116: };
+[; ;pic12f1822.h: 117: struct {
+[; ;pic12f1822.h: 118: unsigned :2;
+[; ;pic12f1822.h: 119: unsigned ZERO :1;
+[; ;pic12f1822.h: 120: };
+[; ;pic12f1822.h: 121: } STATUSbits_t;
+[; ;pic12f1822.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1822.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1822.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1822.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1822.h: 169: typedef union {
+[; ;pic12f1822.h: 170: struct {
+[; ;pic12f1822.h: 171: unsigned FSR0L :8;
+[; ;pic12f1822.h: 172: };
+[; ;pic12f1822.h: 173: } FSR0Lbits_t;
+[; ;pic12f1822.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1822.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1822.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1822.h: 188: typedef union {
+[; ;pic12f1822.h: 189: struct {
+[; ;pic12f1822.h: 190: unsigned FSR0H :8;
+[; ;pic12f1822.h: 191: };
+[; ;pic12f1822.h: 192: } FSR0Hbits_t;
+[; ;pic12f1822.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1822.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1822.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1822.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1822.h: 210: typedef union {
+[; ;pic12f1822.h: 211: struct {
+[; ;pic12f1822.h: 212: unsigned FSR1L :8;
+[; ;pic12f1822.h: 213: };
+[; ;pic12f1822.h: 214: } FSR1Lbits_t;
+[; ;pic12f1822.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1822.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1822.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1822.h: 229: typedef union {
+[; ;pic12f1822.h: 230: struct {
+[; ;pic12f1822.h: 231: unsigned FSR1H :8;
+[; ;pic12f1822.h: 232: };
+[; ;pic12f1822.h: 233: } FSR1Hbits_t;
+[; ;pic12f1822.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1822.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1822.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1822.h: 248: typedef union {
+[; ;pic12f1822.h: 249: struct {
+[; ;pic12f1822.h: 250: unsigned BSR0 :1;
+[; ;pic12f1822.h: 251: unsigned BSR1 :1;
+[; ;pic12f1822.h: 252: unsigned BSR2 :1;
+[; ;pic12f1822.h: 253: unsigned BSR3 :1;
+[; ;pic12f1822.h: 254: unsigned BSR4 :1;
+[; ;pic12f1822.h: 255: };
+[; ;pic12f1822.h: 256: struct {
+[; ;pic12f1822.h: 257: unsigned BSR :5;
+[; ;pic12f1822.h: 258: };
+[; ;pic12f1822.h: 259: } BSRbits_t;
+[; ;pic12f1822.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1822.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1822.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1822.h: 299: typedef union {
+[; ;pic12f1822.h: 300: struct {
+[; ;pic12f1822.h: 301: unsigned WREG0 :8;
+[; ;pic12f1822.h: 302: };
+[; ;pic12f1822.h: 303: } WREGbits_t;
+[; ;pic12f1822.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1822.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1822.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1822.h: 318: typedef union {
+[; ;pic12f1822.h: 319: struct {
+[; ;pic12f1822.h: 320: unsigned PCLATH :7;
+[; ;pic12f1822.h: 321: };
+[; ;pic12f1822.h: 322: } PCLATHbits_t;
+[; ;pic12f1822.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1822.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1822.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1822.h: 337: typedef union {
+[; ;pic12f1822.h: 338: struct {
+[; ;pic12f1822.h: 339: unsigned IOCIF :1;
+[; ;pic12f1822.h: 340: unsigned INTF :1;
+[; ;pic12f1822.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1822.h: 342: unsigned IOCIE :1;
+[; ;pic12f1822.h: 343: unsigned INTE :1;
+[; ;pic12f1822.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1822.h: 345: unsigned PEIE :1;
+[; ;pic12f1822.h: 346: unsigned GIE :1;
+[; ;pic12f1822.h: 347: };
+[; ;pic12f1822.h: 348: struct {
+[; ;pic12f1822.h: 349: unsigned :2;
+[; ;pic12f1822.h: 350: unsigned T0IF :1;
+[; ;pic12f1822.h: 351: unsigned :2;
+[; ;pic12f1822.h: 352: unsigned T0IE :1;
+[; ;pic12f1822.h: 353: };
+[; ;pic12f1822.h: 354: } INTCONbits_t;
+[; ;pic12f1822.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1822.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1822.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1822.h: 414: typedef union {
+[; ;pic12f1822.h: 415: struct {
+[; ;pic12f1822.h: 416: unsigned RA0 :1;
+[; ;pic12f1822.h: 417: unsigned RA1 :1;
+[; ;pic12f1822.h: 418: unsigned RA2 :1;
+[; ;pic12f1822.h: 419: unsigned RA3 :1;
+[; ;pic12f1822.h: 420: unsigned RA4 :1;
+[; ;pic12f1822.h: 421: unsigned RA5 :1;
+[; ;pic12f1822.h: 422: };
+[; ;pic12f1822.h: 423: struct {
+[; ;pic12f1822.h: 424: unsigned AN0 :1;
+[; ;pic12f1822.h: 425: unsigned AN1 :1;
+[; ;pic12f1822.h: 426: unsigned AN2 :1;
+[; ;pic12f1822.h: 427: unsigned :1;
+[; ;pic12f1822.h: 428: unsigned AN3 :1;
+[; ;pic12f1822.h: 429: };
+[; ;pic12f1822.h: 430: struct {
+[; ;pic12f1822.h: 431: unsigned CPS0 :1;
+[; ;pic12f1822.h: 432: unsigned CPS1 :1;
+[; ;pic12f1822.h: 433: unsigned CPS2 :1;
+[; ;pic12f1822.h: 434: unsigned :1;
+[; ;pic12f1822.h: 435: unsigned CPS3 :1;
+[; ;pic12f1822.h: 436: };
+[; ;pic12f1822.h: 437: struct {
+[; ;pic12f1822.h: 438: unsigned C1INP :1;
+[; ;pic12f1822.h: 439: unsigned C1IN0N :1;
+[; ;pic12f1822.h: 440: unsigned C1OUT :1;
+[; ;pic12f1822.h: 441: unsigned :1;
+[; ;pic12f1822.h: 442: unsigned C1IN1N :1;
+[; ;pic12f1822.h: 443: };
+[; ;pic12f1822.h: 444: struct {
+[; ;pic12f1822.h: 445: unsigned DACOUT :1;
+[; ;pic12f1822.h: 446: unsigned SRI :1;
+[; ;pic12f1822.h: 447: unsigned SRQ :1;
+[; ;pic12f1822.h: 448: unsigned :2;
+[; ;pic12f1822.h: 449: unsigned SRNQ :1;
+[; ;pic12f1822.h: 450: };
+[; ;pic12f1822.h: 451: struct {
+[; ;pic12f1822.h: 452: unsigned :1;
+[; ;pic12f1822.h: 453: unsigned SCK :1;
+[; ;pic12f1822.h: 454: unsigned T0CKI :1;
+[; ;pic12f1822.h: 455: unsigned :1;
+[; ;pic12f1822.h: 456: unsigned T1OSO :1;
+[; ;pic12f1822.h: 457: unsigned T1CKI :1;
+[; ;pic12f1822.h: 458: };
+[; ;pic12f1822.h: 459: struct {
+[; ;pic12f1822.h: 460: unsigned :1;
+[; ;pic12f1822.h: 461: unsigned SCL :1;
+[; ;pic12f1822.h: 462: unsigned SDA :1;
+[; ;pic12f1822.h: 463: unsigned nMCLR :1;
+[; ;pic12f1822.h: 464: unsigned CLKR :1;
+[; ;pic12f1822.h: 465: unsigned T1OSI :1;
+[; ;pic12f1822.h: 466: };
+[; ;pic12f1822.h: 467: struct {
+[; ;pic12f1822.h: 468: unsigned MDOUT :1;
+[; ;pic12f1822.h: 469: unsigned MDMIN :1;
+[; ;pic12f1822.h: 470: unsigned MDCIN1 :1;
+[; ;pic12f1822.h: 471: unsigned :1;
+[; ;pic12f1822.h: 472: unsigned MDCIN2 :1;
+[; ;pic12f1822.h: 473: };
+[; ;pic12f1822.h: 474: struct {
+[; ;pic12f1822.h: 475: unsigned :2;
+[; ;pic12f1822.h: 476: unsigned SDI :1;
+[; ;pic12f1822.h: 477: unsigned :1;
+[; ;pic12f1822.h: 478: unsigned OSC2 :1;
+[; ;pic12f1822.h: 479: unsigned OSC1 :1;
+[; ;pic12f1822.h: 480: };
+[; ;pic12f1822.h: 481: struct {
+[; ;pic12f1822.h: 482: unsigned :2;
+[; ;pic12f1822.h: 483: unsigned FLT0 :1;
+[; ;pic12f1822.h: 484: unsigned :1;
+[; ;pic12f1822.h: 485: unsigned CLKOUT :1;
+[; ;pic12f1822.h: 486: unsigned CLKIN :1;
+[; ;pic12f1822.h: 487: };
+[; ;pic12f1822.h: 488: } PORTAbits_t;
+[; ;pic12f1822.h: 489: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1822.h: 698: extern volatile unsigned char PIR1 @ 0x011;
+"700
+[; ;pic12f1822.h: 700: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1822.h: 703: typedef union {
+[; ;pic12f1822.h: 704: struct {
+[; ;pic12f1822.h: 705: unsigned TMR1IF :1;
+[; ;pic12f1822.h: 706: unsigned TMR2IF :1;
+[; ;pic12f1822.h: 707: unsigned CCP1IF :1;
+[; ;pic12f1822.h: 708: unsigned SSP1IF :1;
+[; ;pic12f1822.h: 709: unsigned TXIF :1;
+[; ;pic12f1822.h: 710: unsigned RCIF :1;
+[; ;pic12f1822.h: 711: unsigned ADIF :1;
+[; ;pic12f1822.h: 712: unsigned TMR1GIF :1;
+[; ;pic12f1822.h: 713: };
+[; ;pic12f1822.h: 714: } PIR1bits_t;
+[; ;pic12f1822.h: 715: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1822.h: 759: extern volatile unsigned char PIR2 @ 0x012;
+"761
+[; ;pic12f1822.h: 761: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1822.h: 764: typedef union {
+[; ;pic12f1822.h: 765: struct {
+[; ;pic12f1822.h: 766: unsigned :3;
+[; ;pic12f1822.h: 767: unsigned BCL1IF :1;
+[; ;pic12f1822.h: 768: unsigned EEIF :1;
+[; ;pic12f1822.h: 769: unsigned C1IF :1;
+[; ;pic12f1822.h: 770: unsigned :1;
+[; ;pic12f1822.h: 771: unsigned OSFIF :1;
+[; ;pic12f1822.h: 772: };
+[; ;pic12f1822.h: 773: } PIR2bits_t;
+[; ;pic12f1822.h: 774: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1822.h: 798: extern volatile unsigned char TMR0 @ 0x015;
+"800
+[; ;pic12f1822.h: 800: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1822.h: 803: typedef union {
+[; ;pic12f1822.h: 804: struct {
+[; ;pic12f1822.h: 805: unsigned TMR0 :8;
+[; ;pic12f1822.h: 806: };
+[; ;pic12f1822.h: 807: } TMR0bits_t;
+[; ;pic12f1822.h: 808: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1822.h: 817: extern volatile unsigned short TMR1 @ 0x016;
+"819
+[; ;pic12f1822.h: 819: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1822.h: 823: extern volatile unsigned char TMR1L @ 0x016;
+"825
+[; ;pic12f1822.h: 825: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1822.h: 828: typedef union {
+[; ;pic12f1822.h: 829: struct {
+[; ;pic12f1822.h: 830: unsigned TMR1L :8;
+[; ;pic12f1822.h: 831: };
+[; ;pic12f1822.h: 832: } TMR1Lbits_t;
+[; ;pic12f1822.h: 833: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1822.h: 842: extern volatile unsigned char TMR1H @ 0x017;
+"844
+[; ;pic12f1822.h: 844: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1822.h: 847: typedef union {
+[; ;pic12f1822.h: 848: struct {
+[; ;pic12f1822.h: 849: unsigned TMR1H :8;
+[; ;pic12f1822.h: 850: };
+[; ;pic12f1822.h: 851: } TMR1Hbits_t;
+[; ;pic12f1822.h: 852: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1822.h: 861: extern volatile unsigned char T1CON @ 0x018;
+"863
+[; ;pic12f1822.h: 863: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1822.h: 866: typedef union {
+[; ;pic12f1822.h: 867: struct {
+[; ;pic12f1822.h: 868: unsigned TMR1ON :1;
+[; ;pic12f1822.h: 869: unsigned :1;
+[; ;pic12f1822.h: 870: unsigned nT1SYNC :1;
+[; ;pic12f1822.h: 871: unsigned T1OSCEN :1;
+[; ;pic12f1822.h: 872: unsigned T1CKPS0 :1;
+[; ;pic12f1822.h: 873: unsigned T1CKPS1 :1;
+[; ;pic12f1822.h: 874: unsigned TMR1CS0 :1;
+[; ;pic12f1822.h: 875: unsigned TMR1CS1 :1;
+[; ;pic12f1822.h: 876: };
+[; ;pic12f1822.h: 877: struct {
+[; ;pic12f1822.h: 878: unsigned :4;
+[; ;pic12f1822.h: 879: unsigned T1CKPS :2;
+[; ;pic12f1822.h: 880: unsigned TMR1CS :2;
+[; ;pic12f1822.h: 881: };
+[; ;pic12f1822.h: 882: } T1CONbits_t;
+[; ;pic12f1822.h: 883: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1822.h: 932: extern volatile unsigned char T1GCON @ 0x019;
+"934
+[; ;pic12f1822.h: 934: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1822.h: 937: typedef union {
+[; ;pic12f1822.h: 938: struct {
+[; ;pic12f1822.h: 939: unsigned T1GSS0 :1;
+[; ;pic12f1822.h: 940: unsigned T1GSS1 :1;
+[; ;pic12f1822.h: 941: unsigned T1GVAL :1;
+[; ;pic12f1822.h: 942: unsigned T1GGO_nDONE :1;
+[; ;pic12f1822.h: 943: unsigned T1GSPM :1;
+[; ;pic12f1822.h: 944: unsigned T1GTM :1;
+[; ;pic12f1822.h: 945: unsigned T1GPOL :1;
+[; ;pic12f1822.h: 946: unsigned TMR1GE :1;
+[; ;pic12f1822.h: 947: };
+[; ;pic12f1822.h: 948: struct {
+[; ;pic12f1822.h: 949: unsigned T1GSS :2;
+[; ;pic12f1822.h: 950: unsigned :1;
+[; ;pic12f1822.h: 951: unsigned T1GGO :1;
+[; ;pic12f1822.h: 952: };
+[; ;pic12f1822.h: 953: } T1GCONbits_t;
+[; ;pic12f1822.h: 954: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1822.h: 1008: extern volatile unsigned char TMR2 @ 0x01A;
+"1010
+[; ;pic12f1822.h: 1010: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1822.h: 1013: typedef union {
+[; ;pic12f1822.h: 1014: struct {
+[; ;pic12f1822.h: 1015: unsigned TMR2 :8;
+[; ;pic12f1822.h: 1016: };
+[; ;pic12f1822.h: 1017: } TMR2bits_t;
+[; ;pic12f1822.h: 1018: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1822.h: 1027: extern volatile unsigned char PR2 @ 0x01B;
+"1029
+[; ;pic12f1822.h: 1029: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1822.h: 1032: typedef union {
+[; ;pic12f1822.h: 1033: struct {
+[; ;pic12f1822.h: 1034: unsigned PR2 :8;
+[; ;pic12f1822.h: 1035: };
+[; ;pic12f1822.h: 1036: } PR2bits_t;
+[; ;pic12f1822.h: 1037: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1822.h: 1046: extern volatile unsigned char T2CON @ 0x01C;
+"1048
+[; ;pic12f1822.h: 1048: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1822.h: 1051: typedef union {
+[; ;pic12f1822.h: 1052: struct {
+[; ;pic12f1822.h: 1053: unsigned T2CKPS0 :1;
+[; ;pic12f1822.h: 1054: unsigned T2CKPS1 :1;
+[; ;pic12f1822.h: 1055: unsigned TMR2ON :1;
+[; ;pic12f1822.h: 1056: unsigned T2OUTPS0 :1;
+[; ;pic12f1822.h: 1057: unsigned T2OUTPS1 :1;
+[; ;pic12f1822.h: 1058: unsigned T2OUTPS2 :1;
+[; ;pic12f1822.h: 1059: unsigned T2OUTPS3 :1;
+[; ;pic12f1822.h: 1060: };
+[; ;pic12f1822.h: 1061: struct {
+[; ;pic12f1822.h: 1062: unsigned T2CKPS :2;
+[; ;pic12f1822.h: 1063: unsigned :1;
+[; ;pic12f1822.h: 1064: unsigned T2OUTPS :4;
+[; ;pic12f1822.h: 1065: };
+[; ;pic12f1822.h: 1066: } T2CONbits_t;
+[; ;pic12f1822.h: 1067: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1822.h: 1116: extern volatile unsigned char CPSCON0 @ 0x01E;
+"1118
+[; ;pic12f1822.h: 1118: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1822.h: 1121: typedef union {
+[; ;pic12f1822.h: 1122: struct {
+[; ;pic12f1822.h: 1123: unsigned T0XCS :1;
+[; ;pic12f1822.h: 1124: unsigned CPSOUT :1;
+[; ;pic12f1822.h: 1125: unsigned CPSRNG0 :1;
+[; ;pic12f1822.h: 1126: unsigned CPSRNG1 :1;
+[; ;pic12f1822.h: 1127: unsigned :2;
+[; ;pic12f1822.h: 1128: unsigned CPSRM :1;
+[; ;pic12f1822.h: 1129: unsigned CPSON :1;
+[; ;pic12f1822.h: 1130: };
+[; ;pic12f1822.h: 1131: struct {
+[; ;pic12f1822.h: 1132: unsigned :2;
+[; ;pic12f1822.h: 1133: unsigned CPSRNG :2;
+[; ;pic12f1822.h: 1134: };
+[; ;pic12f1822.h: 1135: } CPSCON0bits_t;
+[; ;pic12f1822.h: 1136: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1822.h: 1175: extern volatile unsigned char CPSCON1 @ 0x01F;
+"1177
+[; ;pic12f1822.h: 1177: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1822.h: 1180: typedef union {
+[; ;pic12f1822.h: 1181: struct {
+[; ;pic12f1822.h: 1182: unsigned CPSCH0 :1;
+[; ;pic12f1822.h: 1183: unsigned CPSCH1 :1;
+[; ;pic12f1822.h: 1184: };
+[; ;pic12f1822.h: 1185: struct {
+[; ;pic12f1822.h: 1186: unsigned CPSCH :2;
+[; ;pic12f1822.h: 1187: };
+[; ;pic12f1822.h: 1188: } CPSCON1bits_t;
+[; ;pic12f1822.h: 1189: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1822.h: 1208: extern volatile unsigned char TRISA @ 0x08C;
+"1210
+[; ;pic12f1822.h: 1210: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1822.h: 1213: typedef union {
+[; ;pic12f1822.h: 1214: struct {
+[; ;pic12f1822.h: 1215: unsigned TRISA0 :1;
+[; ;pic12f1822.h: 1216: unsigned TRISA1 :1;
+[; ;pic12f1822.h: 1217: unsigned TRISA2 :1;
+[; ;pic12f1822.h: 1218: unsigned TRISA3 :1;
+[; ;pic12f1822.h: 1219: unsigned TRISA4 :1;
+[; ;pic12f1822.h: 1220: unsigned TRISA5 :1;
+[; ;pic12f1822.h: 1221: };
+[; ;pic12f1822.h: 1222: } TRISAbits_t;
+[; ;pic12f1822.h: 1223: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1822.h: 1257: extern volatile unsigned char PIE1 @ 0x091;
+"1259
+[; ;pic12f1822.h: 1259: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1822.h: 1262: typedef union {
+[; ;pic12f1822.h: 1263: struct {
+[; ;pic12f1822.h: 1264: unsigned TMR1IE :1;
+[; ;pic12f1822.h: 1265: unsigned TMR2IE :1;
+[; ;pic12f1822.h: 1266: unsigned CCP1IE :1;
+[; ;pic12f1822.h: 1267: unsigned SSP1IE :1;
+[; ;pic12f1822.h: 1268: unsigned TXIE :1;
+[; ;pic12f1822.h: 1269: unsigned RCIE :1;
+[; ;pic12f1822.h: 1270: unsigned ADIE :1;
+[; ;pic12f1822.h: 1271: unsigned TMR1GIE :1;
+[; ;pic12f1822.h: 1272: };
+[; ;pic12f1822.h: 1273: } PIE1bits_t;
+[; ;pic12f1822.h: 1274: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1822.h: 1318: extern volatile unsigned char PIE2 @ 0x092;
+"1320
+[; ;pic12f1822.h: 1320: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1822.h: 1323: typedef union {
+[; ;pic12f1822.h: 1324: struct {
+[; ;pic12f1822.h: 1325: unsigned :3;
+[; ;pic12f1822.h: 1326: unsigned BCL1IE :1;
+[; ;pic12f1822.h: 1327: unsigned EEIE :1;
+[; ;pic12f1822.h: 1328: unsigned C1IE :1;
+[; ;pic12f1822.h: 1329: unsigned :1;
+[; ;pic12f1822.h: 1330: unsigned OSFIE :1;
+[; ;pic12f1822.h: 1331: };
+[; ;pic12f1822.h: 1332: } PIE2bits_t;
+[; ;pic12f1822.h: 1333: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1822.h: 1357: extern volatile unsigned char OPTION_REG @ 0x095;
+"1359
+[; ;pic12f1822.h: 1359: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1822.h: 1362: typedef union {
+[; ;pic12f1822.h: 1363: struct {
+[; ;pic12f1822.h: 1364: unsigned PS0 :1;
+[; ;pic12f1822.h: 1365: unsigned PS1 :1;
+[; ;pic12f1822.h: 1366: unsigned PS2 :1;
+[; ;pic12f1822.h: 1367: unsigned PSA :1;
+[; ;pic12f1822.h: 1368: unsigned TMR0SE :1;
+[; ;pic12f1822.h: 1369: unsigned TMR0CS :1;
+[; ;pic12f1822.h: 1370: unsigned INTEDG :1;
+[; ;pic12f1822.h: 1371: unsigned nWPUEN :1;
+[; ;pic12f1822.h: 1372: };
+[; ;pic12f1822.h: 1373: struct {
+[; ;pic12f1822.h: 1374: unsigned PS :3;
+[; ;pic12f1822.h: 1375: unsigned :1;
+[; ;pic12f1822.h: 1376: unsigned T0SE :1;
+[; ;pic12f1822.h: 1377: unsigned T0CS :1;
+[; ;pic12f1822.h: 1378: };
+[; ;pic12f1822.h: 1379: } OPTION_REGbits_t;
+[; ;pic12f1822.h: 1380: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1822.h: 1439: extern volatile unsigned char PCON @ 0x096;
+"1441
+[; ;pic12f1822.h: 1441: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1822.h: 1444: typedef union {
+[; ;pic12f1822.h: 1445: struct {
+[; ;pic12f1822.h: 1446: unsigned nBOR :1;
+[; ;pic12f1822.h: 1447: unsigned nPOR :1;
+[; ;pic12f1822.h: 1448: unsigned nRI :1;
+[; ;pic12f1822.h: 1449: unsigned nRMCLR :1;
+[; ;pic12f1822.h: 1450: unsigned :2;
+[; ;pic12f1822.h: 1451: unsigned STKUNF :1;
+[; ;pic12f1822.h: 1452: unsigned STKOVF :1;
+[; ;pic12f1822.h: 1453: };
+[; ;pic12f1822.h: 1454: } PCONbits_t;
+[; ;pic12f1822.h: 1455: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1822.h: 1489: extern volatile unsigned char WDTCON @ 0x097;
+"1491
+[; ;pic12f1822.h: 1491: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1822.h: 1494: typedef union {
+[; ;pic12f1822.h: 1495: struct {
+[; ;pic12f1822.h: 1496: unsigned SWDTEN :1;
+[; ;pic12f1822.h: 1497: unsigned WDTPS0 :1;
+[; ;pic12f1822.h: 1498: unsigned WDTPS1 :1;
+[; ;pic12f1822.h: 1499: unsigned WDTPS2 :1;
+[; ;pic12f1822.h: 1500: unsigned WDTPS3 :1;
+[; ;pic12f1822.h: 1501: unsigned WDTPS4 :1;
+[; ;pic12f1822.h: 1502: };
+[; ;pic12f1822.h: 1503: struct {
+[; ;pic12f1822.h: 1504: unsigned :1;
+[; ;pic12f1822.h: 1505: unsigned WDTPS :5;
+[; ;pic12f1822.h: 1506: };
+[; ;pic12f1822.h: 1507: } WDTCONbits_t;
+[; ;pic12f1822.h: 1508: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1822.h: 1547: extern volatile unsigned char OSCTUNE @ 0x098;
+"1549
+[; ;pic12f1822.h: 1549: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1822.h: 1552: typedef union {
+[; ;pic12f1822.h: 1553: struct {
+[; ;pic12f1822.h: 1554: unsigned TUN0 :1;
+[; ;pic12f1822.h: 1555: unsigned TUN1 :1;
+[; ;pic12f1822.h: 1556: unsigned TUN2 :1;
+[; ;pic12f1822.h: 1557: unsigned TUN3 :1;
+[; ;pic12f1822.h: 1558: unsigned TUN4 :1;
+[; ;pic12f1822.h: 1559: unsigned TUN5 :1;
+[; ;pic12f1822.h: 1560: };
+[; ;pic12f1822.h: 1561: struct {
+[; ;pic12f1822.h: 1562: unsigned TUN :6;
+[; ;pic12f1822.h: 1563: };
+[; ;pic12f1822.h: 1564: } OSCTUNEbits_t;
+[; ;pic12f1822.h: 1565: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1822.h: 1604: extern volatile unsigned char OSCCON @ 0x099;
+"1606
+[; ;pic12f1822.h: 1606: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1822.h: 1609: typedef union {
+[; ;pic12f1822.h: 1610: struct {
+[; ;pic12f1822.h: 1611: unsigned SCS0 :1;
+[; ;pic12f1822.h: 1612: unsigned SCS1 :1;
+[; ;pic12f1822.h: 1613: unsigned :1;
+[; ;pic12f1822.h: 1614: unsigned IRCF0 :1;
+[; ;pic12f1822.h: 1615: unsigned IRCF1 :1;
+[; ;pic12f1822.h: 1616: unsigned IRCF2 :1;
+[; ;pic12f1822.h: 1617: unsigned IRCF3 :1;
+[; ;pic12f1822.h: 1618: unsigned SPLLEN :1;
+[; ;pic12f1822.h: 1619: };
+[; ;pic12f1822.h: 1620: struct {
+[; ;pic12f1822.h: 1621: unsigned SCS :2;
+[; ;pic12f1822.h: 1622: unsigned :1;
+[; ;pic12f1822.h: 1623: unsigned IRCF :4;
+[; ;pic12f1822.h: 1624: };
+[; ;pic12f1822.h: 1625: } OSCCONbits_t;
+[; ;pic12f1822.h: 1626: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1822.h: 1675: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1677
+[; ;pic12f1822.h: 1677: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1822.h: 1680: typedef union {
+[; ;pic12f1822.h: 1681: struct {
+[; ;pic12f1822.h: 1682: unsigned HFIOFS :1;
+[; ;pic12f1822.h: 1683: unsigned LFIOFR :1;
+[; ;pic12f1822.h: 1684: unsigned MFIOFR :1;
+[; ;pic12f1822.h: 1685: unsigned HFIOFL :1;
+[; ;pic12f1822.h: 1686: unsigned HFIOFR :1;
+[; ;pic12f1822.h: 1687: unsigned OSTS :1;
+[; ;pic12f1822.h: 1688: unsigned PLLR :1;
+[; ;pic12f1822.h: 1689: unsigned T1OSCR :1;
+[; ;pic12f1822.h: 1690: };
+[; ;pic12f1822.h: 1691: } OSCSTATbits_t;
+[; ;pic12f1822.h: 1692: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1822.h: 1736: extern volatile unsigned short ADRES @ 0x09B;
+"1738
+[; ;pic12f1822.h: 1738: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1822.h: 1742: extern volatile unsigned char ADRESL @ 0x09B;
+"1744
+[; ;pic12f1822.h: 1744: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1822.h: 1747: typedef union {
+[; ;pic12f1822.h: 1748: struct {
+[; ;pic12f1822.h: 1749: unsigned ADRESL :8;
+[; ;pic12f1822.h: 1750: };
+[; ;pic12f1822.h: 1751: } ADRESLbits_t;
+[; ;pic12f1822.h: 1752: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1822.h: 1761: extern volatile unsigned char ADRESH @ 0x09C;
+"1763
+[; ;pic12f1822.h: 1763: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1822.h: 1766: typedef union {
+[; ;pic12f1822.h: 1767: struct {
+[; ;pic12f1822.h: 1768: unsigned ADRESH :8;
+[; ;pic12f1822.h: 1769: };
+[; ;pic12f1822.h: 1770: } ADRESHbits_t;
+[; ;pic12f1822.h: 1771: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1822.h: 1780: extern volatile unsigned char ADCON0 @ 0x09D;
+"1782
+[; ;pic12f1822.h: 1782: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1822.h: 1785: typedef union {
+[; ;pic12f1822.h: 1786: struct {
+[; ;pic12f1822.h: 1787: unsigned ADON :1;
+[; ;pic12f1822.h: 1788: unsigned GO_nDONE :1;
+[; ;pic12f1822.h: 1789: unsigned CHS0 :1;
+[; ;pic12f1822.h: 1790: unsigned CHS1 :1;
+[; ;pic12f1822.h: 1791: unsigned CHS2 :1;
+[; ;pic12f1822.h: 1792: unsigned CHS3 :1;
+[; ;pic12f1822.h: 1793: unsigned CHS4 :1;
+[; ;pic12f1822.h: 1794: };
+[; ;pic12f1822.h: 1795: struct {
+[; ;pic12f1822.h: 1796: unsigned :1;
+[; ;pic12f1822.h: 1797: unsigned ADGO :1;
+[; ;pic12f1822.h: 1798: unsigned CHS :5;
+[; ;pic12f1822.h: 1799: };
+[; ;pic12f1822.h: 1800: struct {
+[; ;pic12f1822.h: 1801: unsigned :1;
+[; ;pic12f1822.h: 1802: unsigned GO :1;
+[; ;pic12f1822.h: 1803: };
+[; ;pic12f1822.h: 1804: struct {
+[; ;pic12f1822.h: 1805: unsigned :1;
+[; ;pic12f1822.h: 1806: unsigned nDONE :1;
+[; ;pic12f1822.h: 1807: };
+[; ;pic12f1822.h: 1808: } ADCON0bits_t;
+[; ;pic12f1822.h: 1809: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1822.h: 1868: extern volatile unsigned char ADCON1 @ 0x09E;
+"1870
+[; ;pic12f1822.h: 1870: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1822.h: 1873: typedef union {
+[; ;pic12f1822.h: 1874: struct {
+[; ;pic12f1822.h: 1875: unsigned ADPREF0 :1;
+[; ;pic12f1822.h: 1876: unsigned ADPREF1 :1;
+[; ;pic12f1822.h: 1877: unsigned :2;
+[; ;pic12f1822.h: 1878: unsigned ADCS0 :1;
+[; ;pic12f1822.h: 1879: unsigned ADCS1 :1;
+[; ;pic12f1822.h: 1880: unsigned ADCS2 :1;
+[; ;pic12f1822.h: 1881: unsigned ADFM :1;
+[; ;pic12f1822.h: 1882: };
+[; ;pic12f1822.h: 1883: struct {
+[; ;pic12f1822.h: 1884: unsigned ADPREF :2;
+[; ;pic12f1822.h: 1885: unsigned :2;
+[; ;pic12f1822.h: 1886: unsigned ADCS :3;
+[; ;pic12f1822.h: 1887: };
+[; ;pic12f1822.h: 1888: } ADCON1bits_t;
+[; ;pic12f1822.h: 1889: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1822.h: 1933: extern volatile unsigned char LATA @ 0x10C;
+"1935
+[; ;pic12f1822.h: 1935: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1822.h: 1938: typedef union {
+[; ;pic12f1822.h: 1939: struct {
+[; ;pic12f1822.h: 1940: unsigned LATA0 :1;
+[; ;pic12f1822.h: 1941: unsigned LATA1 :1;
+[; ;pic12f1822.h: 1942: unsigned LATA2 :1;
+[; ;pic12f1822.h: 1943: unsigned :1;
+[; ;pic12f1822.h: 1944: unsigned LATA4 :1;
+[; ;pic12f1822.h: 1945: unsigned LATA5 :1;
+[; ;pic12f1822.h: 1946: };
+[; ;pic12f1822.h: 1947: } LATAbits_t;
+[; ;pic12f1822.h: 1948: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1822.h: 1977: extern volatile unsigned char CM1CON0 @ 0x111;
+"1979
+[; ;pic12f1822.h: 1979: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1822.h: 1982: typedef union {
+[; ;pic12f1822.h: 1983: struct {
+[; ;pic12f1822.h: 1984: unsigned C1SYNC :1;
+[; ;pic12f1822.h: 1985: unsigned C1HYS :1;
+[; ;pic12f1822.h: 1986: unsigned C1SP :1;
+[; ;pic12f1822.h: 1987: unsigned :1;
+[; ;pic12f1822.h: 1988: unsigned C1POL :1;
+[; ;pic12f1822.h: 1989: unsigned C1OE :1;
+[; ;pic12f1822.h: 1990: unsigned C1OUT :1;
+[; ;pic12f1822.h: 1991: unsigned C1ON :1;
+[; ;pic12f1822.h: 1992: };
+[; ;pic12f1822.h: 1993: } CM1CON0bits_t;
+[; ;pic12f1822.h: 1994: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1822.h: 2033: extern volatile unsigned char CM1CON1 @ 0x112;
+"2035
+[; ;pic12f1822.h: 2035: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1822.h: 2038: typedef union {
+[; ;pic12f1822.h: 2039: struct {
+[; ;pic12f1822.h: 2040: unsigned C1NCH0 :1;
+[; ;pic12f1822.h: 2041: unsigned :3;
+[; ;pic12f1822.h: 2042: unsigned C1PCH0 :1;
+[; ;pic12f1822.h: 2043: unsigned C1PCH1 :1;
+[; ;pic12f1822.h: 2044: unsigned C1INTN :1;
+[; ;pic12f1822.h: 2045: unsigned C1INTP :1;
+[; ;pic12f1822.h: 2046: };
+[; ;pic12f1822.h: 2047: struct {
+[; ;pic12f1822.h: 2048: unsigned :4;
+[; ;pic12f1822.h: 2049: unsigned C1PCH :2;
+[; ;pic12f1822.h: 2050: };
+[; ;pic12f1822.h: 2051: } CM1CON1bits_t;
+[; ;pic12f1822.h: 2052: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1822.h: 2086: extern volatile unsigned char CMOUT @ 0x115;
+"2088
+[; ;pic12f1822.h: 2088: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1822.h: 2091: typedef union {
+[; ;pic12f1822.h: 2092: struct {
+[; ;pic12f1822.h: 2093: unsigned MC1OUT :1;
+[; ;pic12f1822.h: 2094: };
+[; ;pic12f1822.h: 2095: } CMOUTbits_t;
+[; ;pic12f1822.h: 2096: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1822.h: 2105: extern volatile unsigned char BORCON @ 0x116;
+"2107
+[; ;pic12f1822.h: 2107: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1822.h: 2110: typedef union {
+[; ;pic12f1822.h: 2111: struct {
+[; ;pic12f1822.h: 2112: unsigned BORRDY :1;
+[; ;pic12f1822.h: 2113: unsigned :6;
+[; ;pic12f1822.h: 2114: unsigned SBOREN :1;
+[; ;pic12f1822.h: 2115: };
+[; ;pic12f1822.h: 2116: } BORCONbits_t;
+[; ;pic12f1822.h: 2117: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1822.h: 2131: extern volatile unsigned char FVRCON @ 0x117;
+"2133
+[; ;pic12f1822.h: 2133: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1822.h: 2136: typedef union {
+[; ;pic12f1822.h: 2137: struct {
+[; ;pic12f1822.h: 2138: unsigned ADFVR0 :1;
+[; ;pic12f1822.h: 2139: unsigned ADFVR1 :1;
+[; ;pic12f1822.h: 2140: unsigned CDAFVR0 :1;
+[; ;pic12f1822.h: 2141: unsigned CDAFVR1 :1;
+[; ;pic12f1822.h: 2142: unsigned TSRNG :1;
+[; ;pic12f1822.h: 2143: unsigned TSEN :1;
+[; ;pic12f1822.h: 2144: unsigned FVRRDY :1;
+[; ;pic12f1822.h: 2145: unsigned FVREN :1;
+[; ;pic12f1822.h: 2146: };
+[; ;pic12f1822.h: 2147: struct {
+[; ;pic12f1822.h: 2148: unsigned ADFVR :2;
+[; ;pic12f1822.h: 2149: unsigned CDAFVR :2;
+[; ;pic12f1822.h: 2150: };
+[; ;pic12f1822.h: 2151: } FVRCONbits_t;
+[; ;pic12f1822.h: 2152: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1822.h: 2206: extern volatile unsigned char DACCON0 @ 0x118;
+"2208
+[; ;pic12f1822.h: 2208: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1822.h: 2211: typedef union {
+[; ;pic12f1822.h: 2212: struct {
+[; ;pic12f1822.h: 2213: unsigned :2;
+[; ;pic12f1822.h: 2214: unsigned DACPSS0 :1;
+[; ;pic12f1822.h: 2215: unsigned DACPSS1 :1;
+[; ;pic12f1822.h: 2216: unsigned :1;
+[; ;pic12f1822.h: 2217: unsigned DACOE :1;
+[; ;pic12f1822.h: 2218: unsigned DACLPS :1;
+[; ;pic12f1822.h: 2219: unsigned DACEN :1;
+[; ;pic12f1822.h: 2220: };
+[; ;pic12f1822.h: 2221: struct {
+[; ;pic12f1822.h: 2222: unsigned :2;
+[; ;pic12f1822.h: 2223: unsigned DACPSS :2;
+[; ;pic12f1822.h: 2224: };
+[; ;pic12f1822.h: 2225: } DACCON0bits_t;
+[; ;pic12f1822.h: 2226: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1822.h: 2260: extern volatile unsigned char DACCON1 @ 0x119;
+"2262
+[; ;pic12f1822.h: 2262: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1822.h: 2265: typedef union {
+[; ;pic12f1822.h: 2266: struct {
+[; ;pic12f1822.h: 2267: unsigned DACR0 :1;
+[; ;pic12f1822.h: 2268: unsigned DACR1 :1;
+[; ;pic12f1822.h: 2269: unsigned DACR2 :1;
+[; ;pic12f1822.h: 2270: unsigned DACR3 :1;
+[; ;pic12f1822.h: 2271: unsigned DACR4 :1;
+[; ;pic12f1822.h: 2272: };
+[; ;pic12f1822.h: 2273: struct {
+[; ;pic12f1822.h: 2274: unsigned DACR :5;
+[; ;pic12f1822.h: 2275: };
+[; ;pic12f1822.h: 2276: } DACCON1bits_t;
+[; ;pic12f1822.h: 2277: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1822.h: 2311: extern volatile unsigned char SRCON0 @ 0x11A;
+"2313
+[; ;pic12f1822.h: 2313: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1822.h: 2316: typedef union {
+[; ;pic12f1822.h: 2317: struct {
+[; ;pic12f1822.h: 2318: unsigned SRPR :1;
+[; ;pic12f1822.h: 2319: unsigned SRPS :1;
+[; ;pic12f1822.h: 2320: unsigned SRNQEN :1;
+[; ;pic12f1822.h: 2321: unsigned SRQEN :1;
+[; ;pic12f1822.h: 2322: unsigned SRCLK0 :1;
+[; ;pic12f1822.h: 2323: unsigned SRCLK1 :1;
+[; ;pic12f1822.h: 2324: unsigned SRCLK2 :1;
+[; ;pic12f1822.h: 2325: unsigned SRLEN :1;
+[; ;pic12f1822.h: 2326: };
+[; ;pic12f1822.h: 2327: struct {
+[; ;pic12f1822.h: 2328: unsigned :4;
+[; ;pic12f1822.h: 2329: unsigned SRCLK :3;
+[; ;pic12f1822.h: 2330: };
+[; ;pic12f1822.h: 2331: } SRCON0bits_t;
+[; ;pic12f1822.h: 2332: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1822.h: 2381: extern volatile unsigned char SRCON1 @ 0x11B;
+"2383
+[; ;pic12f1822.h: 2383: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1822.h: 2386: typedef union {
+[; ;pic12f1822.h: 2387: struct {
+[; ;pic12f1822.h: 2388: unsigned SRRC1E :1;
+[; ;pic12f1822.h: 2389: unsigned :1;
+[; ;pic12f1822.h: 2390: unsigned SRRCKE :1;
+[; ;pic12f1822.h: 2391: unsigned SRRPE :1;
+[; ;pic12f1822.h: 2392: unsigned SRSC1E :1;
+[; ;pic12f1822.h: 2393: unsigned :1;
+[; ;pic12f1822.h: 2394: unsigned SRSCKE :1;
+[; ;pic12f1822.h: 2395: unsigned SRSPE :1;
+[; ;pic12f1822.h: 2396: };
+[; ;pic12f1822.h: 2397: } SRCON1bits_t;
+[; ;pic12f1822.h: 2398: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1822.h: 2432: extern volatile unsigned char APFCON @ 0x11D;
+"2434
+[; ;pic12f1822.h: 2434: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1822.h: 2437: extern volatile unsigned char APFCON0 @ 0x11D;
+"2439
+[; ;pic12f1822.h: 2439: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1822.h: 2442: typedef union {
+[; ;pic12f1822.h: 2443: struct {
+[; ;pic12f1822.h: 2444: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2445: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2446: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2447: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2448: unsigned :1;
+[; ;pic12f1822.h: 2449: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2450: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2451: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2452: };
+[; ;pic12f1822.h: 2453: struct {
+[; ;pic12f1822.h: 2454: unsigned :5;
+[; ;pic12f1822.h: 2455: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2456: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2457: };
+[; ;pic12f1822.h: 2458: } APFCONbits_t;
+[; ;pic12f1822.h: 2459: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1822.h: 2507: typedef union {
+[; ;pic12f1822.h: 2508: struct {
+[; ;pic12f1822.h: 2509: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2510: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2511: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2512: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2513: unsigned :1;
+[; ;pic12f1822.h: 2514: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2515: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2516: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2517: };
+[; ;pic12f1822.h: 2518: struct {
+[; ;pic12f1822.h: 2519: unsigned :5;
+[; ;pic12f1822.h: 2520: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2521: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2522: };
+[; ;pic12f1822.h: 2523: } APFCON0bits_t;
+[; ;pic12f1822.h: 2524: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1822.h: 2573: extern volatile unsigned char ANSELA @ 0x18C;
+"2575
+[; ;pic12f1822.h: 2575: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1822.h: 2578: typedef union {
+[; ;pic12f1822.h: 2579: struct {
+[; ;pic12f1822.h: 2580: unsigned ANSA0 :1;
+[; ;pic12f1822.h: 2581: unsigned ANSA1 :1;
+[; ;pic12f1822.h: 2582: unsigned ANSA2 :1;
+[; ;pic12f1822.h: 2583: unsigned :1;
+[; ;pic12f1822.h: 2584: unsigned ANSA4 :1;
+[; ;pic12f1822.h: 2585: };
+[; ;pic12f1822.h: 2586: struct {
+[; ;pic12f1822.h: 2587: unsigned ANSELA :5;
+[; ;pic12f1822.h: 2588: };
+[; ;pic12f1822.h: 2589: } ANSELAbits_t;
+[; ;pic12f1822.h: 2590: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1822.h: 2619: extern volatile unsigned short EEADR @ 0x191;
+"2621
+[; ;pic12f1822.h: 2621: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1822.h: 2625: extern volatile unsigned char EEADRL @ 0x191;
+"2627
+[; ;pic12f1822.h: 2627: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1822.h: 2630: typedef union {
+[; ;pic12f1822.h: 2631: struct {
+[; ;pic12f1822.h: 2632: unsigned EEADRL :8;
+[; ;pic12f1822.h: 2633: };
+[; ;pic12f1822.h: 2634: } EEADRLbits_t;
+[; ;pic12f1822.h: 2635: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1822.h: 2644: extern volatile unsigned char EEADRH @ 0x192;
+"2646
+[; ;pic12f1822.h: 2646: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1822.h: 2649: typedef union {
+[; ;pic12f1822.h: 2650: struct {
+[; ;pic12f1822.h: 2651: unsigned EEADRH :7;
+[; ;pic12f1822.h: 2652: };
+[; ;pic12f1822.h: 2653: } EEADRHbits_t;
+[; ;pic12f1822.h: 2654: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1822.h: 2663: extern volatile unsigned short EEDAT @ 0x193;
+"2665
+[; ;pic12f1822.h: 2665: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1822.h: 2669: extern volatile unsigned char EEDATL @ 0x193;
+"2671
+[; ;pic12f1822.h: 2671: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1822.h: 2674: extern volatile unsigned char EEDATA @ 0x193;
+"2676
+[; ;pic12f1822.h: 2676: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1822.h: 2679: typedef union {
+[; ;pic12f1822.h: 2680: struct {
+[; ;pic12f1822.h: 2681: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2682: };
+[; ;pic12f1822.h: 2683: } EEDATLbits_t;
+[; ;pic12f1822.h: 2684: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1822.h: 2692: typedef union {
+[; ;pic12f1822.h: 2693: struct {
+[; ;pic12f1822.h: 2694: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2695: };
+[; ;pic12f1822.h: 2696: } EEDATAbits_t;
+[; ;pic12f1822.h: 2697: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1822.h: 2706: extern volatile unsigned char EEDATH @ 0x194;
+"2708
+[; ;pic12f1822.h: 2708: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1822.h: 2711: typedef union {
+[; ;pic12f1822.h: 2712: struct {
+[; ;pic12f1822.h: 2713: unsigned EEDATH :6;
+[; ;pic12f1822.h: 2714: };
+[; ;pic12f1822.h: 2715: } EEDATHbits_t;
+[; ;pic12f1822.h: 2716: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1822.h: 2725: extern volatile unsigned char EECON1 @ 0x195;
+"2727
+[; ;pic12f1822.h: 2727: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1822.h: 2730: typedef union {
+[; ;pic12f1822.h: 2731: struct {
+[; ;pic12f1822.h: 2732: unsigned RD :1;
+[; ;pic12f1822.h: 2733: unsigned WR :1;
+[; ;pic12f1822.h: 2734: unsigned WREN :1;
+[; ;pic12f1822.h: 2735: unsigned WRERR :1;
+[; ;pic12f1822.h: 2736: unsigned FREE :1;
+[; ;pic12f1822.h: 2737: unsigned LWLO :1;
+[; ;pic12f1822.h: 2738: unsigned CFGS :1;
+[; ;pic12f1822.h: 2739: unsigned EEPGD :1;
+[; ;pic12f1822.h: 2740: };
+[; ;pic12f1822.h: 2741: } EECON1bits_t;
+[; ;pic12f1822.h: 2742: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1822.h: 2786: extern volatile unsigned char EECON2 @ 0x196;
+"2788
+[; ;pic12f1822.h: 2788: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1822.h: 2791: typedef union {
+[; ;pic12f1822.h: 2792: struct {
+[; ;pic12f1822.h: 2793: unsigned EECON2 :8;
+[; ;pic12f1822.h: 2794: };
+[; ;pic12f1822.h: 2795: } EECON2bits_t;
+[; ;pic12f1822.h: 2796: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1822.h: 2805: extern volatile unsigned char RCREG @ 0x199;
+"2807
+[; ;pic12f1822.h: 2807: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1822.h: 2810: typedef union {
+[; ;pic12f1822.h: 2811: struct {
+[; ;pic12f1822.h: 2812: unsigned RCREG :8;
+[; ;pic12f1822.h: 2813: };
+[; ;pic12f1822.h: 2814: } RCREGbits_t;
+[; ;pic12f1822.h: 2815: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1822.h: 2824: extern volatile unsigned char TXREG @ 0x19A;
+"2826
+[; ;pic12f1822.h: 2826: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1822.h: 2829: typedef union {
+[; ;pic12f1822.h: 2830: struct {
+[; ;pic12f1822.h: 2831: unsigned TXREG :8;
+[; ;pic12f1822.h: 2832: };
+[; ;pic12f1822.h: 2833: } TXREGbits_t;
+[; ;pic12f1822.h: 2834: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1822.h: 2843: extern volatile unsigned char SPBRGL @ 0x19B;
+"2845
+[; ;pic12f1822.h: 2845: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1822.h: 2848: extern volatile unsigned char SPBRG @ 0x19B;
+"2850
+[; ;pic12f1822.h: 2850: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1822.h: 2853: typedef union {
+[; ;pic12f1822.h: 2854: struct {
+[; ;pic12f1822.h: 2855: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2856: };
+[; ;pic12f1822.h: 2857: } SPBRGLbits_t;
+[; ;pic12f1822.h: 2858: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1822.h: 2866: typedef union {
+[; ;pic12f1822.h: 2867: struct {
+[; ;pic12f1822.h: 2868: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2869: };
+[; ;pic12f1822.h: 2870: } SPBRGbits_t;
+[; ;pic12f1822.h: 2871: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1822.h: 2880: extern volatile unsigned char SPBRGH @ 0x19C;
+"2882
+[; ;pic12f1822.h: 2882: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1822.h: 2885: typedef union {
+[; ;pic12f1822.h: 2886: struct {
+[; ;pic12f1822.h: 2887: unsigned SPBRGH :8;
+[; ;pic12f1822.h: 2888: };
+[; ;pic12f1822.h: 2889: } SPBRGHbits_t;
+[; ;pic12f1822.h: 2890: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1822.h: 2899: extern volatile unsigned char RCSTA @ 0x19D;
+"2901
+[; ;pic12f1822.h: 2901: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1822.h: 2904: typedef union {
+[; ;pic12f1822.h: 2905: struct {
+[; ;pic12f1822.h: 2906: unsigned RX9D :1;
+[; ;pic12f1822.h: 2907: unsigned OERR :1;
+[; ;pic12f1822.h: 2908: unsigned FERR :1;
+[; ;pic12f1822.h: 2909: unsigned ADDEN :1;
+[; ;pic12f1822.h: 2910: unsigned CREN :1;
+[; ;pic12f1822.h: 2911: unsigned SREN :1;
+[; ;pic12f1822.h: 2912: unsigned RX9 :1;
+[; ;pic12f1822.h: 2913: unsigned SPEN :1;
+[; ;pic12f1822.h: 2914: };
+[; ;pic12f1822.h: 2915: } RCSTAbits_t;
+[; ;pic12f1822.h: 2916: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1822.h: 2960: extern volatile unsigned char TXSTA @ 0x19E;
+"2962
+[; ;pic12f1822.h: 2962: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1822.h: 2965: typedef union {
+[; ;pic12f1822.h: 2966: struct {
+[; ;pic12f1822.h: 2967: unsigned TX9D :1;
+[; ;pic12f1822.h: 2968: unsigned TRMT :1;
+[; ;pic12f1822.h: 2969: unsigned BRGH :1;
+[; ;pic12f1822.h: 2970: unsigned SENDB :1;
+[; ;pic12f1822.h: 2971: unsigned SYNC :1;
+[; ;pic12f1822.h: 2972: unsigned TXEN :1;
+[; ;pic12f1822.h: 2973: unsigned TX9 :1;
+[; ;pic12f1822.h: 2974: unsigned CSRC :1;
+[; ;pic12f1822.h: 2975: };
+[; ;pic12f1822.h: 2976: } TXSTAbits_t;
+[; ;pic12f1822.h: 2977: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1822.h: 3021: extern volatile unsigned char BAUDCON @ 0x19F;
+"3023
+[; ;pic12f1822.h: 3023: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1822.h: 3026: typedef union {
+[; ;pic12f1822.h: 3027: struct {
+[; ;pic12f1822.h: 3028: unsigned ABDEN :1;
+[; ;pic12f1822.h: 3029: unsigned WUE :1;
+[; ;pic12f1822.h: 3030: unsigned :1;
+[; ;pic12f1822.h: 3031: unsigned BRG16 :1;
+[; ;pic12f1822.h: 3032: unsigned SCKP :1;
+[; ;pic12f1822.h: 3033: unsigned :1;
+[; ;pic12f1822.h: 3034: unsigned RCIDL :1;
+[; ;pic12f1822.h: 3035: unsigned ABDOVF :1;
+[; ;pic12f1822.h: 3036: };
+[; ;pic12f1822.h: 3037: } BAUDCONbits_t;
+[; ;pic12f1822.h: 3038: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1822.h: 3072: extern volatile unsigned char WPUA @ 0x20C;
+"3074
+[; ;pic12f1822.h: 3074: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1822.h: 3077: typedef union {
+[; ;pic12f1822.h: 3078: struct {
+[; ;pic12f1822.h: 3079: unsigned WPUA0 :1;
+[; ;pic12f1822.h: 3080: unsigned WPUA1 :1;
+[; ;pic12f1822.h: 3081: unsigned WPUA2 :1;
+[; ;pic12f1822.h: 3082: unsigned WPUA3 :1;
+[; ;pic12f1822.h: 3083: unsigned WPUA4 :1;
+[; ;pic12f1822.h: 3084: unsigned WPUA5 :1;
+[; ;pic12f1822.h: 3085: };
+[; ;pic12f1822.h: 3086: struct {
+[; ;pic12f1822.h: 3087: unsigned WPUA :6;
+[; ;pic12f1822.h: 3088: };
+[; ;pic12f1822.h: 3089: } WPUAbits_t;
+[; ;pic12f1822.h: 3090: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1822.h: 3129: extern volatile unsigned char SSP1BUF @ 0x211;
+"3131
+[; ;pic12f1822.h: 3131: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3134: extern volatile unsigned char SSPBUF @ 0x211;
+"3136
+[; ;pic12f1822.h: 3136: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3139: typedef union {
+[; ;pic12f1822.h: 3140: struct {
+[; ;pic12f1822.h: 3141: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3142: };
+[; ;pic12f1822.h: 3143: } SSP1BUFbits_t;
+[; ;pic12f1822.h: 3144: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1822.h: 3152: typedef union {
+[; ;pic12f1822.h: 3153: struct {
+[; ;pic12f1822.h: 3154: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3155: };
+[; ;pic12f1822.h: 3156: } SSPBUFbits_t;
+[; ;pic12f1822.h: 3157: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1822.h: 3166: extern volatile unsigned char SSP1ADD @ 0x212;
+"3168
+[; ;pic12f1822.h: 3168: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3171: extern volatile unsigned char SSPADD @ 0x212;
+"3173
+[; ;pic12f1822.h: 3173: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3176: typedef union {
+[; ;pic12f1822.h: 3177: struct {
+[; ;pic12f1822.h: 3178: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3179: };
+[; ;pic12f1822.h: 3180: } SSP1ADDbits_t;
+[; ;pic12f1822.h: 3181: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1822.h: 3189: typedef union {
+[; ;pic12f1822.h: 3190: struct {
+[; ;pic12f1822.h: 3191: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3192: };
+[; ;pic12f1822.h: 3193: } SSPADDbits_t;
+[; ;pic12f1822.h: 3194: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1822.h: 3203: extern volatile unsigned char SSP1MSK @ 0x213;
+"3205
+[; ;pic12f1822.h: 3205: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3208: extern volatile unsigned char SSPMSK @ 0x213;
+"3210
+[; ;pic12f1822.h: 3210: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3213: typedef union {
+[; ;pic12f1822.h: 3214: struct {
+[; ;pic12f1822.h: 3215: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3216: };
+[; ;pic12f1822.h: 3217: } SSP1MSKbits_t;
+[; ;pic12f1822.h: 3218: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1822.h: 3226: typedef union {
+[; ;pic12f1822.h: 3227: struct {
+[; ;pic12f1822.h: 3228: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3229: };
+[; ;pic12f1822.h: 3230: } SSPMSKbits_t;
+[; ;pic12f1822.h: 3231: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1822.h: 3240: extern volatile unsigned char SSP1STAT @ 0x214;
+"3242
+[; ;pic12f1822.h: 3242: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3245: extern volatile unsigned char SSPSTAT @ 0x214;
+"3247
+[; ;pic12f1822.h: 3247: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3250: typedef union {
+[; ;pic12f1822.h: 3251: struct {
+[; ;pic12f1822.h: 3252: unsigned BF :1;
+[; ;pic12f1822.h: 3253: unsigned UA :1;
+[; ;pic12f1822.h: 3254: unsigned R_nW :1;
+[; ;pic12f1822.h: 3255: unsigned S :1;
+[; ;pic12f1822.h: 3256: unsigned P :1;
+[; ;pic12f1822.h: 3257: unsigned D_nA :1;
+[; ;pic12f1822.h: 3258: unsigned CKE :1;
+[; ;pic12f1822.h: 3259: unsigned SMP :1;
+[; ;pic12f1822.h: 3260: };
+[; ;pic12f1822.h: 3261: } SSP1STATbits_t;
+[; ;pic12f1822.h: 3262: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1822.h: 3305: typedef union {
+[; ;pic12f1822.h: 3306: struct {
+[; ;pic12f1822.h: 3307: unsigned BF :1;
+[; ;pic12f1822.h: 3308: unsigned UA :1;
+[; ;pic12f1822.h: 3309: unsigned R_nW :1;
+[; ;pic12f1822.h: 3310: unsigned S :1;
+[; ;pic12f1822.h: 3311: unsigned P :1;
+[; ;pic12f1822.h: 3312: unsigned D_nA :1;
+[; ;pic12f1822.h: 3313: unsigned CKE :1;
+[; ;pic12f1822.h: 3314: unsigned SMP :1;
+[; ;pic12f1822.h: 3315: };
+[; ;pic12f1822.h: 3316: } SSPSTATbits_t;
+[; ;pic12f1822.h: 3317: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1822.h: 3361: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3363
+[; ;pic12f1822.h: 3363: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3366: extern volatile unsigned char SSPCON1 @ 0x215;
+"3368
+[; ;pic12f1822.h: 3368: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3370: extern volatile unsigned char SSPCON @ 0x215;
+"3372
+[; ;pic12f1822.h: 3372: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1822.h: 3375: typedef union {
+[; ;pic12f1822.h: 3376: struct {
+[; ;pic12f1822.h: 3377: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3378: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3379: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3380: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3381: unsigned CKP :1;
+[; ;pic12f1822.h: 3382: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3383: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3384: unsigned WCOL :1;
+[; ;pic12f1822.h: 3385: };
+[; ;pic12f1822.h: 3386: struct {
+[; ;pic12f1822.h: 3387: unsigned SSPM :4;
+[; ;pic12f1822.h: 3388: };
+[; ;pic12f1822.h: 3389: } SSP1CON1bits_t;
+[; ;pic12f1822.h: 3390: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1822.h: 3438: typedef union {
+[; ;pic12f1822.h: 3439: struct {
+[; ;pic12f1822.h: 3440: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3441: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3442: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3443: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3444: unsigned CKP :1;
+[; ;pic12f1822.h: 3445: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3446: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3447: unsigned WCOL :1;
+[; ;pic12f1822.h: 3448: };
+[; ;pic12f1822.h: 3449: struct {
+[; ;pic12f1822.h: 3450: unsigned SSPM :4;
+[; ;pic12f1822.h: 3451: };
+[; ;pic12f1822.h: 3452: } SSPCON1bits_t;
+[; ;pic12f1822.h: 3453: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1822.h: 3500: typedef union {
+[; ;pic12f1822.h: 3501: struct {
+[; ;pic12f1822.h: 3502: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3503: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3504: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3505: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3506: unsigned CKP :1;
+[; ;pic12f1822.h: 3507: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3508: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3509: unsigned WCOL :1;
+[; ;pic12f1822.h: 3510: };
+[; ;pic12f1822.h: 3511: struct {
+[; ;pic12f1822.h: 3512: unsigned SSPM :4;
+[; ;pic12f1822.h: 3513: };
+[; ;pic12f1822.h: 3514: } SSPCONbits_t;
+[; ;pic12f1822.h: 3515: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1822.h: 3564: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3566
+[; ;pic12f1822.h: 3566: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3569: extern volatile unsigned char SSPCON2 @ 0x216;
+"3571
+[; ;pic12f1822.h: 3571: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3574: typedef union {
+[; ;pic12f1822.h: 3575: struct {
+[; ;pic12f1822.h: 3576: unsigned SEN :1;
+[; ;pic12f1822.h: 3577: unsigned RSEN :1;
+[; ;pic12f1822.h: 3578: unsigned PEN :1;
+[; ;pic12f1822.h: 3579: unsigned RCEN :1;
+[; ;pic12f1822.h: 3580: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3581: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3582: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3583: unsigned GCEN :1;
+[; ;pic12f1822.h: 3584: };
+[; ;pic12f1822.h: 3585: } SSP1CON2bits_t;
+[; ;pic12f1822.h: 3586: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1822.h: 3629: typedef union {
+[; ;pic12f1822.h: 3630: struct {
+[; ;pic12f1822.h: 3631: unsigned SEN :1;
+[; ;pic12f1822.h: 3632: unsigned RSEN :1;
+[; ;pic12f1822.h: 3633: unsigned PEN :1;
+[; ;pic12f1822.h: 3634: unsigned RCEN :1;
+[; ;pic12f1822.h: 3635: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3636: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3637: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3638: unsigned GCEN :1;
+[; ;pic12f1822.h: 3639: };
+[; ;pic12f1822.h: 3640: } SSPCON2bits_t;
+[; ;pic12f1822.h: 3641: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1822.h: 3685: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3687
+[; ;pic12f1822.h: 3687: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3690: extern volatile unsigned char SSPCON3 @ 0x217;
+"3692
+[; ;pic12f1822.h: 3692: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3695: typedef union {
+[; ;pic12f1822.h: 3696: struct {
+[; ;pic12f1822.h: 3697: unsigned DHEN :1;
+[; ;pic12f1822.h: 3698: unsigned AHEN :1;
+[; ;pic12f1822.h: 3699: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3700: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3701: unsigned BOEN :1;
+[; ;pic12f1822.h: 3702: unsigned SCIE :1;
+[; ;pic12f1822.h: 3703: unsigned PCIE :1;
+[; ;pic12f1822.h: 3704: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3705: };
+[; ;pic12f1822.h: 3706: } SSP1CON3bits_t;
+[; ;pic12f1822.h: 3707: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1822.h: 3750: typedef union {
+[; ;pic12f1822.h: 3751: struct {
+[; ;pic12f1822.h: 3752: unsigned DHEN :1;
+[; ;pic12f1822.h: 3753: unsigned AHEN :1;
+[; ;pic12f1822.h: 3754: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3755: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3756: unsigned BOEN :1;
+[; ;pic12f1822.h: 3757: unsigned SCIE :1;
+[; ;pic12f1822.h: 3758: unsigned PCIE :1;
+[; ;pic12f1822.h: 3759: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3760: };
+[; ;pic12f1822.h: 3761: } SSPCON3bits_t;
+[; ;pic12f1822.h: 3762: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1822.h: 3806: extern volatile unsigned char CCPR1L @ 0x291;
+"3808
+[; ;pic12f1822.h: 3808: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1822.h: 3811: typedef union {
+[; ;pic12f1822.h: 3812: struct {
+[; ;pic12f1822.h: 3813: unsigned CCPR1L :8;
+[; ;pic12f1822.h: 3814: };
+[; ;pic12f1822.h: 3815: } CCPR1Lbits_t;
+[; ;pic12f1822.h: 3816: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1822.h: 3825: extern volatile unsigned char CCPR1H @ 0x292;
+"3827
+[; ;pic12f1822.h: 3827: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1822.h: 3830: typedef union {
+[; ;pic12f1822.h: 3831: struct {
+[; ;pic12f1822.h: 3832: unsigned CCPR1H :8;
+[; ;pic12f1822.h: 3833: };
+[; ;pic12f1822.h: 3834: } CCPR1Hbits_t;
+[; ;pic12f1822.h: 3835: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1822.h: 3844: extern volatile unsigned char CCP1CON @ 0x293;
+"3846
+[; ;pic12f1822.h: 3846: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1822.h: 3849: typedef union {
+[; ;pic12f1822.h: 3850: struct {
+[; ;pic12f1822.h: 3851: unsigned CCP1M0 :1;
+[; ;pic12f1822.h: 3852: unsigned CCP1M1 :1;
+[; ;pic12f1822.h: 3853: unsigned CCP1M2 :1;
+[; ;pic12f1822.h: 3854: unsigned CCP1M3 :1;
+[; ;pic12f1822.h: 3855: unsigned DC1B0 :1;
+[; ;pic12f1822.h: 3856: unsigned DC1B1 :1;
+[; ;pic12f1822.h: 3857: unsigned P1M0 :1;
+[; ;pic12f1822.h: 3858: unsigned P1M1 :1;
+[; ;pic12f1822.h: 3859: };
+[; ;pic12f1822.h: 3860: struct {
+[; ;pic12f1822.h: 3861: unsigned CCP1M :4;
+[; ;pic12f1822.h: 3862: unsigned DC1B :2;
+[; ;pic12f1822.h: 3863: unsigned P1M :2;
+[; ;pic12f1822.h: 3864: };
+[; ;pic12f1822.h: 3865: } CCP1CONbits_t;
+[; ;pic12f1822.h: 3866: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1822.h: 3925: extern volatile unsigned char PWM1CON @ 0x294;
+"3927
+[; ;pic12f1822.h: 3927: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1822.h: 3930: typedef union {
+[; ;pic12f1822.h: 3931: struct {
+[; ;pic12f1822.h: 3932: unsigned P1DC0 :1;
+[; ;pic12f1822.h: 3933: unsigned P1DC1 :1;
+[; ;pic12f1822.h: 3934: unsigned P1DC2 :1;
+[; ;pic12f1822.h: 3935: unsigned P1DC3 :1;
+[; ;pic12f1822.h: 3936: unsigned P1DC4 :1;
+[; ;pic12f1822.h: 3937: unsigned P1DC5 :1;
+[; ;pic12f1822.h: 3938: unsigned P1DC6 :1;
+[; ;pic12f1822.h: 3939: unsigned P1RSEN :1;
+[; ;pic12f1822.h: 3940: };
+[; ;pic12f1822.h: 3941: struct {
+[; ;pic12f1822.h: 3942: unsigned P1DC :7;
+[; ;pic12f1822.h: 3943: };
+[; ;pic12f1822.h: 3944: } PWM1CONbits_t;
+[; ;pic12f1822.h: 3945: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1822.h: 3994: extern volatile unsigned char CCP1AS @ 0x295;
+"3996
+[; ;pic12f1822.h: 3996: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 3999: extern volatile unsigned char ECCP1AS @ 0x295;
+"4001
+[; ;pic12f1822.h: 4001: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 4004: typedef union {
+[; ;pic12f1822.h: 4005: struct {
+[; ;pic12f1822.h: 4006: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4007: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4008: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4009: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4010: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4011: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4012: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4013: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4014: };
+[; ;pic12f1822.h: 4015: struct {
+[; ;pic12f1822.h: 4016: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4017: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4018: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4019: };
+[; ;pic12f1822.h: 4020: } CCP1ASbits_t;
+[; ;pic12f1822.h: 4021: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4079: typedef union {
+[; ;pic12f1822.h: 4080: struct {
+[; ;pic12f1822.h: 4081: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4082: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4083: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4084: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4085: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4086: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4087: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4088: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4089: };
+[; ;pic12f1822.h: 4090: struct {
+[; ;pic12f1822.h: 4091: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4092: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4093: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4094: };
+[; ;pic12f1822.h: 4095: } ECCP1ASbits_t;
+[; ;pic12f1822.h: 4096: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4155: extern volatile unsigned char PSTR1CON @ 0x296;
+"4157
+[; ;pic12f1822.h: 4157: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1822.h: 4160: typedef union {
+[; ;pic12f1822.h: 4161: struct {
+[; ;pic12f1822.h: 4162: unsigned STR1A :1;
+[; ;pic12f1822.h: 4163: unsigned STR1B :1;
+[; ;pic12f1822.h: 4164: unsigned STR1C :1;
+[; ;pic12f1822.h: 4165: unsigned STR1D :1;
+[; ;pic12f1822.h: 4166: unsigned STR1SYNC :1;
+[; ;pic12f1822.h: 4167: };
+[; ;pic12f1822.h: 4168: } PSTR1CONbits_t;
+[; ;pic12f1822.h: 4169: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1822.h: 4198: extern volatile unsigned char IOCAP @ 0x391;
+"4200
+[; ;pic12f1822.h: 4200: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1822.h: 4203: typedef union {
+[; ;pic12f1822.h: 4204: struct {
+[; ;pic12f1822.h: 4205: unsigned IOCAP0 :1;
+[; ;pic12f1822.h: 4206: unsigned IOCAP1 :1;
+[; ;pic12f1822.h: 4207: unsigned IOCAP2 :1;
+[; ;pic12f1822.h: 4208: unsigned IOCAP3 :1;
+[; ;pic12f1822.h: 4209: unsigned IOCAP4 :1;
+[; ;pic12f1822.h: 4210: unsigned IOCAP5 :1;
+[; ;pic12f1822.h: 4211: };
+[; ;pic12f1822.h: 4212: struct {
+[; ;pic12f1822.h: 4213: unsigned IOCAP :6;
+[; ;pic12f1822.h: 4214: };
+[; ;pic12f1822.h: 4215: } IOCAPbits_t;
+[; ;pic12f1822.h: 4216: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1822.h: 4255: extern volatile unsigned char IOCAN @ 0x392;
+"4257
+[; ;pic12f1822.h: 4257: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1822.h: 4260: typedef union {
+[; ;pic12f1822.h: 4261: struct {
+[; ;pic12f1822.h: 4262: unsigned IOCAN0 :1;
+[; ;pic12f1822.h: 4263: unsigned IOCAN1 :1;
+[; ;pic12f1822.h: 4264: unsigned IOCAN2 :1;
+[; ;pic12f1822.h: 4265: unsigned IOCAN3 :1;
+[; ;pic12f1822.h: 4266: unsigned IOCAN4 :1;
+[; ;pic12f1822.h: 4267: unsigned IOCAN5 :1;
+[; ;pic12f1822.h: 4268: };
+[; ;pic12f1822.h: 4269: struct {
+[; ;pic12f1822.h: 4270: unsigned IOCAN :6;
+[; ;pic12f1822.h: 4271: };
+[; ;pic12f1822.h: 4272: } IOCANbits_t;
+[; ;pic12f1822.h: 4273: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1822.h: 4312: extern volatile unsigned char IOCAF @ 0x393;
+"4314
+[; ;pic12f1822.h: 4314: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1822.h: 4317: typedef union {
+[; ;pic12f1822.h: 4318: struct {
+[; ;pic12f1822.h: 4319: unsigned IOCAF0 :1;
+[; ;pic12f1822.h: 4320: unsigned IOCAF1 :1;
+[; ;pic12f1822.h: 4321: unsigned IOCAF2 :1;
+[; ;pic12f1822.h: 4322: unsigned IOCAF3 :1;
+[; ;pic12f1822.h: 4323: unsigned IOCAF4 :1;
+[; ;pic12f1822.h: 4324: unsigned IOCAF5 :1;
+[; ;pic12f1822.h: 4325: };
+[; ;pic12f1822.h: 4326: struct {
+[; ;pic12f1822.h: 4327: unsigned IOCAF :6;
+[; ;pic12f1822.h: 4328: };
+[; ;pic12f1822.h: 4329: } IOCAFbits_t;
+[; ;pic12f1822.h: 4330: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1822.h: 4369: extern volatile unsigned char CLKRCON @ 0x39A;
+"4371
+[; ;pic12f1822.h: 4371: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1822.h: 4374: typedef union {
+[; ;pic12f1822.h: 4375: struct {
+[; ;pic12f1822.h: 4376: unsigned CLKRDIV0 :1;
+[; ;pic12f1822.h: 4377: unsigned CLKRDIV1 :1;
+[; ;pic12f1822.h: 4378: unsigned CLKRDIV2 :1;
+[; ;pic12f1822.h: 4379: unsigned CLKRDC0 :1;
+[; ;pic12f1822.h: 4380: unsigned CLKRDC1 :1;
+[; ;pic12f1822.h: 4381: unsigned CLKRSLR :1;
+[; ;pic12f1822.h: 4382: unsigned CLKROE :1;
+[; ;pic12f1822.h: 4383: unsigned CLKREN :1;
+[; ;pic12f1822.h: 4384: };
+[; ;pic12f1822.h: 4385: struct {
+[; ;pic12f1822.h: 4386: unsigned CLKRDIV :3;
+[; ;pic12f1822.h: 4387: unsigned CLKRDC :2;
+[; ;pic12f1822.h: 4388: };
+[; ;pic12f1822.h: 4389: } CLKRCONbits_t;
+[; ;pic12f1822.h: 4390: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1822.h: 4444: extern volatile unsigned char MDCON @ 0x39C;
+"4446
+[; ;pic12f1822.h: 4446: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1822.h: 4449: typedef union {
+[; ;pic12f1822.h: 4450: struct {
+[; ;pic12f1822.h: 4451: unsigned MDBIT :1;
+[; ;pic12f1822.h: 4452: unsigned :2;
+[; ;pic12f1822.h: 4453: unsigned MDOUT :1;
+[; ;pic12f1822.h: 4454: unsigned MDOPOL :1;
+[; ;pic12f1822.h: 4455: unsigned MDSLR :1;
+[; ;pic12f1822.h: 4456: unsigned MDOE :1;
+[; ;pic12f1822.h: 4457: unsigned MDEN :1;
+[; ;pic12f1822.h: 4458: };
+[; ;pic12f1822.h: 4459: } MDCONbits_t;
+[; ;pic12f1822.h: 4460: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1822.h: 4494: extern volatile unsigned char MDSRC @ 0x39D;
+"4496
+[; ;pic12f1822.h: 4496: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1822.h: 4499: typedef union {
+[; ;pic12f1822.h: 4500: struct {
+[; ;pic12f1822.h: 4501: unsigned MDMS0 :1;
+[; ;pic12f1822.h: 4502: unsigned MDMS1 :1;
+[; ;pic12f1822.h: 4503: unsigned MDMS2 :1;
+[; ;pic12f1822.h: 4504: unsigned MDMS3 :1;
+[; ;pic12f1822.h: 4505: unsigned :3;
+[; ;pic12f1822.h: 4506: unsigned MDMSODIS :1;
+[; ;pic12f1822.h: 4507: };
+[; ;pic12f1822.h: 4508: struct {
+[; ;pic12f1822.h: 4509: unsigned MDMS :4;
+[; ;pic12f1822.h: 4510: };
+[; ;pic12f1822.h: 4511: } MDSRCbits_t;
+[; ;pic12f1822.h: 4512: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1822.h: 4546: extern volatile unsigned char MDCARL @ 0x39E;
+"4548
+[; ;pic12f1822.h: 4548: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1822.h: 4551: typedef union {
+[; ;pic12f1822.h: 4552: struct {
+[; ;pic12f1822.h: 4553: unsigned MDCL0 :1;
+[; ;pic12f1822.h: 4554: unsigned MDCL1 :1;
+[; ;pic12f1822.h: 4555: unsigned MDCL2 :1;
+[; ;pic12f1822.h: 4556: unsigned MDCL3 :1;
+[; ;pic12f1822.h: 4557: unsigned :1;
+[; ;pic12f1822.h: 4558: unsigned MDCLSYNC :1;
+[; ;pic12f1822.h: 4559: unsigned MDCLPOL :1;
+[; ;pic12f1822.h: 4560: unsigned MDCLODIS :1;
+[; ;pic12f1822.h: 4561: };
+[; ;pic12f1822.h: 4562: struct {
+[; ;pic12f1822.h: 4563: unsigned MDCL :4;
+[; ;pic12f1822.h: 4564: };
+[; ;pic12f1822.h: 4565: } MDCARLbits_t;
+[; ;pic12f1822.h: 4566: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1822.h: 4610: extern volatile unsigned char MDCARH @ 0x39F;
+"4612
+[; ;pic12f1822.h: 4612: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1822.h: 4615: typedef union {
+[; ;pic12f1822.h: 4616: struct {
+[; ;pic12f1822.h: 4617: unsigned MDCH0 :1;
+[; ;pic12f1822.h: 4618: unsigned MDCH1 :1;
+[; ;pic12f1822.h: 4619: unsigned MDCH2 :1;
+[; ;pic12f1822.h: 4620: unsigned MDCH3 :1;
+[; ;pic12f1822.h: 4621: unsigned :1;
+[; ;pic12f1822.h: 4622: unsigned MDCHSYNC :1;
+[; ;pic12f1822.h: 4623: unsigned MDCHPOL :1;
+[; ;pic12f1822.h: 4624: unsigned MDCHODIS :1;
+[; ;pic12f1822.h: 4625: };
+[; ;pic12f1822.h: 4626: struct {
+[; ;pic12f1822.h: 4627: unsigned MDCH :4;
+[; ;pic12f1822.h: 4628: };
+[; ;pic12f1822.h: 4629: } MDCARHbits_t;
+[; ;pic12f1822.h: 4630: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1822.h: 4674: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4676
+[; ;pic12f1822.h: 4676: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1822.h: 4679: typedef union {
+[; ;pic12f1822.h: 4680: struct {
+[; ;pic12f1822.h: 4681: unsigned C_SHAD :1;
+[; ;pic12f1822.h: 4682: unsigned DC_SHAD :1;
+[; ;pic12f1822.h: 4683: unsigned Z_SHAD :1;
+[; ;pic12f1822.h: 4684: };
+[; ;pic12f1822.h: 4685: } STATUS_SHADbits_t;
+[; ;pic12f1822.h: 4686: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1822.h: 4705: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4707
+[; ;pic12f1822.h: 4707: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1822.h: 4710: typedef union {
+[; ;pic12f1822.h: 4711: struct {
+[; ;pic12f1822.h: 4712: unsigned WREG_SHAD :8;
+[; ;pic12f1822.h: 4713: };
+[; ;pic12f1822.h: 4714: } WREG_SHADbits_t;
+[; ;pic12f1822.h: 4715: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1822.h: 4724: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4726
+[; ;pic12f1822.h: 4726: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1822.h: 4729: typedef union {
+[; ;pic12f1822.h: 4730: struct {
+[; ;pic12f1822.h: 4731: unsigned BSR_SHAD :5;
+[; ;pic12f1822.h: 4732: };
+[; ;pic12f1822.h: 4733: } BSR_SHADbits_t;
+[; ;pic12f1822.h: 4734: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1822.h: 4743: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4745
+[; ;pic12f1822.h: 4745: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1822.h: 4748: typedef union {
+[; ;pic12f1822.h: 4749: struct {
+[; ;pic12f1822.h: 4750: unsigned PCLATH_SHAD :7;
+[; ;pic12f1822.h: 4751: };
+[; ;pic12f1822.h: 4752: } PCLATH_SHADbits_t;
+[; ;pic12f1822.h: 4753: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1822.h: 4762: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4764
+[; ;pic12f1822.h: 4764: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1822.h: 4767: typedef union {
+[; ;pic12f1822.h: 4768: struct {
+[; ;pic12f1822.h: 4769: unsigned FSR0L_SHAD :8;
+[; ;pic12f1822.h: 4770: };
+[; ;pic12f1822.h: 4771: } FSR0L_SHADbits_t;
+[; ;pic12f1822.h: 4772: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1822.h: 4781: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4783
+[; ;pic12f1822.h: 4783: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1822.h: 4786: typedef union {
+[; ;pic12f1822.h: 4787: struct {
+[; ;pic12f1822.h: 4788: unsigned FSR0H_SHAD :8;
+[; ;pic12f1822.h: 4789: };
+[; ;pic12f1822.h: 4790: } FSR0H_SHADbits_t;
+[; ;pic12f1822.h: 4791: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1822.h: 4800: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4802
+[; ;pic12f1822.h: 4802: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1822.h: 4805: typedef union {
+[; ;pic12f1822.h: 4806: struct {
+[; ;pic12f1822.h: 4807: unsigned FSR1L_SHAD :8;
+[; ;pic12f1822.h: 4808: };
+[; ;pic12f1822.h: 4809: } FSR1L_SHADbits_t;
+[; ;pic12f1822.h: 4810: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1822.h: 4819: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4821
+[; ;pic12f1822.h: 4821: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1822.h: 4824: typedef union {
+[; ;pic12f1822.h: 4825: struct {
+[; ;pic12f1822.h: 4826: unsigned FSR1H_SHAD :8;
+[; ;pic12f1822.h: 4827: };
+[; ;pic12f1822.h: 4828: } FSR1H_SHADbits_t;
+[; ;pic12f1822.h: 4829: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1822.h: 4838: extern volatile unsigned char STKPTR @ 0xFED;
+"4840
+[; ;pic12f1822.h: 4840: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1822.h: 4843: typedef union {
+[; ;pic12f1822.h: 4844: struct {
+[; ;pic12f1822.h: 4845: unsigned STKPTR :5;
+[; ;pic12f1822.h: 4846: };
+[; ;pic12f1822.h: 4847: } STKPTRbits_t;
+[; ;pic12f1822.h: 4848: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1822.h: 4857: extern volatile unsigned char TOSL @ 0xFEE;
+"4859
+[; ;pic12f1822.h: 4859: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1822.h: 4862: typedef union {
+[; ;pic12f1822.h: 4863: struct {
+[; ;pic12f1822.h: 4864: unsigned TOSL :8;
+[; ;pic12f1822.h: 4865: };
+[; ;pic12f1822.h: 4866: } TOSLbits_t;
+[; ;pic12f1822.h: 4867: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1822.h: 4876: extern volatile unsigned char TOSH @ 0xFEF;
+"4878
+[; ;pic12f1822.h: 4878: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1822.h: 4881: typedef union {
+[; ;pic12f1822.h: 4882: struct {
+[; ;pic12f1822.h: 4883: unsigned TOSH :7;
+[; ;pic12f1822.h: 4884: };
+[; ;pic12f1822.h: 4885: } TOSHbits_t;
+[; ;pic12f1822.h: 4886: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1822.h: 4901: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1822.h: 4903: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1822.h: 4905: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1822.h: 4907: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1822.h: 4909: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1822.h: 4911: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1822.h: 4913: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1822.h: 4915: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1822.h: 4917: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1822.h: 4919: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1822.h: 4921: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1822.h: 4923: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1822.h: 4925: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1822.h: 4927: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 4929: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1822.h: 4931: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1822.h: 4933: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1822.h: 4935: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1822.h: 4937: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1822.h: 4939: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1822.h: 4941: extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4943: extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4945: extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 4947: extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4949: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1822.h: 4951: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1822.h: 4953: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1822.h: 4955: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1822.h: 4957: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1822.h: 4959: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1822.h: 4961: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1822.h: 4963: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1822.h: 4965: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1822.h: 4967: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1822.h: 4969: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1822.h: 4971: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1822.h: 4973: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1822.h: 4975: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1822.h: 4977: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1822.h: 4979: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1822.h: 4981: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1822.h: 4983: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1822.h: 4985: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1822.h: 4987: extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4989: extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4991: extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4993: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1822.h: 4995: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1822.h: 4997: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1822.h: 4999: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1822.h: 5001: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1822.h: 5003: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1822.h: 5005: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1822.h: 5007: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1822.h: 5009: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1822.h: 5011: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1822.h: 5013: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1822.h: 5015: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1822.h: 5017: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1822.h: 5019: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1822.h: 5021: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1822.h: 5023: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1822.h: 5025: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1822.h: 5027: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1822.h: 5029: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1822.h: 5031: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1822.h: 5033: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1822.h: 5035: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1822.h: 5037: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1822.h: 5039: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1822.h: 5041: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1822.h: 5043: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1822.h: 5045: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1822.h: 5047: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1822.h: 5049: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1822.h: 5051: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1822.h: 5053: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1822.h: 5055: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1822.h: 5057: extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5059: extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5061: extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5063: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1822.h: 5065: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1822.h: 5067: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1822.h: 5069: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1822.h: 5071: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1822.h: 5073: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1822.h: 5075: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1822.h: 5077: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1822.h: 5079: extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5081: extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5083: extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5085: extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5087: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1822.h: 5089: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1822.h: 5091: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1822.h: 5093: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1822.h: 5095: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1822.h: 5097: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1822.h: 5099: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1822.h: 5101: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1822.h: 5103: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1822.h: 5105: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1822.h: 5107: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1822.h: 5109: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1822.h: 5111: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1822.h: 5113: extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5115: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1822.h: 5117: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1822.h: 5119: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1822.h: 5121: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1822.h: 5123: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1822.h: 5125: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1822.h: 5127: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1822.h: 5129: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1822.h: 5131: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1822.h: 5133: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1822.h: 5135: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1822.h: 5137: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1822.h: 5139: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1822.h: 5141: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1822.h: 5143: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1822.h: 5145: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1822.h: 5147: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1822.h: 5149: extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5151: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1822.h: 5153: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1822.h: 5155: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1822.h: 5157: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1822.h: 5159: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1822.h: 5161: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5163: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5165: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1822.h: 5167: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1822.h: 5169: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1822.h: 5171: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1822.h: 5173: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1822.h: 5175: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1822.h: 5177: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1822.h: 5179: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1822.h: 5181: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1822.h: 5183: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1822.h: 5185: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1822.h: 5187: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1822.h: 5189: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1822.h: 5191: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1822.h: 5193: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1822.h: 5195: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1822.h: 5197: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1822.h: 5199: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1822.h: 5201: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1822.h: 5203: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1822.h: 5205: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1822.h: 5207: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1822.h: 5209: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1822.h: 5211: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1822.h: 5213: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1822.h: 5215: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1822.h: 5217: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1822.h: 5219: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1822.h: 5221: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1822.h: 5223: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1822.h: 5225: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1822.h: 5227: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1822.h: 5229: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1822.h: 5231: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1822.h: 5233: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1822.h: 5235: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1822.h: 5237: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1822.h: 5239: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1822.h: 5241: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1822.h: 5243: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1822.h: 5245: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1822.h: 5247: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1822.h: 5249: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1822.h: 5251: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1822.h: 5253: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1822.h: 5255: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1822.h: 5257: extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5259: extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5261: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1822.h: 5263: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1822.h: 5265: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1822.h: 5267: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1822.h: 5269: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1822.h: 5271: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1822.h: 5273: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1822.h: 5275: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1822.h: 5277: extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5279: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1822.h: 5281: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1822.h: 5283: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1822.h: 5285: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1822.h: 5287: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1822.h: 5289: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1822.h: 5291: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1822.h: 5293: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1822.h: 5295: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1822.h: 5297: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1822.h: 5299: extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5301: extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5303: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1822.h: 5305: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1822.h: 5307: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1822.h: 5309: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1822.h: 5311: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1822.h: 5313: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1822.h: 5315: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1822.h: 5317: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1822.h: 5319: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1822.h: 5321: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1822.h: 5323: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1822.h: 5325: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1822.h: 5327: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1822.h: 5329: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1822.h: 5331: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1822.h: 5333: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1822.h: 5335: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1822.h: 5337: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1822.h: 5339: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1822.h: 5341: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1822.h: 5343: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1822.h: 5345: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1822.h: 5347: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1822.h: 5349: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1822.h: 5351: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1822.h: 5353: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1822.h: 5355: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5357: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5359: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5361: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5363: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5365: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5367: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1822.h: 5369: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1822.h: 5371: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1822.h: 5373: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1822.h: 5375: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1822.h: 5377: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1822.h: 5379: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1822.h: 5381: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1822.h: 5383: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1822.h: 5385: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1822.h: 5387: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1822.h: 5389: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1822.h: 5391: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1822.h: 5393: extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5395: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1822.h: 5397: extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5399: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1822.h: 5401: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1822.h: 5403: extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5405: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1822.h: 5407: extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5409: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5411: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5413: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1822.h: 5415: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1822.h: 5417: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1822.h: 5419: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1822.h: 5421: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1822.h: 5423: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1822.h: 5425: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1822.h: 5427: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1822.h: 5429: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1822.h: 5431: extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5433: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1822.h: 5435: extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5437: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1822.h: 5439: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1822.h: 5441: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1822.h: 5443: extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5445: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1822.h: 5447: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1822.h: 5449: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1822.h: 5451: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1822.h: 5453: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1822.h: 5455: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1822.h: 5457: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1822.h: 5459: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5461: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1822.h: 5463: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1822.h: 5465: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1822.h: 5467: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1822.h: 5469: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1822.h: 5471: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1822.h: 5473: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1822.h: 5475: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1822.h: 5477: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5479: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1822.h: 5481: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1822.h: 5483: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1822.h: 5485: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1822.h: 5487: extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+[; ;pic12f1822.h: 5489: extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+[; ;pic12f1822.h: 5491: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1822.h: 5493: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1822.h: 5495: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1822.h: 5497: extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5499: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5501: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5503: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5505: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5507: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1822.h: 5509: extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5511: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1822.h: 5513: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1822.h: 5515: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5517: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5519: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1822.h: 5521: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1822.h: 5523: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1822.h: 5525: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1822.h: 5527: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1822.h: 5529: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1822.h: 5531: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1822.h: 5533: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1822.h: 5535: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1822.h: 5537: extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5539: extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5541: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1822.h: 5543: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1822.h: 5545: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1822.h: 5547: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1822.h: 5549: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1822.h: 5551: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1822.h: 5553: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5555: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5557: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5559: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5561: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1822.h: 5563: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1822.h: 5565: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1822.h: 5567: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1822.h: 5569: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1822.h: 5571: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1822.h: 5573: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1822.h: 5575: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1822.h: 5577: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1822.h: 5579: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1822.h: 5581: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1822.h: 5583: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1822.h: 5585: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1822.h: 5587: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1822.h: 5589: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1822.h: 5591: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1822.h: 5593: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1822.h: 5595: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1822.h: 5597: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1822.h: 5599: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1822.h: 5601: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1822.h: 5603: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1822.h: 5605: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1822.h: 5607: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1822.h: 5609: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1822.h: 5611: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1822.h: 5613: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1822.h: 5615: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1822.h: 5617: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1822.h: 5619: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1822.h: 5621: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1822.h: 5623: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1822.h: 5625: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1822.h: 5627: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1822.h: 5629: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1822.h: 5631: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1822.h: 5633: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1822.h: 5635: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1822.h: 5637: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1822.h: 5639: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1822.h: 5641: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1822.h: 5643: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1822.h: 5645: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1822.h: 5647: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1822.h: 5649: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1822.h: 5651: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1822.h: 5653: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1822.h: 5655: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1822.h: 5657: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1822.h: 5659: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1822.h: 5661: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1822.h: 5663: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1822.h: 5665: extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5667: extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5669: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1822.h: 5671: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1822.h: 5673: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1822.h: 5675: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1822.h: 5677: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1822.h: 5679: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1822.h: 5681: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdio.h: 8: typedef int ptrdiff_t;
+[; ;stdio.h: 9: typedef unsigned size_t;
+[; ;stdio.h: 10: typedef unsigned short wchar_t;
+[; ;stdarg.h: 7: typedef void * va_list[1];
+[; ;stdarg.h: 10: extern void * __va_start(void);
+[; ;stdarg.h: 13: extern void * __va_arg(void *, ...);
+[; ;stdio.h: 23: extern int errno;
+[; ;stdio.h: 54: struct __prbuf
+[; ;stdio.h: 55: {
+[; ;stdio.h: 56: char * ptr;
+[; ;stdio.h: 57: void (* func)(char);
+[; ;stdio.h: 58: };
+[; ;conio.h: 17: extern int errno;
+[; ;conio.h: 20: extern void init_uart(void);
+[; ;conio.h: 22: extern char getch(void);
+[; ;conio.h: 23: extern char getche(void);
+[; ;conio.h: 24: extern void putch(char);
+[; ;conio.h: 25: extern void ungetch(char);
+[; ;conio.h: 27: extern __bit kbhit(void);
+[; ;conio.h: 31: extern char * cgets(char *);
+[; ;conio.h: 32: extern void cputs(const char *);
+[; ;stdio.h: 99: extern int cprintf(char *, ...);
+[; ;stdio.h: 104: extern int _doprnt(struct __prbuf *, const register char *, register va_list);
+[; ;stdio.h: 194: extern char * gets(char *);
+[; ;stdio.h: 195: extern int puts(const char *);
+[; ;stdio.h: 196: extern int scanf(const char *, ...);
+[; ;stdio.h: 197: extern int sscanf(const char *, const char *, ...);
+[; ;stdio.h: 198: extern int vprintf(const char *, va_list);
+[; ;stdio.h: 199: extern int vsprintf(char *, const char *, va_list) __attribute__((unsupported("vsprintf() is not supported by this compiler")));
+[; ;stdio.h: 200: extern int vscanf(const char *, va_list ap);
+[; ;stdio.h: 201: extern int vsscanf(const char *, const char *, va_list);
+[; ;stdio.h: 205: extern int sprintf(char *, const char *, ...);
+[; ;stdio.h: 206: extern int printf(const char *, ...);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;system.h: 31: void ConfigureOscillator(void);
+[; ;user.h: 13: void InitApp(void);
+[; ;user.h: 14: bool msg_empty(void);
+[; ;user.h: 15: void msg_write(const char *msg);
+[; ;user.h: 16: void msg_writebyte(const char msg);
+[; ;user.h: 17: void msg_sendnext(void);
+[; ;user.h: 18: void tohex(char val[3], char i);
+[; ;user.h: 19: void msg_recvnext(void);
+[; ;user.h: 20: bool msg_recvready(void);
+[; ;user.h: 21: char msg_recv(void);
+[; ;user.h: 22: void putch(char);
+[; ;user.h: 24: void int_disable(void);
+[; ;user.h: 25: void int_enable(void);
+[; ;onewire.h: 11: bool OW_reset(void);
+[; ;onewire.h: 12: void OW_write_bit(bool val);
+[; ;onewire.h: 13: bool OW_read_bit();
+[; ;onewire.h: 14: void OW_write_byte(unsigned char byte);
+[; ;onewire.h: 15: unsigned char OW_read_byte(void);
+[; ;onewire.h: 17: void OW_search_init();
+[; ;onewire.h: 18: bool OW_search(void);
+[; ;onewire.h: 19: void OW_start(void);
+[; ;onewire.h: 21: void OW_identify();
+[; ;onewire.h: 22: bool OW_parasite(void);
+[; ;onewire.h: 23: void OW_read_block(uint8_t code, uint8_t * data, uint8_t len);
+[; ;onewire.h: 24: void OW_convert();
+[; ;onewire.h: 27: inline void drive_OW_low(void);
+[; ;onewire.h: 28: inline void drive_OW_high(void);
+[; ;onewire.h: 29: inline void float_OW(void);
+[; ;onewire.h: 30: inline bool read_OW(void);
+[; ;onewire.h: 32: extern unsigned char romid[8];
+"27 main.c
+[v _outbuff `uc ~T0 @X0 -> 60 `i e ]
+[; ;main.c: 27: char outbuff[60];
+"28
+[v _outp `*uc ~T0 @X0 1 e ]
+[i _outp
+-> -> 0 `i `*uc
+]
+[; ;main.c: 28: char * outp = 0;
+"29
+[v _outlen `uc ~T0 @X0 1 e ]
+[i _outlen
+-> -> 0 `i `uc
+]
+[; ;main.c: 29: uint8_t outlen = 0;
+"31
+[v _inbuff `uc ~T0 @X0 -> 10 `i e ]
+[; ;main.c: 31: char inbuff[10];
+"32
+[v _inlen `uc ~T0 @X0 1 e ]
+[i _inlen
+-> -> 0 `i `uc
+]
+[; ;main.c: 32: uint8_t inlen = 0;
+"38
+[v _prompt `uc ~T0 @X0 -> 9 `i e ]
+[; ;main.c: 38: char prompt[9];
+"40
+[v _banner `*Cuc ~T0 @X0 1 e ]
+[i _banner
+:s 1C
+]
+[; ;main.c: 40: const char * banner = "\r\n\n\nPIC 1-Wire Bridge system.  Press 'H' for help.\r\n";
+"43
+[v _main `(v ~T0 @X0 1 ef ]
+{
+[; ;main.c: 42: void main(void)
+[; ;main.c: 43: {
+[e :U _main ]
+[f ]
+[; ;main.c: 44: prompt[0] = 'c';
+"44
+[e = *U + &U _prompt * -> -> -> 0 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 99 `ui `uc ]
+[; ;main.c: 45: prompt[1] = 'm';
+"45
+[e = *U + &U _prompt * -> -> -> 1 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 109 `ui `uc ]
+[; ;main.c: 46: prompt[2] = 'd';
+"46
+[e = *U + &U _prompt * -> -> -> 2 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 100 `ui `uc ]
+[; ;main.c: 47: prompt[3] = ' ';
+"47
+[e = *U + &U _prompt * -> -> -> 3 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 32 `ui `uc ]
+[; ;main.c: 48: prompt[4] = '?';
+"48
+[e = *U + &U _prompt * -> -> -> 4 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 63 `ui `uc ]
+[; ;main.c: 49: prompt[5] = '?';
+"49
+[e = *U + &U _prompt * -> -> -> 5 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 63 `ui `uc ]
+[; ;main.c: 50: prompt[6] = '>';
+"50
+[e = *U + &U _prompt * -> -> -> 6 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 62 `ui `uc ]
+[; ;main.c: 51: prompt[7] = ' ';
+"51
+[e = *U + &U _prompt * -> -> -> 7 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 32 `ui `uc ]
+[; ;main.c: 52: prompt[8] = 0;
+"52
+[e = *U + &U _prompt * -> -> -> 8 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 0 `i `uc ]
+"54
+[v _usermode `uc ~T0 @X0 1 a ]
+[; ;main.c: 54: bool usermode = 0;
+[e = _usermode -> -> 0 `i `uc ]
+[; ;main.c: 57: ConfigureOscillator();
+"57
+[e ( _ConfigureOscillator ..  ]
+[; ;main.c: 60: InitApp();
+"60
+[e ( _InitApp ..  ]
+[; ;main.c: 62: OW_start();
+"62
+[e ( _OW_start ..  ]
+[; ;main.c: 63: msg_write(banner);
+"63
+[e ( _msg_write (1 _banner ]
+[; ;main.c: 66: while(1)
+"66
+[e :U 527 ]
+[; ;main.c: 67: {
+"67
+{
+[; ;main.c: 68: asm("clrwdt");
+"68
+[; <" clrwdt ;# ">
+[; ;main.c: 70: if (TRISAbits.TRISA5 == 1) {
+"70
+[e $ ! == -> . . _TRISAbits 0 5 `i -> 1 `i 529  ]
+{
+[; ;main.c: 71: prompt[4] = 'i';
+"71
+[e = *U + &U _prompt * -> -> -> 4 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 105 `ui `uc ]
+[; ;main.c: 72: prompt[5] = PORTAbits.RA5 ? '1':'0';
+"72
+[e = *U + &U _prompt * -> -> -> 5 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> ? != -> . . _PORTAbits 0 5 `i -> -> -> 0 `i `Vuc `i : -> 49 `ui -> 48 `ui `uc ]
+"73
+}
+[; ;main.c: 73: } else {
+[e $U 530  ]
+[e :U 529 ]
+{
+[; ;main.c: 74: prompt[4] = 'o';
+"74
+[e = *U + &U _prompt * -> -> -> 4 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> -> 111 `ui `uc ]
+[; ;main.c: 75: prompt[5] = PORTAbits.RA5 ? '1':'0';
+"75
+[e = *U + &U _prompt * -> -> -> 5 `i `ui `ux -> -> # *U &U _prompt `ui `ux -> ? != -> . . _PORTAbits 0 5 `i -> -> -> 0 `i `Vuc `i : -> 49 `ui -> 48 `ui `uc ]
+"76
+}
+[e :U 530 ]
+[; ;main.c: 76: }
+[; ;main.c: 78: if (!msg_empty()) continue;
+"78
+[e $ ! ! != -> ( _msg_empty ..  `i -> -> -> 0 `i `uc `i 531  ]
+[e $U 526  ]
+[e :U 531 ]
+[; ;main.c: 80: if (!msg_recvready()) continue;
+"80
+[e $ ! ! != -> ( _msg_recvready ..  `i -> -> -> 0 `i `uc `i 532  ]
+[e $U 526  ]
+[e :U 532 ]
+"82
+[v _cmd `uc ~T0 @X0 1 a ]
+[; ;main.c: 82: char cmd = msg_recv();
+[e = _cmd ( _msg_recv ..  ]
+[; ;main.c: 84: if (cmd == '\r' || cmd == '\n') {
+"84
+[e $ ! || == -> _cmd `ui -> 13 `ui == -> _cmd `ui -> 10 `ui 533  ]
+{
+[; ;main.c: 85: if (usermode) msg_write("\r\n");
+"85
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 534  ]
+[e ( _msg_write (1 :s 2C ]
+[e :U 534 ]
+"86
+}
+[; ;main.c: 86: }else
+[e $U 535  ]
+[e :U 533 ]
+[; ;main.c: 87: if (cmd == 'h' || cmd == 'H') {
+"87
+[e $ ! || == -> _cmd `ui -> 104 `ui == -> _cmd `ui -> 72 `ui 536  ]
+{
+[; ;main.c: 88: msg_write(banner);
+"88
+[e ( _msg_write (1 _banner ]
+[; ;main.c: 89: msg_write("\nHelp:\r\n");
+"89
+[e ( _msg_write (1 :s 3C ]
+[; ;main.c: 90: while (!msg_empty());
+"90
+[e $U 537  ]
+[e :U 538 ]
+[e :U 537 ]
+[e $ ! != -> ( _msg_empty ..  `i -> -> -> 0 `i `uc `i 538  ]
+[e :U 539 ]
+[; ;main.c: 91: msg_write("E - Enumerate the Bus\r\n");
+"91
+[e ( _msg_write (1 :s 4C ]
+[; ;main.c: 92: msg_write("R - Reset Bus\r\n");
+"92
+[e ( _msg_write (1 :s 5C ]
+[; ;main.c: 93: while (!msg_empty());
+"93
+[e $U 540  ]
+[e :U 541 ]
+[e :U 540 ]
+[e $ ! != -> ( _msg_empty ..  `i -> -> -> 0 `i `uc `i 541  ]
+[e :U 542 ]
+[; ;main.c: 94: msg_write("0,1,3 - bus to Low, High, Tristate\r\n");
+"94
+[e ( _msg_write (1 :s 6C ]
+[; ;main.c: 95: msg_write("I - Read (one) Device ID\r\n");
+"95
+[e ( _msg_write (1 :s 7C ]
+[; ;main.c: 96: while (!msg_empty());
+"96
+[e $U 543  ]
+[e :U 544 ]
+[e :U 543 ]
+[e $ ! != -> ( _msg_empty ..  `i -> -> -> 0 `i `uc `i 544  ]
+[e :U 545 ]
+[; ;main.c: 97: msg_write("P - Any device parasitic powered?\r\n");
+"97
+[e ( _msg_write (1 :s 8C ]
+[; ;main.c: 98: msg_write("S - Read scratchpad memory\r\n");
+"98
+[e ( _msg_write (1 :s 9C ]
+[; ;main.c: 99: while (!msg_empty());
+"99
+[e $U 546  ]
+[e :U 547 ]
+[e :U 546 ]
+[e $ ! != -> ( _msg_empty ..  `i -> -> -> 0 `i `uc `i 547  ]
+[e :U 548 ]
+[; ;main.c: 100: msg_write("T - read temperature of all devices\r\n");
+"100
+[e ( _msg_write (1 :s 10C ]
+[; ;main.c: 101: usermode = 1;
+"101
+[e = _usermode -> -> 1 `i `uc ]
+"102
+}
+[; ;main.c: 102: } else
+[e $U 549  ]
+[e :U 536 ]
+[; ;main.c: 103: if (cmd == 'r' || cmd == 'R') {
+"103
+[e $ ! || == -> _cmd `ui -> 114 `ui == -> _cmd `ui -> 82 `ui 550  ]
+{
+[; ;main.c: 104: int_disable();
+"104
+[e ( _int_disable ..  ]
+"105
+[v _present `uc ~T0 @X0 1 a ]
+[; ;main.c: 105: bool present = OW_reset();
+[e = _present ( _OW_reset ..  ]
+[; ;main.c: 106: int_enable();
+"106
+[e ( _int_enable ..  ]
+[; ;main.c: 107: if (usermode) msg_write("\r");
+"107
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 551  ]
+[e ( _msg_write (1 :s 11C ]
+[e :U 551 ]
+[; ;main.c: 108: if (present)
+"108
+[e $ ! != -> _present `i -> -> -> 0 `i `uc `i 552  ]
+[; ;main.c: 109: msg_write("RESET Device detected.\r\n");
+"109
+[e ( _msg_write (1 :s 12C ]
+[e $U 553  ]
+"110
+[e :U 552 ]
+[; ;main.c: 110: else
+[; ;main.c: 111: msg_write("RESET No Devices detected.\r\n");
+"111
+[e ( _msg_write (1 :s 13C ]
+[e :U 553 ]
+"112
+}
+[; ;main.c: 112: } else
+[e $U 554  ]
+[e :U 550 ]
+[; ;main.c: 113: if (cmd == 'e' || cmd == 'E')
+"113
+[e $ ! || == -> _cmd `ui -> 101 `ui == -> _cmd `ui -> 69 `ui 555  ]
+[; ;main.c: 114: {
+"114
+{
+"115
+[v _count `uc ~T0 @X0 1 a ]
+[; ;main.c: 115: char count = 0;
+[e = _count -> -> 0 `i `uc ]
+[; ;main.c: 116: if (usermode) msg_write("\r");
+"116
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 556  ]
+[e ( _msg_write (1 :s 14C ]
+[e :U 556 ]
+[; ;main.c: 117: OW_search_init();
+"117
+[e ( _OW_search_init ..  ]
+[; ;main.c: 118: while (OW_search())
+"118
+[e $U 557  ]
+[e :U 558 ]
+[; ;main.c: 119: {
+"119
+{
+"120
+[v _val `uc ~T0 @X0 -> 3 `i a ]
+[; ;main.c: 120: char val[3];
+[; ;main.c: 121: if (usermode) msg_write("ENUM ");
+"121
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 560  ]
+[e ( _msg_write (1 :s 15C ]
+[e :U 560 ]
+[; ;main.c: 122: for (char j=0; j<8; j++) {
+"122
+{
+[v _j `uc ~T0 @X0 1 a ]
+[e = _j -> -> 0 `i `uc ]
+[e $ < -> _j `i -> 8 `i 561  ]
+[e $U 562  ]
+[e :U 561 ]
+{
+[; ;main.c: 123: tohex(val, romid[j]);
+"123
+[e ( _tohex (2 , &U _val *U + &U _romid * -> _j `ux -> -> # *U &U _romid `ui `ux ]
+[; ;main.c: 124: msg_write(val);
+"124
+[e ( _msg_write (1 -> &U _val `*Cuc ]
+"125
+}
+"122
+[e ++ _j -> -> 1 `i `uc ]
+[e $ < -> _j `i -> 8 `i 561  ]
+[e :U 562 ]
+"125
+}
+[; ;main.c: 125: }
+[; ;main.c: 126: if (usermode) msg_write("\r\n"); else msg_write("\n");
+"126
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 564  ]
+[e ( _msg_write (1 :s 16C ]
+[e $U 565  ]
+[e :U 564 ]
+[e ( _msg_write (1 :s 17C ]
+[e :U 565 ]
+[; ;main.c: 127: count++;
+"127
+[e ++ _count -> -> 1 `i `uc ]
+"128
+}
+[e :U 557 ]
+"118
+[e $ != -> ( _OW_search ..  `i -> -> -> 0 `i `uc `i 558  ]
+[e :U 559 ]
+[; ;main.c: 128: }
+[; ;main.c: 129: if (usermode) {
+"129
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 566  ]
+{
+[; ;main.c: 130: if (count==0) msg_write("ERROR No devices found\r\n");
+"130
+[e $ ! == -> _count `i -> 0 `i 567  ]
+[e ( _msg_write (1 :s 18C ]
+[e :U 567 ]
+"131
+}
+[; ;main.c: 131: } else {
+[e $U 568  ]
+[e :U 566 ]
+{
+[; ;main.c: 132: msg_write("END\n");
+"132
+[e ( _msg_write (1 :s 19C ]
+"133
+}
+[e :U 568 ]
+"134
+}
+[; ;main.c: 133: }
+[; ;main.c: 134: }else
+[e $U 569  ]
+[e :U 555 ]
+[; ;main.c: 135: if (cmd == 'i' || cmd == 'I') {
+"135
+[e $ ! || == -> _cmd `ui -> 105 `ui == -> _cmd `ui -> 73 `ui 570  ]
+{
+[; ;main.c: 136: OW_identify();
+"136
+[e ( _OW_identify ..  ]
+"137
+[v _val `uc ~T0 @X0 -> 3 `i a ]
+[; ;main.c: 137: char val[3];
+[; ;main.c: 138: if (usermode) msg_write("\rID ");
+"138
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 571  ]
+[e ( _msg_write (1 :s 20C ]
+[e :U 571 ]
+[; ;main.c: 139: for (char j=0; j<8; j++) {
+"139
+{
+[v _j `uc ~T0 @X0 1 a ]
+[e = _j -> -> 0 `i `uc ]
+[e $ < -> _j `i -> 8 `i 572  ]
+[e $U 573  ]
+[e :U 572 ]
+{
+[; ;main.c: 140: tohex(val, romid[j]);
+"140
+[e ( _tohex (2 , &U _val *U + &U _romid * -> _j `ux -> -> # *U &U _romid `ui `ux ]
+[; ;main.c: 141: msg_write(val);
+"141
+[e ( _msg_write (1 -> &U _val `*Cuc ]
+"142
+}
+"139
+[e ++ _j -> -> 1 `i `uc ]
+[e $ < -> _j `i -> 8 `i 572  ]
+[e :U 573 ]
+"142
+}
+[; ;main.c: 142: }
+[; ;main.c: 143: if (usermode) msg_write("\r\n"); else msg_write("\n");
+"143
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 575  ]
+[e ( _msg_write (1 :s 21C ]
+[e $U 576  ]
+[e :U 575 ]
+[e ( _msg_write (1 :s 22C ]
+[e :U 576 ]
+"144
+}
+[; ;main.c: 144: }else
+[e $U 577  ]
+[e :U 570 ]
+[; ;main.c: 145: if (cmd == 'p' || cmd == 'P') {
+"145
+[e $ ! || == -> _cmd `ui -> 112 `ui == -> _cmd `ui -> 80 `ui 578  ]
+{
+[; ;main.c: 146: if (usermode) msg_write("\r");
+"146
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 579  ]
+[e ( _msg_write (1 :s 23C ]
+[e :U 579 ]
+"147
+[v _para `uc ~T0 @X0 1 a ]
+[; ;main.c: 147: bool para = OW_parasite();
+[e = _para ( _OW_parasite ..  ]
+[; ;main.c: 148: if (usermode) {
+"148
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 580  ]
+{
+[; ;main.c: 149: if (para)
+"149
+[e $ ! != -> _para `i -> -> -> 0 `i `uc `i 581  ]
+[; ;main.c: 150: msg_write("PARA A Device is parasite powered\r\n");
+"150
+[e ( _msg_write (1 :s 24C ]
+[e $U 582  ]
+"151
+[e :U 581 ]
+[; ;main.c: 151: else
+[; ;main.c: 152: msg_write("PARA No Device is parasite powered.\r\n");
+"152
+[e ( _msg_write (1 :s 25C ]
+[e :U 582 ]
+"153
+}
+[; ;main.c: 153: } else {
+[e $U 583  ]
+[e :U 580 ]
+{
+[; ;main.c: 154: if (para) msg_write("PARA\n"); else msg_write("DIRECT\n");
+"154
+[e $ ! != -> _para `i -> -> -> 0 `i `uc `i 584  ]
+[e ( _msg_write (1 :s 26C ]
+[e $U 585  ]
+[e :U 584 ]
+[e ( _msg_write (1 :s 27C ]
+[e :U 585 ]
+"155
+}
+[e :U 583 ]
+"156
+}
+[; ;main.c: 155: }
+[; ;main.c: 156: }else
+[e $U 586  ]
+[e :U 578 ]
+[; ;main.c: 157: if (cmd == 's' || cmd =='S') {
+"157
+[e $ ! || == -> _cmd `ui -> 115 `ui == -> _cmd `ui -> 83 `ui 587  ]
+{
+"158
+[v _scratch `uc ~T0 @X0 -> 9 `i a ]
+[; ;main.c: 158: uint8_t scratch[9];
+[; ;main.c: 159: romid[0] = 0;
+"159
+[e = *U + &U _romid * -> -> -> 0 `i `ui `ux -> -> # *U &U _romid `ui `ux -> -> 0 `i `uc ]
+[; ;main.c: 160: OW_read_block(0xBE, scratch, 9);
+"160
+[e ( _OW_read_block (3 , , -> -> 190 `i `uc &U _scratch -> -> 9 `i `uc ]
+[; ;main.c: 161: if (usermode) msg_write("\rSCRATCH");
+"161
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 588  ]
+[e ( _msg_write (1 :s 28C ]
+[e :U 588 ]
+[; ;main.c: 162: for (char j=0; j<9; j++) {
+"162
+{
+[v _j `uc ~T0 @X0 1 a ]
+[e = _j -> -> 0 `i `uc ]
+[e $ < -> _j `i -> 9 `i 589  ]
+[e $U 590  ]
+[e :U 589 ]
+{
+"163
+[v _val `uc ~T0 @X0 -> 3 `i a ]
+[; ;main.c: 163: char val[3];
+[; ;main.c: 164: tohex(val, scratch[j]);
+"164
+[e ( _tohex (2 , &U _val *U + &U _scratch * -> _j `ux -> -> # *U &U _scratch `ui `ux ]
+[; ;main.c: 165: msg_write(" ");
+"165
+[e ( _msg_write (1 :s 29C ]
+[; ;main.c: 166: msg_write(val);
+"166
+[e ( _msg_write (1 -> &U _val `*Cuc ]
+"167
+}
+"162
+[e ++ _j -> -> 1 `i `uc ]
+[e $ < -> _j `i -> 9 `i 589  ]
+[e :U 590 ]
+"167
+}
+[; ;main.c: 167: }
+[; ;main.c: 168: if (usermode) msg_write("\r\n"); else msg_write("\n");
+"168
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 592  ]
+[e ( _msg_write (1 :s 30C ]
+[e $U 593  ]
+[e :U 592 ]
+[e ( _msg_write (1 :s 31C ]
+[e :U 593 ]
+"169
+}
+[; ;main.c: 169: }else
+[e $U 594  ]
+[e :U 587 ]
+[; ;main.c: 170: if (cmd == 't' || cmd == 'T') {
+"170
+[e $ ! || == -> _cmd `ui -> 116 `ui == -> _cmd `ui -> 84 `ui 595  ]
+{
+"171
+[v _val `uc ~T0 @X0 -> 3 `i a ]
+"172
+[v _scratch `uc ~T0 @X0 -> 9 `i a ]
+[; ;main.c: 171: char val[3];
+[; ;main.c: 172: uint8_t scratch[9];
+[; ;main.c: 178: OW_search_init();
+"178
+[e ( _OW_search_init ..  ]
+[; ;main.c: 179: while (OW_search())
+"179
+[e $U 596  ]
+[e :U 597 ]
+[; ;main.c: 180: {
+"180
+{
+[; ;main.c: 182: asm("clrwdt");
+"182
+[; <" clrwdt ;# ">
+[; ;main.c: 184: OW_convert();
+"184
+[e ( _OW_convert ..  ]
+[; ;main.c: 185: asm("clrwdt");
+"185
+[; <" clrwdt ;# ">
+[; ;main.c: 188: for (char j=0; j<9; j++) scratch[j]=0;
+"188
+{
+[v _j `uc ~T0 @X0 1 a ]
+[e = _j -> -> 0 `i `uc ]
+[e $ < -> _j `i -> 9 `i 599  ]
+[e $U 600  ]
+[e :U 599 ]
+[e = *U + &U _scratch * -> _j `ux -> -> # *U &U _scratch `ui `ux -> -> 0 `i `uc ]
+[e ++ _j -> -> 1 `i `uc ]
+[e $ < -> _j `i -> 9 `i 599  ]
+[e :U 600 ]
+}
+[; ;main.c: 191: OW_read_block(0xBE, scratch, 9);
+"191
+[e ( _OW_read_block (3 , , -> -> 190 `i `uc &U _scratch -> -> 9 `i `uc ]
+[; ;main.c: 194: if (usermode) msg_write("\r");
+"194
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 602  ]
+[e ( _msg_write (1 :s 32C ]
+[e :U 602 ]
+[; ;main.c: 195: msg_write("TEMP ");
+"195
+[e ( _msg_write (1 :s 33C ]
+[; ;main.c: 196: for (char j=0;j<8;j++) {
+"196
+{
+[v _j `uc ~T0 @X0 1 a ]
+[e = _j -> -> 0 `i `uc ]
+[e $ < -> _j `i -> 8 `i 603  ]
+[e $U 604  ]
+[e :U 603 ]
+{
+[; ;main.c: 197: tohex(val, romid[j]);
+"197
+[e ( _tohex (2 , &U _val *U + &U _romid * -> _j `ux -> -> # *U &U _romid `ui `ux ]
+[; ;main.c: 198: msg_write(val);
+"198
+[e ( _msg_write (1 -> &U _val `*Cuc ]
+"199
+}
+"196
+[e ++ _j -> -> 1 `i `uc ]
+[e $ < -> _j `i -> 8 `i 603  ]
+[e :U 604 ]
+"199
+}
+[; ;main.c: 199: }
+[; ;main.c: 200: msg_write(" ");
+"200
+[e ( _msg_write (1 :s 34C ]
+[; ;main.c: 201: tohex(val, scratch[1]);
+"201
+[e ( _tohex (2 , &U _val *U + &U _scratch * -> -> -> 1 `i `ui `ux -> -> # *U &U _scratch `ui `ux ]
+[; ;main.c: 202: msg_write(val);
+"202
+[e ( _msg_write (1 -> &U _val `*Cuc ]
+[; ;main.c: 203: tohex(val, scratch[0]);
+"203
+[e ( _tohex (2 , &U _val *U + &U _scratch * -> -> -> 0 `i `ui `ux -> -> # *U &U _scratch `ui `ux ]
+[; ;main.c: 204: msg_write(val);
+"204
+[e ( _msg_write (1 -> &U _val `*Cuc ]
+[; ;main.c: 205: if (usermode) msg_write("\r\n"); else msg_write("\n");
+"205
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 606  ]
+[e ( _msg_write (1 :s 35C ]
+[e $U 607  ]
+[e :U 606 ]
+[e ( _msg_write (1 :s 36C ]
+[e :U 607 ]
+"206
+}
+[e :U 596 ]
+"179
+[e $ != -> ( _OW_search ..  `i -> -> -> 0 `i `uc `i 597  ]
+[e :U 598 ]
+[; ;main.c: 206: }
+[; ;main.c: 208: if (!usermode) msg_write("END\n");
+"208
+[e $ ! ! != -> _usermode `i -> -> -> 0 `i `uc `i 608  ]
+[e ( _msg_write (1 :s 37C ]
+[e :U 608 ]
+"210
+}
+[; ;main.c: 210: }else
+[e $U 609  ]
+[e :U 595 ]
+[; ;main.c: 211: if (cmd == '0')
+"211
+[e $ ! == -> _cmd `ui -> 48 `ui 610  ]
+[; ;main.c: 212: {
+"212
+{
+[; ;main.c: 213: drive_OW_low();
+"213
+[e ( _drive_OW_low ..  ]
+[; ;main.c: 214: if (usermode)
+"214
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 611  ]
+[; ;main.c: 215: msg_write("\rBUS 1-Wire set low\r\n");
+"215
+[e ( _msg_write (1 :s 38C ]
+[e $U 612  ]
+"216
+[e :U 611 ]
+[; ;main.c: 216: else
+[; ;main.c: 217: msg_write("LOW\n");
+"217
+[e ( _msg_write (1 :s 39C ]
+[e :U 612 ]
+"218
+}
+[; ;main.c: 218: }else
+[e $U 613  ]
+[e :U 610 ]
+[; ;main.c: 219: if (cmd == '1')
+"219
+[e $ ! == -> _cmd `ui -> 49 `ui 614  ]
+[; ;main.c: 220: {
+"220
+{
+[; ;main.c: 221: drive_OW_high();
+"221
+[e ( _drive_OW_high ..  ]
+[; ;main.c: 222: if (usermode)
+"222
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 615  ]
+[; ;main.c: 223: msg_write("\rBUS 1-wire set high\r\n");
+"223
+[e ( _msg_write (1 :s 40C ]
+[e $U 616  ]
+"224
+[e :U 615 ]
+[; ;main.c: 224: else
+[; ;main.c: 225: msg_write("HIGH\n");
+"225
+[e ( _msg_write (1 :s 41C ]
+[e :U 616 ]
+"226
+}
+[; ;main.c: 226: }else
+[e $U 617  ]
+[e :U 614 ]
+[; ;main.c: 227: if (cmd == '3')
+"227
+[e $ ! == -> _cmd `ui -> 51 `ui 618  ]
+[; ;main.c: 228: {
+"228
+{
+[; ;main.c: 229: float_OW();
+"229
+[e ( _float_OW ..  ]
+[; ;main.c: 230: if (usermode)
+"230
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 619  ]
+[; ;main.c: 231: msg_write("\rBUS 1-wire set to tri-state\r\n");
+"231
+[e ( _msg_write (1 :s 42C ]
+[e $U 620  ]
+"232
+[e :U 619 ]
+[; ;main.c: 232: else
+[; ;main.c: 233: msg_write("TRISTATE\n");
+"233
+[e ( _msg_write (1 :s 43C ]
+[e :U 620 ]
+"234
+}
+[; ;main.c: 234: }else
+[e $U 621  ]
+[e :U 618 ]
+[; ;main.c: 235: if (cmd == '!')
+"235
+[e $ ! == -> _cmd `ui -> 33 `ui 622  ]
+[; ;main.c: 236: {
+"236
+{
+[; ;main.c: 238: msg_write("Play dead.\r\n");
+"238
+[e ( _msg_write (1 :s 44C ]
+[; ;main.c: 239: while (1) { _nop(); }
+"239
+[e :U 624 ]
+{
+[e ( __nop ..  ]
+}
+[e :U 623 ]
+[e $U 624  ]
+[e :U 625 ]
+"240
+}
+[; ;main.c: 240: }else
+[e $U 626  ]
+[e :U 622 ]
+[; ;main.c: 241: if (cmd == '?')
+"241
+[e $ ! == -> _cmd `ui -> 63 `ui 627  ]
+[; ;main.c: 242: {
+"242
+{
+"243
+[v _line `uc ~T0 @X0 1 a ]
+[; ;main.c: 243: bool line = read_OW();
+[e = _line ( _read_OW ..  ]
+[; ;main.c: 244: if (line) {
+"244
+[e $ ! != -> _line `i -> -> -> 0 `i `uc `i 628  ]
+{
+[; ;main.c: 245: if (usermode) msg_write("\rBUS HIGH\r\n");
+"245
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 629  ]
+[e ( _msg_write (1 :s 45C ]
+[e $U 630  ]
+"246
+[e :U 629 ]
+[; ;main.c: 246: else
+[; ;main.c: 247: msg_write("HIGH\n");
+"247
+[e ( _msg_write (1 :s 46C ]
+[e :U 630 ]
+"248
+}
+[; ;main.c: 248: } else {
+[e $U 631  ]
+[e :U 628 ]
+{
+[; ;main.c: 249: if (usermode) msg_write("\rBUS LOW\r\n");
+"249
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 632  ]
+[e ( _msg_write (1 :s 47C ]
+[e $U 633  ]
+"250
+[e :U 632 ]
+[; ;main.c: 250: else msg_write("LOW\n");
+[e ( _msg_write (1 :s 48C ]
+[e :U 633 ]
+"251
+}
+[e :U 631 ]
+"252
+}
+[; ;main.c: 251: }
+[; ;main.c: 252: }else
+[e $U 634  ]
+[e :U 627 ]
+[; ;main.c: 253: {
+"253
+{
+[; ;main.c: 254: if (usermode) {
+"254
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 635  ]
+{
+[; ;main.c: 255: msg_write("ERROR Press H for Help\n");
+"255
+[e ( _msg_write (1 :s 49C ]
+"256
+}
+[; ;main.c: 256: } else {
+[e $U 636  ]
+[e :U 635 ]
+{
+[; ;main.c: 257: msg_write("\rERROR Unknown command '");
+"257
+[e ( _msg_write (1 :s 50C ]
+[; ;main.c: 258: msg_writebyte(cmd);
+"258
+[e ( _msg_writebyte (1 _cmd ]
+[; ;main.c: 259: msg_write("' Press 'H' for help.\r\n");
+"259
+[e ( _msg_write (1 :s 51C ]
+"260
+}
+[e :U 636 ]
+"261
+}
+[e :U 634 ]
+[e :U 626 ]
+[e :U 621 ]
+[e :U 617 ]
+[e :U 613 ]
+[e :U 609 ]
+[e :U 594 ]
+[e :U 586 ]
+[e :U 577 ]
+[e :U 569 ]
+[e :U 554 ]
+[e :U 549 ]
+[e :U 535 ]
+[; ;main.c: 260: }
+[; ;main.c: 261: }
+[; ;main.c: 263: if (usermode) msg_write(prompt);
+"263
+[e $ ! != -> _usermode `i -> -> -> 0 `i `uc `i 637  ]
+[e ( _msg_write (1 -> &U _prompt `*Cuc ]
+[e :U 637 ]
+"264
+}
+[e :U 526 ]
+"66
+[e $U 527  ]
+[e :U 528 ]
+[; ;main.c: 264: }
+[; ;main.c: 265: }
+"265
+[e :UE 525 ]
+}
+"270
+[v _tohex `(v ~T0 @X0 1 ef2`*uc`uc ]
+{
+[; ;main.c: 269: void tohex(char val[], char i)
+[; ;main.c: 270: {
+[e :U _tohex ]
+[v _val `*uc ~T0 @X0 1 r1 ]
+[v _i `uc ~T0 @X0 1 r2 ]
+[f ]
+"271
+[v _bt `uc ~T0 @X0 1 a ]
+[; ;main.c: 271: char bt = i >> 4;
+[e = _bt -> >> -> _i `i -> 4 `i `uc ]
+[; ;main.c: 272: if (bt > 9)
+"272
+[e $ ! > -> _bt `i -> 9 `i 639  ]
+[; ;main.c: 273: val[0] = 'A' + (bt - 10);
+"273
+[e = *U + _val * -> -> 0 `i `x -> -> # *U _val `i `x -> + -> 65 `ui -> - -> _bt `i -> 10 `i `ui `uc ]
+[e $U 640  ]
+"274
+[e :U 639 ]
+[; ;main.c: 274: else
+[; ;main.c: 275: val[0] = '0' + bt;
+"275
+[e = *U + _val * -> -> 0 `i `x -> -> # *U _val `i `x -> + -> 48 `ui -> _bt `ui `uc ]
+[e :U 640 ]
+[; ;main.c: 276: bt = i & 0x0F;
+"276
+[e = _bt -> & -> _i `i -> 15 `i `uc ]
+[; ;main.c: 277: if (bt > 9)
+"277
+[e $ ! > -> _bt `i -> 9 `i 641  ]
+[; ;main.c: 278: val[1] = 'A' + (bt - 10);
+"278
+[e = *U + _val * -> -> 1 `i `x -> -> # *U _val `i `x -> + -> 65 `ui -> - -> _bt `i -> 10 `i `ui `uc ]
+[e $U 642  ]
+"279
+[e :U 641 ]
+[; ;main.c: 279: else
+[; ;main.c: 280: val[1] = '0' + bt;
+"280
+[e = *U + _val * -> -> 1 `i `x -> -> # *U _val `i `x -> + -> 48 `ui -> _bt `ui `uc ]
+[e :U 642 ]
+[; ;main.c: 281: val[2] = 0;
+"281
+[e = *U + _val * -> -> 2 `i `x -> -> # *U _val `i `x -> -> 0 `i `uc ]
+[; ;main.c: 282: }
+"282
+[e :UE 638 ]
+}
+"287
+[v _msg_empty `(uc ~T0 @X0 1 ef ]
+{
+[; ;main.c: 286: bool msg_empty(void)
+[; ;main.c: 287: {
+[e :U _msg_empty ]
+[f ]
+[; ;main.c: 288: if (outp == 0) return 1;
+"288
+[e $ ! == _outp -> -> 0 `i `*uc 644  ]
+[e ) -> -> 1 `i `uc ]
+[e $UE 643  ]
+[e :U 644 ]
+[; ;main.c: 289: return 0;
+"289
+[e ) -> -> 0 `i `uc ]
+[e $UE 643  ]
+[; ;main.c: 290: }
+"290
+[e :UE 643 ]
+}
+"294
+[v _msg_write `(v ~T0 @X0 1 ef1`*Cuc ]
+{
+[; ;main.c: 293: void msg_write(const char *msg)
+[; ;main.c: 294: {
+[e :U _msg_write ]
+[v _msg `*Cuc ~T0 @X0 1 r1 ]
+[f ]
+"295
+[v _p `*uc ~T0 @X0 1 a ]
+[; ;main.c: 295: char * p = outbuff + outlen;
+[e = _p + &U _outbuff * -> _outlen `ux -> -> # *U &U _outbuff `ui `ux ]
+[; ;main.c: 296: while (outlen < sizeof(outbuff) && *msg != 0) {
+"296
+[e $U 646  ]
+[e :U 647 ]
+{
+[; ;main.c: 297: *(p++) = *(msg++);
+"297
+[e = *U ++ _p * -> -> 1 `i `x -> -> # *U _p `i `x *U ++ _msg * -> -> 1 `i `x -> -> # *U _msg `i `x ]
+[; ;main.c: 298: outlen++;
+"298
+[e ++ _outlen -> -> 1 `i `uc ]
+"299
+}
+[e :U 646 ]
+"296
+[e $ && < -> _outlen `ui -> # _outbuff `ui != -> *U _msg `i -> 0 `i 647  ]
+[e :U 648 ]
+[; ;main.c: 299: }
+[; ;main.c: 300: *p = 0;
+"300
+[e = *U _p -> -> 0 `i `uc ]
+[; ;main.c: 301: if (outp == 0) {
+"301
+[e $ ! == _outp -> -> 0 `i `*uc 649  ]
+{
+[; ;main.c: 302: outp = outbuff;
+"302
+[e = _outp &U _outbuff ]
+[; ;main.c: 303: PIE1bits.TXIE = 1;
+"303
+[e = . . _PIE1bits 0 4 -> -> 1 `i `uc ]
+"304
+}
+[e :U 649 ]
+[; ;main.c: 304: }
+[; ;main.c: 305: }
+"305
+[e :UE 645 ]
+}
+"308
+[v _msg_writebyte `(v ~T0 @X0 1 ef1`Cuc ]
+{
+[; ;main.c: 307: void msg_writebyte(const char msg)
+[; ;main.c: 308: {
+[e :U _msg_writebyte ]
+[v _msg `Cuc ~T0 @X0 1 r1 ]
+[f ]
+[; ;main.c: 309: if (outlen+1 >= (uint8_t)sizeof(outbuff)) return;
+"309
+[e $ ! >= + -> _outlen `i -> 1 `i -> -> -> # _outbuff `ui `uc `i 651  ]
+[e $UE 650  ]
+[e :U 651 ]
+[; ;main.c: 310: outbuff[outlen++] = msg;
+"310
+[e = *U + &U _outbuff * -> ++ _outlen -> -> 1 `i `uc `ux -> -> # *U &U _outbuff `ui `ux _msg ]
+[; ;main.c: 311: outbuff[outlen] = 0;
+"311
+[e = *U + &U _outbuff * -> _outlen `ux -> -> # *U &U _outbuff `ui `ux -> -> 0 `i `uc ]
+[; ;main.c: 312: if (outp == 0) {
+"312
+[e $ ! == _outp -> -> 0 `i `*uc 652  ]
+{
+[; ;main.c: 313: outp = outbuff;
+"313
+[e = _outp &U _outbuff ]
+[; ;main.c: 314: PIE1bits.TXIE = 1;
+"314
+[e = . . _PIE1bits 0 4 -> -> 1 `i `uc ]
+"315
+}
+[e :U 652 ]
+[; ;main.c: 315: }
+[; ;main.c: 316: }
+"316
+[e :UE 650 ]
+}
+"319
+[v _putch `(v ~T0 @X0 1 ef1`uc ]
+{
+[; ;main.c: 318: void putch(char data)
+[; ;main.c: 319: {
+[e :U _putch ]
+[v _data `uc ~T0 @X0 1 r1 ]
+[f ]
+[; ;main.c: 320: msg_writebyte(data);
+"320
+[e ( _msg_writebyte (1 _data ]
+[; ;main.c: 321: }
+"321
+[e :UE 653 ]
+}
+"325
+[v _msg_sendnext `(v ~T0 @X0 1 ef ]
+{
+[; ;main.c: 324: void msg_sendnext(void)
+[; ;main.c: 325: {
+[e :U _msg_sendnext ]
+[f ]
+[; ;main.c: 327: if (outp == 0 || *outp == 0) {
+"327
+[e $ ! || == _outp -> -> 0 `i `*uc == -> *U _outp `i -> 0 `i 655  ]
+{
+[; ;main.c: 328: PIE1bits.TXIE = 0;
+"328
+[e = . . _PIE1bits 0 4 -> -> 0 `i `uc ]
+[; ;main.c: 329: outp = 0;
+"329
+[e = _outp -> -> 0 `i `*uc ]
+[; ;main.c: 330: outlen = 0;
+"330
+[e = _outlen -> -> 0 `i `uc ]
+[; ;main.c: 331: return;
+"331
+[e $UE 654  ]
+"332
+}
+[e :U 655 ]
+[; ;main.c: 332: }
+[; ;main.c: 333: TXREG = *outp;
+"333
+[e = _TXREG *U _outp ]
+[; ;main.c: 334: outp++;
+"334
+[e ++ _outp * -> -> 1 `i `x -> -> # *U _outp `i `x ]
+[; ;main.c: 335: }
+"335
+[e :UE 654 ]
+}
+"339
+[v _msg_recvnext `(v ~T0 @X0 1 ef ]
+{
+[; ;main.c: 338: void msg_recvnext(void)
+[; ;main.c: 339: {
+[e :U _msg_recvnext ]
+[f ]
+[; ;main.c: 340: while (PIR1bits.RCIF) {
+"340
+[e $U 657  ]
+[e :U 658 ]
+{
+"341
+[v _err `uc ~T0 @X0 1 a ]
+[; ;main.c: 341: bool err = RCSTAbits.FERR;
+[e = _err . . _RCSTAbits 0 2 ]
+"342
+[v _new `uc ~T0 @X0 1 a ]
+[; ;main.c: 342: char new = RCREG;
+[e = _new _RCREG ]
+[; ;main.c: 345: if (err) continue;
+"345
+[e $ ! != -> _err `i -> -> -> 0 `i `uc `i 660  ]
+[e $U 657  ]
+[e :U 660 ]
+[; ;main.c: 348: if (inlen > sizeof(inbuff)) return;
+"348
+[e $ ! > -> _inlen `ui -> # _inbuff `ui 661  ]
+[e $UE 656  ]
+[e :U 661 ]
+[; ;main.c: 351: inbuff[inlen++] = new;
+"351
+[e = *U + &U _inbuff * -> ++ _inlen -> -> 1 `i `uc `ux -> -> # *U &U _inbuff `ui `ux _new ]
+"352
+}
+[e :U 657 ]
+"340
+[e $ != -> . . _PIR1bits 0 5 `i -> -> -> 0 `i `Vuc `i 658  ]
+[e :U 659 ]
+[; ;main.c: 352: }
+[; ;main.c: 353: }
+"353
+[e :UE 656 ]
+}
+"356
+[v _msg_recvready `(uc ~T0 @X0 1 ef ]
+{
+[; ;main.c: 355: bool msg_recvready(void)
+[; ;main.c: 356: {
+[e :U _msg_recvready ]
+[f ]
+[; ;main.c: 357: if (inlen > 0) return 1;
+"357
+[e $ ! > -> _inlen `i -> 0 `i 663  ]
+[e ) -> -> 1 `i `uc ]
+[e $UE 662  ]
+[e :U 663 ]
+[; ;main.c: 358: return 0;
+"358
+[e ) -> -> 0 `i `uc ]
+[e $UE 662  ]
+[; ;main.c: 359: }
+"359
+[e :UE 662 ]
+}
+"362
+[v _msg_recv `(uc ~T0 @X0 1 ef ]
+{
+[; ;main.c: 361: char msg_recv(void)
+[; ;main.c: 362: {
+[e :U _msg_recv ]
+[f ]
+[; ;main.c: 363: if (inlen == 0) return 0;
+"363
+[e $ ! == -> _inlen `i -> 0 `i 665  ]
+[e ) -> -> 0 `i `uc ]
+[e $UE 664  ]
+[e :U 665 ]
+"366
+[v _in `uc ~T0 @X0 1 a ]
+[; ;main.c: 366: bool in = PIE1bits.RCIE;
+[e = _in . . _PIE1bits 0 5 ]
+[; ;main.c: 367: PIE1bits.RCIE = 0;
+"367
+[e = . . _PIE1bits 0 5 -> -> 0 `i `uc ]
+"369
+[v _new `uc ~T0 @X0 1 a ]
+[; ;main.c: 369: char new = inbuff[0];
+[e = _new *U + &U _inbuff * -> -> -> 0 `i `ui `ux -> -> # *U &U _inbuff `ui `ux ]
+[; ;main.c: 370: inlen--;
+"370
+[e -- _inlen -> -> 1 `i `uc ]
+[; ;main.c: 373: for (char i=0;i<inlen;i++)
+"373
+{
+[v _i `uc ~T0 @X0 1 a ]
+[e = _i -> -> 0 `i `uc ]
+[e $U 669  ]
+"374
+[e :U 666 ]
+[; ;main.c: 374: inbuff[i] = inbuff[i+1];
+[e = *U + &U _inbuff * -> _i `ux -> -> # *U &U _inbuff `ui `ux *U + &U _inbuff * -> -> + -> _i `i -> 1 `i `ui `ux -> -> # *U &U _inbuff `ui `ux ]
+"373
+[e ++ _i -> -> 1 `i `uc ]
+[e :U 669 ]
+[e $ < -> _i `i -> _inlen `i 666  ]
+[e :U 667 ]
+"374
+}
+[; ;main.c: 377: PIE1bits.RCIE = in;
+"377
+[e = . . _PIE1bits 0 5 _in ]
+[; ;main.c: 378: return new;
+"378
+[e ) _new ]
+[e $UE 664  ]
+[; ;main.c: 379: }
+"379
+[e :UE 664 ]
+}
+"383
+[v _int_disable `(v ~T0 @X0 1 ef ]
+{
+[; ;main.c: 382: void int_disable(void)
+[; ;main.c: 383: {
+[e :U _int_disable ]
+[f ]
+[; ;main.c: 384: INTCONbits.GIE = 0;
+"384
+[e = . . _INTCONbits 0 7 -> -> 0 `i `uc ]
+[; ;main.c: 385: }
+"385
+[e :UE 670 ]
+}
+"388
+[v _int_enable `(v ~T0 @X0 1 ef ]
+{
+[; ;main.c: 387: void int_enable(void)
+[; ;main.c: 388: {
+[e :U _int_enable ]
+[f ]
+[; ;main.c: 389: INTCONbits.GIE = 1;
+"389
+[e = . . _INTCONbits 0 7 -> -> 1 `i `uc ]
+[; ;main.c: 390: }
+"390
+[e :UE 671 ]
+}
+[a 28C 13 83 67 82 65 84 67 72 0 ]
+[a 50C 13 69 82 82 79 82 32 85 110 107 110 111 119 110 32 99 111 109 109 97 110 100 32 39 0 ]
+[a 33C 84 69 77 80 32 0 ]
+[a 15C 69 78 85 77 32 0 ]
+[a 20C 13 73 68 32 0 ]
+[a 29C 32 0 ]
+[a 34C 32 0 ]
+[a 11C 13 0 ]
+[a 14C 13 0 ]
+[a 23C 13 0 ]
+[a 32C 13 0 ]
+[a 49C 69 82 82 79 82 32 80 114 101 115 115 32 72 32 102 111 114 32 72 101 108 112 10 0 ]
+[a 39C 76 79 87 10 0 ]
+[a 48C 76 79 87 10 0 ]
+[a 27C 68 73 82 69 67 84 10 0 ]
+[a 41C 72 73 71 72 10 0 ]
+[a 46C 72 73 71 72 10 0 ]
+[a 43C 84 82 73 83 84 65 84 69 10 0 ]
+[a 19C 69 78 68 10 0 ]
+[a 37C 69 78 68 10 0 ]
+[a 26C 80 65 82 65 10 0 ]
+[a 9C 83 32 45 32 82 101 97 100 32 115 99 114 97 116 99 104 112 97 100 32 109 101 109 111 114 121 13 10 0 ]
+[a 38C 13 66 85 83 32 49 45 87 105 114 101 32 115 101 116 32 108 111 119 13 10 0 ]
+[a 5C 82 32 45 32 82 101 115 101 116 32 66 117 115 13 10 0 ]
+[a 4C 69 32 45 32 69 110 117 109 101 114 97 116 101 32 116 104 101 32 66 117 115 13 10 0 ]
+[a 10C 84 32 45 32 114 101 97 100 32 116 101 109 112 101 114 97 116 117 114 101 32 111 102 32 97 108 108 32 100 101 118 105 99 101 115 13 10 0 ]
+[a 40C 13 66 85 83 32 49 45 119 105 114 101 32 115 101 116 32 104 105 103 104 13 10 0 ]
+[a 6C 48 44 49 44 51 32 45 32 98 117 115 32 116 111 32 76 111 119 44 32 72 105 103 104 44 32 84 114 105 115 116 97 116 101 13 10 0 ]
+[a 42C 13 66 85 83 32 49 45 119 105 114 101 32 115 101 116 32 116 111 32 116 114 105 45 115 116 97 116 101 13 10 0 ]
+[a 18C 69 82 82 79 82 32 78 111 32 100 101 118 105 99 101 115 32 102 111 117 110 100 13 10 0 ]
+[a 24C 80 65 82 65 32 65 32 68 101 118 105 99 101 32 105 115 32 112 97 114 97 115 105 116 101 32 112 111 119 101 114 101 100 13 10 0 ]
+[a 47C 13 66 85 83 32 76 79 87 13 10 0 ]
+[a 45C 13 66 85 83 32 72 73 71 72 13 10 0 ]
+[a 7C 73 32 45 32 82 101 97 100 32 40 111 110 101 41 32 68 101 118 105 99 101 32 73 68 13 10 0 ]
+[a 8C 80 32 45 32 65 110 121 32 100 101 118 105 99 101 32 112 97 114 97 115 105 116 105 99 32 112 111 119 101 114 101 100 63 13 10 0 ]
+[a 3C 10 72 101 108 112 58 13 10 0 ]
+[a 51C 39 32 80 114 101 115 115 32 39 72 39 32 102 111 114 32 104 101 108 112 46 13 10 0 ]
+[a 1C 13 10 10 10 80 73 67 32 49 45 87 105 114 101 32 66 114 105 100 103 101 32 115 121 115 116 101 109 46 32 32 80 114 101 115 115 32 39 72 39 32 102 111 114 32 104 101 108 112 46 13 10 0 ]
+[a 13C 82 69 83 69 84 32 78 111 32 68 101 118 105 99 101 115 32 100 101 116 101 99 116 101 100 46 13 10 0 ]
+[a 12C 82 69 83 69 84 32 68 101 118 105 99 101 32 100 101 116 101 99 116 101 100 46 13 10 0 ]
+[a 25C 80 65 82 65 32 78 111 32 68 101 118 105 99 101 32 105 115 32 112 97 114 97 115 105 116 101 32 112 111 119 101 114 101 100 46 13 10 0 ]
+[a 44C 80 108 97 121 32 100 101 97 100 46 13 10 0 ]
+[a 2C 13 10 0 ]
+[a 16C 13 10 0 ]
+[a 21C 13 10 0 ]
+[a 30C 13 10 0 ]
+[a 35C 13 10 0 ]
+[a 17C 10 0 ]
+[a 22C 10 0 ]
+[a 31C 10 0 ]
+[a 36C 10 0 ]

diff --git a/build/XC8_12F1822/production/main.p1.d b/build/XC8_12F1822/production/main.p1.d
new file mode 100644 (file)
index 0000000..4e631f2
--- /dev/null
+++ b/build/XC8_12F1822/production/main.p1.d
@@ -0,0 +1,6 @@
+ build/XC8_12F1822/production/main.d  \
+ build/XC8_12F1822/production/main.p1:  \
+ main.c  \
+onewire.h  \
+user.h  \
+system.h 
\ No newline at end of file

diff --git a/build/XC8_12F1822/production/main.pre b/build/XC8_12F1822/production/main.pre
new file mode 100644 (file)
index 0000000..527c387
--- /dev/null
+++ b/build/XC8_12F1822/production/main.pre
@@ -0,0 +1,6091 @@
+
+# 1 "main.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1822.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+struct {
+unsigned AN0 :1;
+unsigned AN1 :1;
+unsigned AN2 :1;
+unsigned :1;
+unsigned AN3 :1;
+};
+struct {
+unsigned CPS0 :1;
+unsigned CPS1 :1;
+unsigned CPS2 :1;
+unsigned :1;
+unsigned CPS3 :1;
+};
+struct {
+unsigned C1INP :1;
+unsigned C1IN0N :1;
+unsigned C1OUT :1;
+unsigned :1;
+unsigned C1IN1N :1;
+};
+struct {
+unsigned DACOUT :1;
+unsigned SRI :1;
+unsigned SRQ :1;
+unsigned :2;
+unsigned SRNQ :1;
+};
+struct {
+unsigned :1;
+unsigned SCK :1;
+unsigned T0CKI :1;
+unsigned :1;
+unsigned T1OSO :1;
+unsigned T1CKI :1;
+};
+struct {
+unsigned :1;
+unsigned SCL :1;
+unsigned SDA :1;
+unsigned nMCLR :1;
+unsigned CLKR :1;
+unsigned T1OSI :1;
+};
+struct {
+unsigned MDOUT :1;
+unsigned MDMIN :1;
+unsigned MDCIN1 :1;
+unsigned :1;
+unsigned MDCIN2 :1;
+};
+struct {
+unsigned :2;
+unsigned SDI :1;
+unsigned :1;
+unsigned OSC2 :1;
+unsigned OSC1 :1;
+};
+struct {
+unsigned :2;
+unsigned FLT0 :1;
+unsigned :1;
+unsigned CLKOUT :1;
+unsigned CLKIN :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 698
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 759
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 798
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 817
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 842
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 861
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 932
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 1008
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 1027
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 1046
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 1116
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 1175
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 1208
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1257
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1318
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1357
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1439
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1489
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1547
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1604
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1675
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1736
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1761
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1780
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+struct {
+unsigned :1;
+unsigned nDONE :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1868
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1933
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1977
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 2033
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned :4;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 2086
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 2105
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :6;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 2131
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 2206
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2260
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2311
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2381
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2432
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2507
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2573
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2619
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2644
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2663
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2692
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2706
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2725
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2786
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2805
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2824
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2843
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2866
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2880
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2899
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2960
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 3021
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 3072
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 3129
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 3152
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 3166
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 3189
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 3203
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3226
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3240
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3305
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3361
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3438
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3500
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3564
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3629
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3685
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3750
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3806
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3825
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3844
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3925
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3994
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 4079
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 4155
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned STR1C :1;
+unsigned STR1D :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 4198
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4255
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4312
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4369
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4444
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4494
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4546
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4610
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4674
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4705
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4724
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4743
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4762
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4781
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4800
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4819
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4838
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4857
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4876
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4901
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+
+extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 8 "/opt/microchip/xc8/v1.12/include/stdio.h"
+typedef int ptrdiff_t;
+typedef unsigned size_t;
+typedef unsigned short wchar_t;
+
+# 7 "/opt/microchip/xc8/v1.12/include/stdarg.h"
+typedef void * va_list[1];
+
+#pragma intrinsic(__va_start)
+extern void * __va_start(void);
+
+#pragma intrinsic(__va_arg)
+extern void * __va_arg(void *, ...);
+
+# 23 "/opt/microchip/xc8/v1.12/include/stdio.h"
+extern int errno;
+
+# 54
+struct __prbuf
+{
+char * ptr;
+void (* func)(char);
+};
+
+# 17 "/opt/microchip/xc8/v1.12/include/conio.h"
+extern int errno;
+
+
+extern void init_uart(void);
+
+extern char getch(void);
+extern char getche(void);
+extern void putch(char);
+extern void ungetch(char);
+
+extern __bit kbhit(void);
+
+# 31
+extern char * cgets(char *);
+extern void cputs(const char *);
+
+# 99 "/opt/microchip/xc8/v1.12/include/stdio.h"
+extern int cprintf(char *, ...);
+#pragma printf_check(cprintf)
+
+
+
+extern int _doprnt(struct __prbuf *, const register char *, register va_list);
+
+
+# 191
+#pragma printf_check(vprintf) const
+#pragma printf_check(vsprintf) const
+
+extern char * gets(char *);
+extern int puts(const char *);
+extern int scanf(const char *, ...);
+extern int sscanf(const char *, const char *, ...);
+extern int vprintf(const char *, va_list);
+extern int vsprintf(char *, const char *, va_list) __attribute__((unsupported("vsprintf() is not supported by this compiler")));
+extern int vscanf(const char *, va_list ap);
+extern int vsscanf(const char *, const char *, va_list);
+
+#pragma printf_check(printf) const
+#pragma printf_check(sprintf) const
+extern int sprintf(char *, const char *, ...);
+extern int printf(const char *, ...);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+# 31 "system.h"
+void ConfigureOscillator(void);
+
+# 13 "user.h"
+void InitApp(void);
+bool msg_empty(void);
+void msg_write(const char *msg);
+void msg_writebyte(const char msg);
+void msg_sendnext(void);
+void tohex(char val[3], char i);
+void msg_recvnext(void);
+bool msg_recvready(void);
+char msg_recv(void);
+void putch(char);
+
+void int_disable(void);
+void int_enable(void);
+
+# 11 "onewire.h"
+bool OW_reset(void);
+void OW_write_bit(bool val);
+bool OW_read_bit();
+void OW_write_byte(unsigned char byte);
+unsigned char OW_read_byte(void);
+
+void OW_search_init();
+bool OW_search(void);
+void OW_start(void);
+
+void OW_identify();
+bool OW_parasite(void);
+void OW_read_block(uint8_t code, uint8_t * data, uint8_t len);
+void OW_convert();
+
+
+inline void drive_OW_low(void);
+inline void drive_OW_high(void);
+inline void float_OW(void);
+inline bool read_OW(void);
+
+extern unsigned char romid[8];
+
+# 27 "main.c"
+char outbuff[60];
+char * outp = 0;
+uint8_t outlen = 0;
+
+char inbuff[10];
+uint8_t inlen = 0;
+
+# 38
+char prompt[9];
+
+const char * banner = "\r\n\n\nPIC 1-Wire Bridge system.  Press 'H' for help.\r\n";
+
+void main(void)
+{
+prompt[0] = 'c';
+prompt[1] = 'm';
+prompt[2] = 'd';
+prompt[3] = ' ';
+prompt[4] = '?';
+prompt[5] = '?';
+prompt[6] = '>';
+prompt[7] = ' ';
+prompt[8] = 0;
+
+bool usermode = 0;
+
+
+ConfigureOscillator();
+
+
+InitApp();
+
+OW_start();
+msg_write(banner);
+
+
+while(1)
+{
+asm("clrwdt");
+
+if (TRISAbits.TRISA5 == 1) {
+prompt[4] = 'i';
+prompt[5] = PORTAbits.RA5 ? '1':'0';
+} else {
+prompt[4] = 'o';
+prompt[5] = PORTAbits.RA5 ? '1':'0';
+}
+
+if (!msg_empty()) continue;
+
+if (!msg_recvready()) continue;
+
+char cmd = msg_recv();
+
+if (cmd == '\r' || cmd == '\n') {
+if (usermode) msg_write("\r\n");
+}else
+if (cmd == 'h' || cmd == 'H') {
+msg_write(banner);
+msg_write("\nHelp:\r\n");
+while (!msg_empty());
+msg_write("E - Enumerate the Bus\r\n");
+msg_write("R - Reset Bus\r\n");
+while (!msg_empty());
+msg_write("0,1,3 - bus to Low, High, Tristate\r\n");
+msg_write("I - Read (one) Device ID\r\n");
+while (!msg_empty());
+msg_write("P - Any device parasitic powered?\r\n");
+msg_write("S - Read scratchpad memory\r\n");
+while (!msg_empty());
+msg_write("T - read temperature of all devices\r\n");
+usermode = 1;
+} else
+if (cmd == 'r' || cmd == 'R') {
+int_disable();
+bool present = OW_reset();
+int_enable();
+if (usermode) msg_write("\r");
+if (present)
+msg_write("RESET Device detected.\r\n");
+else
+msg_write("RESET No Devices detected.\r\n");
+} else
+if (cmd == 'e' || cmd == 'E')
+{
+char count = 0;
+if (usermode) msg_write("\r");
+OW_search_init();
+while (OW_search())
+{
+char val[3];
+if (usermode) msg_write("ENUM ");
+for (char j=0; j<8; j++) {
+tohex(val, romid[j]);
+msg_write(val);
+}
+if (usermode) msg_write("\r\n"); else msg_write("\n");
+count++;
+}
+if (usermode) {
+if (count==0) msg_write("ERROR No devices found\r\n");
+} else {
+msg_write("END\n");
+}
+}else
+if (cmd == 'i' || cmd == 'I') {
+OW_identify();
+char val[3];
+if (usermode) msg_write("\rID ");
+for (char j=0; j<8; j++) {
+tohex(val, romid[j]);
+msg_write(val);
+}
+if (usermode) msg_write("\r\n"); else msg_write("\n");
+}else
+if (cmd == 'p' || cmd == 'P') {
+if (usermode) msg_write("\r");
+bool para = OW_parasite();
+if (usermode) {
+if (para)
+msg_write("PARA A Device is parasite powered\r\n");
+else
+msg_write("PARA No Device is parasite powered.\r\n");
+} else {
+if (para) msg_write("PARA\n"); else msg_write("DIRECT\n");
+}
+}else
+if (cmd == 's' || cmd =='S') {
+uint8_t scratch[9];
+romid[0] = 0;
+OW_read_block(0xBE, scratch, 9);
+if (usermode) msg_write("\rSCRATCH");
+for (char j=0; j<9; j++) {
+char val[3];
+tohex(val, scratch[j]);
+msg_write(" ");
+msg_write(val);
+}
+if (usermode) msg_write("\r\n"); else msg_write("\n");
+}else
+if (cmd == 't' || cmd == 'T') {
+char val[3];
+uint8_t scratch[9];
+
+# 178
+OW_search_init();
+while (OW_search())
+{
+
+asm("clrwdt");
+
+OW_convert();
+asm("clrwdt");
+
+
+for (char j=0; j<9; j++) scratch[j]=0;
+
+
+OW_read_block(0xBE, scratch, 9);
+
+
+if (usermode) msg_write("\r");
+msg_write("TEMP ");
+for (char j=0;j<8;j++) {
+tohex(val, romid[j]);
+msg_write(val);
+}
+msg_write(" ");
+tohex(val, scratch[1]);
+msg_write(val);
+tohex(val, scratch[0]);
+msg_write(val);
+if (usermode) msg_write("\r\n"); else msg_write("\n");
+}
+
+if (!usermode) msg_write("END\n");
+
+}else
+if (cmd == '0')
+{
+drive_OW_low();
+if (usermode)
+msg_write("\rBUS 1-Wire set low\r\n");
+else
+msg_write("LOW\n");
+}else
+if (cmd == '1')
+{
+drive_OW_high();
+if (usermode)
+msg_write("\rBUS 1-wire set high\r\n");
+else
+msg_write("HIGH\n");
+}else
+if (cmd == '3')
+{
+float_OW();
+if (usermode)
+msg_write("\rBUS 1-wire set to tri-state\r\n");
+else
+msg_write("TRISTATE\n");
+}else
+if (cmd == '!')
+{
+
+msg_write("Play dead.\r\n");
+while (1) { _nop(); }
+}else
+if (cmd == '?')
+{
+bool line = read_OW();
+if (line) {
+if (usermode) msg_write("\rBUS HIGH\r\n");
+else
+msg_write("HIGH\n");
+} else {
+if (usermode) msg_write("\rBUS LOW\r\n");
+else msg_write("LOW\n");
+}
+}else
+{
+if (usermode) {
+msg_write("ERROR Press H for Help\n");
+} else {
+msg_write("\rERROR Unknown command '");
+msg_writebyte(cmd);
+msg_write("' Press 'H' for help.\r\n");
+}
+}
+
+if (usermode) msg_write(prompt);
+}
+}
+
+# 269
+void tohex(char val[], char i)
+{
+char bt = i >> 4;
+if (bt > 9)
+val[0] = 'A' + (bt - 10);
+else
+val[0] = '0' + bt;
+bt = i & 0x0F;
+if (bt > 9)
+val[1] = 'A' + (bt - 10);
+else
+val[1] = '0' + bt;
+val[2] = 0;
+}
+
+
+
+bool msg_empty(void)
+{
+if (outp == 0) return 1;
+return 0;
+}
+
+
+void msg_write(const char *msg)
+{
+char * p = outbuff + outlen;
+while (outlen < sizeof(outbuff) && *msg != 0) {
+*(p++) = *(msg++);
+outlen++;
+}
+*p = 0;
+if (outp == 0) {
+outp = outbuff;
+PIE1bits.TXIE = 1;
+}
+}
+
+void msg_writebyte(const char msg)
+{
+if (outlen+1 >= (uint8_t)sizeof(outbuff)) return;
+outbuff[outlen++] = msg;
+outbuff[outlen] = 0;
+if (outp == 0) {
+outp = outbuff;
+PIE1bits.TXIE = 1;
+}
+}
+
+void putch(char data)
+{
+msg_writebyte(data);
+}
+
+
+void msg_sendnext(void)
+{
+
+if (outp == 0 || *outp == 0) {
+PIE1bits.TXIE = 0;
+outp = 0;
+outlen = 0;
+return;
+}
+TXREG = *outp;
+outp++;
+}
+
+
+void msg_recvnext(void)
+{
+while (PIR1bits.RCIF) {
+bool err = RCSTAbits.FERR;
+char new = RCREG;
+
+
+if (err) continue;
+
+
+if (inlen > sizeof(inbuff)) return;
+
+
+inbuff[inlen++] = new;
+}
+}
+
+bool msg_recvready(void)
+{
+if (inlen > 0) return 1;
+return 0;
+}
+
+char msg_recv(void)
+{
+if (inlen == 0) return 0;
+
+
+bool in = PIE1bits.RCIE;
+PIE1bits.RCIE = 0;
+
+char new = inbuff[0];
+inlen--;
+
+
+for (char i=0;i<inlen;i++)
+inbuff[i] = inbuff[i+1];
+
+
+PIE1bits.RCIE = in;
+return new;
+}
+
+
+void int_disable(void)
+{
+INTCONbits.GIE = 0;
+}
+
+void int_enable(void)
+{
+INTCONbits.GIE = 1;
+}

diff --git a/build/XC8_12F1822/production/onewire.p1 b/build/XC8_12F1822/production/onewire.p1
new file mode 100644 (file)
index 0000000..4ceb8ab
--- /dev/null
+++ b/build/XC8_12F1822/production/onewire.p1
@@ -0,0 +1,5450 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[s S30 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S30 . RA0 RA1 RA2 RA3 RA4 RA5 ]
+[s S31 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S31 . AN0 AN1 AN2 . AN3 ]
+[s S32 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S32 . CPS0 CPS1 CPS2 . CPS3 ]
+[s S33 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S33 . C1INP C1IN0N C1OUT . C1IN1N ]
+[s S34 :1 `uc 1 :1 `uc 1 :1 `uc 1 :2 `uc 1 :1 `uc 1 ]
+[n S34 . DACOUT SRI SRQ . SRNQ ]
+[s S35 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S35 . . SCK T0CKI . T1OSO T1CKI ]
+[s S36 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S36 . . SCL SDA nMCLR CLKR T1OSI ]
+[s S37 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S37 . MDOUT MDMIN MDCIN1 . MDCIN2 ]
+[s S38 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S38 . . SDI . OSC2 OSC1 ]
+[s S39 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S39 . . FLT0 . CLKOUT CLKIN ]
+[u S29 `S30 1 `S31 1 `S32 1 `S33 1 `S34 1 `S35 1 `S36 1 `S37 1 `S38 1 `S39 1 ]
+[n S29 . . . . . . . . . . . ]
+"489 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[v _PORTAbits `VS29 ~T0 @X0 0 e@12 ]
+[s S70 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S70 . TRISA0 TRISA1 TRISA2 TRISA3 TRISA4 TRISA5 ]
+[u S69 `S70 1 ]
+[n S69 . . ]
+"1223
+[v _TRISAbits `VS69 ~T0 @X0 0 e@140 ]
+"151 /opt/microchip/xc8/v1.12/include/pic.h
+[v __delay `(v ~T0 @X0 0 ef1`ul ]
+[p i __delay ]
+"28
+[v __nop `(v ~T0 @X0 0 ef ]
+[p i __nop ]
+"24 user.h
+[v _int_disable `(v ~T0 @X0 0 ef ]
+"15
+[v _msg_write `(v ~T0 @X0 0 ef1`*Cuc ]
+"25
+[v _int_enable `(v ~T0 @X0 0 ef ]
+[; ;pic12f1822.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[; ;pic12f1822.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1822.h: 49: typedef union {
+[; ;pic12f1822.h: 50: struct {
+[; ;pic12f1822.h: 51: unsigned INDF0 :8;
+[; ;pic12f1822.h: 52: };
+[; ;pic12f1822.h: 53: } INDF0bits_t;
+[; ;pic12f1822.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1822.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1822.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1822.h: 68: typedef union {
+[; ;pic12f1822.h: 69: struct {
+[; ;pic12f1822.h: 70: unsigned INDF1 :8;
+[; ;pic12f1822.h: 71: };
+[; ;pic12f1822.h: 72: } INDF1bits_t;
+[; ;pic12f1822.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1822.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1822.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1822.h: 87: typedef union {
+[; ;pic12f1822.h: 88: struct {
+[; ;pic12f1822.h: 89: unsigned PCL :8;
+[; ;pic12f1822.h: 90: };
+[; ;pic12f1822.h: 91: } PCLbits_t;
+[; ;pic12f1822.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1822.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1822.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1822.h: 106: typedef union {
+[; ;pic12f1822.h: 107: struct {
+[; ;pic12f1822.h: 108: unsigned C :1;
+[; ;pic12f1822.h: 109: unsigned DC :1;
+[; ;pic12f1822.h: 110: unsigned Z :1;
+[; ;pic12f1822.h: 111: unsigned nPD :1;
+[; ;pic12f1822.h: 112: unsigned nTO :1;
+[; ;pic12f1822.h: 113: };
+[; ;pic12f1822.h: 114: struct {
+[; ;pic12f1822.h: 115: unsigned CARRY :1;
+[; ;pic12f1822.h: 116: };
+[; ;pic12f1822.h: 117: struct {
+[; ;pic12f1822.h: 118: unsigned :2;
+[; ;pic12f1822.h: 119: unsigned ZERO :1;
+[; ;pic12f1822.h: 120: };
+[; ;pic12f1822.h: 121: } STATUSbits_t;
+[; ;pic12f1822.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1822.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1822.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1822.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1822.h: 169: typedef union {
+[; ;pic12f1822.h: 170: struct {
+[; ;pic12f1822.h: 171: unsigned FSR0L :8;
+[; ;pic12f1822.h: 172: };
+[; ;pic12f1822.h: 173: } FSR0Lbits_t;
+[; ;pic12f1822.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1822.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1822.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1822.h: 188: typedef union {
+[; ;pic12f1822.h: 189: struct {
+[; ;pic12f1822.h: 190: unsigned FSR0H :8;
+[; ;pic12f1822.h: 191: };
+[; ;pic12f1822.h: 192: } FSR0Hbits_t;
+[; ;pic12f1822.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1822.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1822.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1822.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1822.h: 210: typedef union {
+[; ;pic12f1822.h: 211: struct {
+[; ;pic12f1822.h: 212: unsigned FSR1L :8;
+[; ;pic12f1822.h: 213: };
+[; ;pic12f1822.h: 214: } FSR1Lbits_t;
+[; ;pic12f1822.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1822.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1822.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1822.h: 229: typedef union {
+[; ;pic12f1822.h: 230: struct {
+[; ;pic12f1822.h: 231: unsigned FSR1H :8;
+[; ;pic12f1822.h: 232: };
+[; ;pic12f1822.h: 233: } FSR1Hbits_t;
+[; ;pic12f1822.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1822.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1822.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1822.h: 248: typedef union {
+[; ;pic12f1822.h: 249: struct {
+[; ;pic12f1822.h: 250: unsigned BSR0 :1;
+[; ;pic12f1822.h: 251: unsigned BSR1 :1;
+[; ;pic12f1822.h: 252: unsigned BSR2 :1;
+[; ;pic12f1822.h: 253: unsigned BSR3 :1;
+[; ;pic12f1822.h: 254: unsigned BSR4 :1;
+[; ;pic12f1822.h: 255: };
+[; ;pic12f1822.h: 256: struct {
+[; ;pic12f1822.h: 257: unsigned BSR :5;
+[; ;pic12f1822.h: 258: };
+[; ;pic12f1822.h: 259: } BSRbits_t;
+[; ;pic12f1822.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1822.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1822.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1822.h: 299: typedef union {
+[; ;pic12f1822.h: 300: struct {
+[; ;pic12f1822.h: 301: unsigned WREG0 :8;
+[; ;pic12f1822.h: 302: };
+[; ;pic12f1822.h: 303: } WREGbits_t;
+[; ;pic12f1822.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1822.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1822.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1822.h: 318: typedef union {
+[; ;pic12f1822.h: 319: struct {
+[; ;pic12f1822.h: 320: unsigned PCLATH :7;
+[; ;pic12f1822.h: 321: };
+[; ;pic12f1822.h: 322: } PCLATHbits_t;
+[; ;pic12f1822.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1822.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1822.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1822.h: 337: typedef union {
+[; ;pic12f1822.h: 338: struct {
+[; ;pic12f1822.h: 339: unsigned IOCIF :1;
+[; ;pic12f1822.h: 340: unsigned INTF :1;
+[; ;pic12f1822.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1822.h: 342: unsigned IOCIE :1;
+[; ;pic12f1822.h: 343: unsigned INTE :1;
+[; ;pic12f1822.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1822.h: 345: unsigned PEIE :1;
+[; ;pic12f1822.h: 346: unsigned GIE :1;
+[; ;pic12f1822.h: 347: };
+[; ;pic12f1822.h: 348: struct {
+[; ;pic12f1822.h: 349: unsigned :2;
+[; ;pic12f1822.h: 350: unsigned T0IF :1;
+[; ;pic12f1822.h: 351: unsigned :2;
+[; ;pic12f1822.h: 352: unsigned T0IE :1;
+[; ;pic12f1822.h: 353: };
+[; ;pic12f1822.h: 354: } INTCONbits_t;
+[; ;pic12f1822.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1822.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1822.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1822.h: 414: typedef union {
+[; ;pic12f1822.h: 415: struct {
+[; ;pic12f1822.h: 416: unsigned RA0 :1;
+[; ;pic12f1822.h: 417: unsigned RA1 :1;
+[; ;pic12f1822.h: 418: unsigned RA2 :1;
+[; ;pic12f1822.h: 419: unsigned RA3 :1;
+[; ;pic12f1822.h: 420: unsigned RA4 :1;
+[; ;pic12f1822.h: 421: unsigned RA5 :1;
+[; ;pic12f1822.h: 422: };
+[; ;pic12f1822.h: 423: struct {
+[; ;pic12f1822.h: 424: unsigned AN0 :1;
+[; ;pic12f1822.h: 425: unsigned AN1 :1;
+[; ;pic12f1822.h: 426: unsigned AN2 :1;
+[; ;pic12f1822.h: 427: unsigned :1;
+[; ;pic12f1822.h: 428: unsigned AN3 :1;
+[; ;pic12f1822.h: 429: };
+[; ;pic12f1822.h: 430: struct {
+[; ;pic12f1822.h: 431: unsigned CPS0 :1;
+[; ;pic12f1822.h: 432: unsigned CPS1 :1;
+[; ;pic12f1822.h: 433: unsigned CPS2 :1;
+[; ;pic12f1822.h: 434: unsigned :1;
+[; ;pic12f1822.h: 435: unsigned CPS3 :1;
+[; ;pic12f1822.h: 436: };
+[; ;pic12f1822.h: 437: struct {
+[; ;pic12f1822.h: 438: unsigned C1INP :1;
+[; ;pic12f1822.h: 439: unsigned C1IN0N :1;
+[; ;pic12f1822.h: 440: unsigned C1OUT :1;
+[; ;pic12f1822.h: 441: unsigned :1;
+[; ;pic12f1822.h: 442: unsigned C1IN1N :1;
+[; ;pic12f1822.h: 443: };
+[; ;pic12f1822.h: 444: struct {
+[; ;pic12f1822.h: 445: unsigned DACOUT :1;
+[; ;pic12f1822.h: 446: unsigned SRI :1;
+[; ;pic12f1822.h: 447: unsigned SRQ :1;
+[; ;pic12f1822.h: 448: unsigned :2;
+[; ;pic12f1822.h: 449: unsigned SRNQ :1;
+[; ;pic12f1822.h: 450: };
+[; ;pic12f1822.h: 451: struct {
+[; ;pic12f1822.h: 452: unsigned :1;
+[; ;pic12f1822.h: 453: unsigned SCK :1;
+[; ;pic12f1822.h: 454: unsigned T0CKI :1;
+[; ;pic12f1822.h: 455: unsigned :1;
+[; ;pic12f1822.h: 456: unsigned T1OSO :1;
+[; ;pic12f1822.h: 457: unsigned T1CKI :1;
+[; ;pic12f1822.h: 458: };
+[; ;pic12f1822.h: 459: struct {
+[; ;pic12f1822.h: 460: unsigned :1;
+[; ;pic12f1822.h: 461: unsigned SCL :1;
+[; ;pic12f1822.h: 462: unsigned SDA :1;
+[; ;pic12f1822.h: 463: unsigned nMCLR :1;
+[; ;pic12f1822.h: 464: unsigned CLKR :1;
+[; ;pic12f1822.h: 465: unsigned T1OSI :1;
+[; ;pic12f1822.h: 466: };
+[; ;pic12f1822.h: 467: struct {
+[; ;pic12f1822.h: 468: unsigned MDOUT :1;
+[; ;pic12f1822.h: 469: unsigned MDMIN :1;
+[; ;pic12f1822.h: 470: unsigned MDCIN1 :1;
+[; ;pic12f1822.h: 471: unsigned :1;
+[; ;pic12f1822.h: 472: unsigned MDCIN2 :1;
+[; ;pic12f1822.h: 473: };
+[; ;pic12f1822.h: 474: struct {
+[; ;pic12f1822.h: 475: unsigned :2;
+[; ;pic12f1822.h: 476: unsigned SDI :1;
+[; ;pic12f1822.h: 477: unsigned :1;
+[; ;pic12f1822.h: 478: unsigned OSC2 :1;
+[; ;pic12f1822.h: 479: unsigned OSC1 :1;
+[; ;pic12f1822.h: 480: };
+[; ;pic12f1822.h: 481: struct {
+[; ;pic12f1822.h: 482: unsigned :2;
+[; ;pic12f1822.h: 483: unsigned FLT0 :1;
+[; ;pic12f1822.h: 484: unsigned :1;
+[; ;pic12f1822.h: 485: unsigned CLKOUT :1;
+[; ;pic12f1822.h: 486: unsigned CLKIN :1;
+[; ;pic12f1822.h: 487: };
+[; ;pic12f1822.h: 488: } PORTAbits_t;
+[; ;pic12f1822.h: 489: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1822.h: 698: extern volatile unsigned char PIR1 @ 0x011;
+"700
+[; ;pic12f1822.h: 700: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1822.h: 703: typedef union {
+[; ;pic12f1822.h: 704: struct {
+[; ;pic12f1822.h: 705: unsigned TMR1IF :1;
+[; ;pic12f1822.h: 706: unsigned TMR2IF :1;
+[; ;pic12f1822.h: 707: unsigned CCP1IF :1;
+[; ;pic12f1822.h: 708: unsigned SSP1IF :1;
+[; ;pic12f1822.h: 709: unsigned TXIF :1;
+[; ;pic12f1822.h: 710: unsigned RCIF :1;
+[; ;pic12f1822.h: 711: unsigned ADIF :1;
+[; ;pic12f1822.h: 712: unsigned TMR1GIF :1;
+[; ;pic12f1822.h: 713: };
+[; ;pic12f1822.h: 714: } PIR1bits_t;
+[; ;pic12f1822.h: 715: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1822.h: 759: extern volatile unsigned char PIR2 @ 0x012;
+"761
+[; ;pic12f1822.h: 761: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1822.h: 764: typedef union {
+[; ;pic12f1822.h: 765: struct {
+[; ;pic12f1822.h: 766: unsigned :3;
+[; ;pic12f1822.h: 767: unsigned BCL1IF :1;
+[; ;pic12f1822.h: 768: unsigned EEIF :1;
+[; ;pic12f1822.h: 769: unsigned C1IF :1;
+[; ;pic12f1822.h: 770: unsigned :1;
+[; ;pic12f1822.h: 771: unsigned OSFIF :1;
+[; ;pic12f1822.h: 772: };
+[; ;pic12f1822.h: 773: } PIR2bits_t;
+[; ;pic12f1822.h: 774: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1822.h: 798: extern volatile unsigned char TMR0 @ 0x015;
+"800
+[; ;pic12f1822.h: 800: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1822.h: 803: typedef union {
+[; ;pic12f1822.h: 804: struct {
+[; ;pic12f1822.h: 805: unsigned TMR0 :8;
+[; ;pic12f1822.h: 806: };
+[; ;pic12f1822.h: 807: } TMR0bits_t;
+[; ;pic12f1822.h: 808: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1822.h: 817: extern volatile unsigned short TMR1 @ 0x016;
+"819
+[; ;pic12f1822.h: 819: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1822.h: 823: extern volatile unsigned char TMR1L @ 0x016;
+"825
+[; ;pic12f1822.h: 825: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1822.h: 828: typedef union {
+[; ;pic12f1822.h: 829: struct {
+[; ;pic12f1822.h: 830: unsigned TMR1L :8;
+[; ;pic12f1822.h: 831: };
+[; ;pic12f1822.h: 832: } TMR1Lbits_t;
+[; ;pic12f1822.h: 833: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1822.h: 842: extern volatile unsigned char TMR1H @ 0x017;
+"844
+[; ;pic12f1822.h: 844: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1822.h: 847: typedef union {
+[; ;pic12f1822.h: 848: struct {
+[; ;pic12f1822.h: 849: unsigned TMR1H :8;
+[; ;pic12f1822.h: 850: };
+[; ;pic12f1822.h: 851: } TMR1Hbits_t;
+[; ;pic12f1822.h: 852: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1822.h: 861: extern volatile unsigned char T1CON @ 0x018;
+"863
+[; ;pic12f1822.h: 863: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1822.h: 866: typedef union {
+[; ;pic12f1822.h: 867: struct {
+[; ;pic12f1822.h: 868: unsigned TMR1ON :1;
+[; ;pic12f1822.h: 869: unsigned :1;
+[; ;pic12f1822.h: 870: unsigned nT1SYNC :1;
+[; ;pic12f1822.h: 871: unsigned T1OSCEN :1;
+[; ;pic12f1822.h: 872: unsigned T1CKPS0 :1;
+[; ;pic12f1822.h: 873: unsigned T1CKPS1 :1;
+[; ;pic12f1822.h: 874: unsigned TMR1CS0 :1;
+[; ;pic12f1822.h: 875: unsigned TMR1CS1 :1;
+[; ;pic12f1822.h: 876: };
+[; ;pic12f1822.h: 877: struct {
+[; ;pic12f1822.h: 878: unsigned :4;
+[; ;pic12f1822.h: 879: unsigned T1CKPS :2;
+[; ;pic12f1822.h: 880: unsigned TMR1CS :2;
+[; ;pic12f1822.h: 881: };
+[; ;pic12f1822.h: 882: } T1CONbits_t;
+[; ;pic12f1822.h: 883: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1822.h: 932: extern volatile unsigned char T1GCON @ 0x019;
+"934
+[; ;pic12f1822.h: 934: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1822.h: 937: typedef union {
+[; ;pic12f1822.h: 938: struct {
+[; ;pic12f1822.h: 939: unsigned T1GSS0 :1;
+[; ;pic12f1822.h: 940: unsigned T1GSS1 :1;
+[; ;pic12f1822.h: 941: unsigned T1GVAL :1;
+[; ;pic12f1822.h: 942: unsigned T1GGO_nDONE :1;
+[; ;pic12f1822.h: 943: unsigned T1GSPM :1;
+[; ;pic12f1822.h: 944: unsigned T1GTM :1;
+[; ;pic12f1822.h: 945: unsigned T1GPOL :1;
+[; ;pic12f1822.h: 946: unsigned TMR1GE :1;
+[; ;pic12f1822.h: 947: };
+[; ;pic12f1822.h: 948: struct {
+[; ;pic12f1822.h: 949: unsigned T1GSS :2;
+[; ;pic12f1822.h: 950: unsigned :1;
+[; ;pic12f1822.h: 951: unsigned T1GGO :1;
+[; ;pic12f1822.h: 952: };
+[; ;pic12f1822.h: 953: } T1GCONbits_t;
+[; ;pic12f1822.h: 954: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1822.h: 1008: extern volatile unsigned char TMR2 @ 0x01A;
+"1010
+[; ;pic12f1822.h: 1010: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1822.h: 1013: typedef union {
+[; ;pic12f1822.h: 1014: struct {
+[; ;pic12f1822.h: 1015: unsigned TMR2 :8;
+[; ;pic12f1822.h: 1016: };
+[; ;pic12f1822.h: 1017: } TMR2bits_t;
+[; ;pic12f1822.h: 1018: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1822.h: 1027: extern volatile unsigned char PR2 @ 0x01B;
+"1029
+[; ;pic12f1822.h: 1029: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1822.h: 1032: typedef union {
+[; ;pic12f1822.h: 1033: struct {
+[; ;pic12f1822.h: 1034: unsigned PR2 :8;
+[; ;pic12f1822.h: 1035: };
+[; ;pic12f1822.h: 1036: } PR2bits_t;
+[; ;pic12f1822.h: 1037: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1822.h: 1046: extern volatile unsigned char T2CON @ 0x01C;
+"1048
+[; ;pic12f1822.h: 1048: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1822.h: 1051: typedef union {
+[; ;pic12f1822.h: 1052: struct {
+[; ;pic12f1822.h: 1053: unsigned T2CKPS0 :1;
+[; ;pic12f1822.h: 1054: unsigned T2CKPS1 :1;
+[; ;pic12f1822.h: 1055: unsigned TMR2ON :1;
+[; ;pic12f1822.h: 1056: unsigned T2OUTPS0 :1;
+[; ;pic12f1822.h: 1057: unsigned T2OUTPS1 :1;
+[; ;pic12f1822.h: 1058: unsigned T2OUTPS2 :1;
+[; ;pic12f1822.h: 1059: unsigned T2OUTPS3 :1;
+[; ;pic12f1822.h: 1060: };
+[; ;pic12f1822.h: 1061: struct {
+[; ;pic12f1822.h: 1062: unsigned T2CKPS :2;
+[; ;pic12f1822.h: 1063: unsigned :1;
+[; ;pic12f1822.h: 1064: unsigned T2OUTPS :4;
+[; ;pic12f1822.h: 1065: };
+[; ;pic12f1822.h: 1066: } T2CONbits_t;
+[; ;pic12f1822.h: 1067: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1822.h: 1116: extern volatile unsigned char CPSCON0 @ 0x01E;
+"1118
+[; ;pic12f1822.h: 1118: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1822.h: 1121: typedef union {
+[; ;pic12f1822.h: 1122: struct {
+[; ;pic12f1822.h: 1123: unsigned T0XCS :1;
+[; ;pic12f1822.h: 1124: unsigned CPSOUT :1;
+[; ;pic12f1822.h: 1125: unsigned CPSRNG0 :1;
+[; ;pic12f1822.h: 1126: unsigned CPSRNG1 :1;
+[; ;pic12f1822.h: 1127: unsigned :2;
+[; ;pic12f1822.h: 1128: unsigned CPSRM :1;
+[; ;pic12f1822.h: 1129: unsigned CPSON :1;
+[; ;pic12f1822.h: 1130: };
+[; ;pic12f1822.h: 1131: struct {
+[; ;pic12f1822.h: 1132: unsigned :2;
+[; ;pic12f1822.h: 1133: unsigned CPSRNG :2;
+[; ;pic12f1822.h: 1134: };
+[; ;pic12f1822.h: 1135: } CPSCON0bits_t;
+[; ;pic12f1822.h: 1136: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1822.h: 1175: extern volatile unsigned char CPSCON1 @ 0x01F;
+"1177
+[; ;pic12f1822.h: 1177: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1822.h: 1180: typedef union {
+[; ;pic12f1822.h: 1181: struct {
+[; ;pic12f1822.h: 1182: unsigned CPSCH0 :1;
+[; ;pic12f1822.h: 1183: unsigned CPSCH1 :1;
+[; ;pic12f1822.h: 1184: };
+[; ;pic12f1822.h: 1185: struct {
+[; ;pic12f1822.h: 1186: unsigned CPSCH :2;
+[; ;pic12f1822.h: 1187: };
+[; ;pic12f1822.h: 1188: } CPSCON1bits_t;
+[; ;pic12f1822.h: 1189: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1822.h: 1208: extern volatile unsigned char TRISA @ 0x08C;
+"1210
+[; ;pic12f1822.h: 1210: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1822.h: 1213: typedef union {
+[; ;pic12f1822.h: 1214: struct {
+[; ;pic12f1822.h: 1215: unsigned TRISA0 :1;
+[; ;pic12f1822.h: 1216: unsigned TRISA1 :1;
+[; ;pic12f1822.h: 1217: unsigned TRISA2 :1;
+[; ;pic12f1822.h: 1218: unsigned TRISA3 :1;
+[; ;pic12f1822.h: 1219: unsigned TRISA4 :1;
+[; ;pic12f1822.h: 1220: unsigned TRISA5 :1;
+[; ;pic12f1822.h: 1221: };
+[; ;pic12f1822.h: 1222: } TRISAbits_t;
+[; ;pic12f1822.h: 1223: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1822.h: 1257: extern volatile unsigned char PIE1 @ 0x091;
+"1259
+[; ;pic12f1822.h: 1259: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1822.h: 1262: typedef union {
+[; ;pic12f1822.h: 1263: struct {
+[; ;pic12f1822.h: 1264: unsigned TMR1IE :1;
+[; ;pic12f1822.h: 1265: unsigned TMR2IE :1;
+[; ;pic12f1822.h: 1266: unsigned CCP1IE :1;
+[; ;pic12f1822.h: 1267: unsigned SSP1IE :1;
+[; ;pic12f1822.h: 1268: unsigned TXIE :1;
+[; ;pic12f1822.h: 1269: unsigned RCIE :1;
+[; ;pic12f1822.h: 1270: unsigned ADIE :1;
+[; ;pic12f1822.h: 1271: unsigned TMR1GIE :1;
+[; ;pic12f1822.h: 1272: };
+[; ;pic12f1822.h: 1273: } PIE1bits_t;
+[; ;pic12f1822.h: 1274: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1822.h: 1318: extern volatile unsigned char PIE2 @ 0x092;
+"1320
+[; ;pic12f1822.h: 1320: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1822.h: 1323: typedef union {
+[; ;pic12f1822.h: 1324: struct {
+[; ;pic12f1822.h: 1325: unsigned :3;
+[; ;pic12f1822.h: 1326: unsigned BCL1IE :1;
+[; ;pic12f1822.h: 1327: unsigned EEIE :1;
+[; ;pic12f1822.h: 1328: unsigned C1IE :1;
+[; ;pic12f1822.h: 1329: unsigned :1;
+[; ;pic12f1822.h: 1330: unsigned OSFIE :1;
+[; ;pic12f1822.h: 1331: };
+[; ;pic12f1822.h: 1332: } PIE2bits_t;
+[; ;pic12f1822.h: 1333: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1822.h: 1357: extern volatile unsigned char OPTION_REG @ 0x095;
+"1359
+[; ;pic12f1822.h: 1359: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1822.h: 1362: typedef union {
+[; ;pic12f1822.h: 1363: struct {
+[; ;pic12f1822.h: 1364: unsigned PS0 :1;
+[; ;pic12f1822.h: 1365: unsigned PS1 :1;
+[; ;pic12f1822.h: 1366: unsigned PS2 :1;
+[; ;pic12f1822.h: 1367: unsigned PSA :1;
+[; ;pic12f1822.h: 1368: unsigned TMR0SE :1;
+[; ;pic12f1822.h: 1369: unsigned TMR0CS :1;
+[; ;pic12f1822.h: 1370: unsigned INTEDG :1;
+[; ;pic12f1822.h: 1371: unsigned nWPUEN :1;
+[; ;pic12f1822.h: 1372: };
+[; ;pic12f1822.h: 1373: struct {
+[; ;pic12f1822.h: 1374: unsigned PS :3;
+[; ;pic12f1822.h: 1375: unsigned :1;
+[; ;pic12f1822.h: 1376: unsigned T0SE :1;
+[; ;pic12f1822.h: 1377: unsigned T0CS :1;
+[; ;pic12f1822.h: 1378: };
+[; ;pic12f1822.h: 1379: } OPTION_REGbits_t;
+[; ;pic12f1822.h: 1380: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1822.h: 1439: extern volatile unsigned char PCON @ 0x096;
+"1441
+[; ;pic12f1822.h: 1441: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1822.h: 1444: typedef union {
+[; ;pic12f1822.h: 1445: struct {
+[; ;pic12f1822.h: 1446: unsigned nBOR :1;
+[; ;pic12f1822.h: 1447: unsigned nPOR :1;
+[; ;pic12f1822.h: 1448: unsigned nRI :1;
+[; ;pic12f1822.h: 1449: unsigned nRMCLR :1;
+[; ;pic12f1822.h: 1450: unsigned :2;
+[; ;pic12f1822.h: 1451: unsigned STKUNF :1;
+[; ;pic12f1822.h: 1452: unsigned STKOVF :1;
+[; ;pic12f1822.h: 1453: };
+[; ;pic12f1822.h: 1454: } PCONbits_t;
+[; ;pic12f1822.h: 1455: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1822.h: 1489: extern volatile unsigned char WDTCON @ 0x097;
+"1491
+[; ;pic12f1822.h: 1491: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1822.h: 1494: typedef union {
+[; ;pic12f1822.h: 1495: struct {
+[; ;pic12f1822.h: 1496: unsigned SWDTEN :1;
+[; ;pic12f1822.h: 1497: unsigned WDTPS0 :1;
+[; ;pic12f1822.h: 1498: unsigned WDTPS1 :1;
+[; ;pic12f1822.h: 1499: unsigned WDTPS2 :1;
+[; ;pic12f1822.h: 1500: unsigned WDTPS3 :1;
+[; ;pic12f1822.h: 1501: unsigned WDTPS4 :1;
+[; ;pic12f1822.h: 1502: };
+[; ;pic12f1822.h: 1503: struct {
+[; ;pic12f1822.h: 1504: unsigned :1;
+[; ;pic12f1822.h: 1505: unsigned WDTPS :5;
+[; ;pic12f1822.h: 1506: };
+[; ;pic12f1822.h: 1507: } WDTCONbits_t;
+[; ;pic12f1822.h: 1508: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1822.h: 1547: extern volatile unsigned char OSCTUNE @ 0x098;
+"1549
+[; ;pic12f1822.h: 1549: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1822.h: 1552: typedef union {
+[; ;pic12f1822.h: 1553: struct {
+[; ;pic12f1822.h: 1554: unsigned TUN0 :1;
+[; ;pic12f1822.h: 1555: unsigned TUN1 :1;
+[; ;pic12f1822.h: 1556: unsigned TUN2 :1;
+[; ;pic12f1822.h: 1557: unsigned TUN3 :1;
+[; ;pic12f1822.h: 1558: unsigned TUN4 :1;
+[; ;pic12f1822.h: 1559: unsigned TUN5 :1;
+[; ;pic12f1822.h: 1560: };
+[; ;pic12f1822.h: 1561: struct {
+[; ;pic12f1822.h: 1562: unsigned TUN :6;
+[; ;pic12f1822.h: 1563: };
+[; ;pic12f1822.h: 1564: } OSCTUNEbits_t;
+[; ;pic12f1822.h: 1565: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1822.h: 1604: extern volatile unsigned char OSCCON @ 0x099;
+"1606
+[; ;pic12f1822.h: 1606: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1822.h: 1609: typedef union {
+[; ;pic12f1822.h: 1610: struct {
+[; ;pic12f1822.h: 1611: unsigned SCS0 :1;
+[; ;pic12f1822.h: 1612: unsigned SCS1 :1;
+[; ;pic12f1822.h: 1613: unsigned :1;
+[; ;pic12f1822.h: 1614: unsigned IRCF0 :1;
+[; ;pic12f1822.h: 1615: unsigned IRCF1 :1;
+[; ;pic12f1822.h: 1616: unsigned IRCF2 :1;
+[; ;pic12f1822.h: 1617: unsigned IRCF3 :1;
+[; ;pic12f1822.h: 1618: unsigned SPLLEN :1;
+[; ;pic12f1822.h: 1619: };
+[; ;pic12f1822.h: 1620: struct {
+[; ;pic12f1822.h: 1621: unsigned SCS :2;
+[; ;pic12f1822.h: 1622: unsigned :1;
+[; ;pic12f1822.h: 1623: unsigned IRCF :4;
+[; ;pic12f1822.h: 1624: };
+[; ;pic12f1822.h: 1625: } OSCCONbits_t;
+[; ;pic12f1822.h: 1626: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1822.h: 1675: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1677
+[; ;pic12f1822.h: 1677: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1822.h: 1680: typedef union {
+[; ;pic12f1822.h: 1681: struct {
+[; ;pic12f1822.h: 1682: unsigned HFIOFS :1;
+[; ;pic12f1822.h: 1683: unsigned LFIOFR :1;
+[; ;pic12f1822.h: 1684: unsigned MFIOFR :1;
+[; ;pic12f1822.h: 1685: unsigned HFIOFL :1;
+[; ;pic12f1822.h: 1686: unsigned HFIOFR :1;
+[; ;pic12f1822.h: 1687: unsigned OSTS :1;
+[; ;pic12f1822.h: 1688: unsigned PLLR :1;
+[; ;pic12f1822.h: 1689: unsigned T1OSCR :1;
+[; ;pic12f1822.h: 1690: };
+[; ;pic12f1822.h: 1691: } OSCSTATbits_t;
+[; ;pic12f1822.h: 1692: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1822.h: 1736: extern volatile unsigned short ADRES @ 0x09B;
+"1738
+[; ;pic12f1822.h: 1738: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1822.h: 1742: extern volatile unsigned char ADRESL @ 0x09B;
+"1744
+[; ;pic12f1822.h: 1744: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1822.h: 1747: typedef union {
+[; ;pic12f1822.h: 1748: struct {
+[; ;pic12f1822.h: 1749: unsigned ADRESL :8;
+[; ;pic12f1822.h: 1750: };
+[; ;pic12f1822.h: 1751: } ADRESLbits_t;
+[; ;pic12f1822.h: 1752: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1822.h: 1761: extern volatile unsigned char ADRESH @ 0x09C;
+"1763
+[; ;pic12f1822.h: 1763: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1822.h: 1766: typedef union {
+[; ;pic12f1822.h: 1767: struct {
+[; ;pic12f1822.h: 1768: unsigned ADRESH :8;
+[; ;pic12f1822.h: 1769: };
+[; ;pic12f1822.h: 1770: } ADRESHbits_t;
+[; ;pic12f1822.h: 1771: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1822.h: 1780: extern volatile unsigned char ADCON0 @ 0x09D;
+"1782
+[; ;pic12f1822.h: 1782: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1822.h: 1785: typedef union {
+[; ;pic12f1822.h: 1786: struct {
+[; ;pic12f1822.h: 1787: unsigned ADON :1;
+[; ;pic12f1822.h: 1788: unsigned GO_nDONE :1;
+[; ;pic12f1822.h: 1789: unsigned CHS0 :1;
+[; ;pic12f1822.h: 1790: unsigned CHS1 :1;
+[; ;pic12f1822.h: 1791: unsigned CHS2 :1;
+[; ;pic12f1822.h: 1792: unsigned CHS3 :1;
+[; ;pic12f1822.h: 1793: unsigned CHS4 :1;
+[; ;pic12f1822.h: 1794: };
+[; ;pic12f1822.h: 1795: struct {
+[; ;pic12f1822.h: 1796: unsigned :1;
+[; ;pic12f1822.h: 1797: unsigned ADGO :1;
+[; ;pic12f1822.h: 1798: unsigned CHS :5;
+[; ;pic12f1822.h: 1799: };
+[; ;pic12f1822.h: 1800: struct {
+[; ;pic12f1822.h: 1801: unsigned :1;
+[; ;pic12f1822.h: 1802: unsigned GO :1;
+[; ;pic12f1822.h: 1803: };
+[; ;pic12f1822.h: 1804: struct {
+[; ;pic12f1822.h: 1805: unsigned :1;
+[; ;pic12f1822.h: 1806: unsigned nDONE :1;
+[; ;pic12f1822.h: 1807: };
+[; ;pic12f1822.h: 1808: } ADCON0bits_t;
+[; ;pic12f1822.h: 1809: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1822.h: 1868: extern volatile unsigned char ADCON1 @ 0x09E;
+"1870
+[; ;pic12f1822.h: 1870: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1822.h: 1873: typedef union {
+[; ;pic12f1822.h: 1874: struct {
+[; ;pic12f1822.h: 1875: unsigned ADPREF0 :1;
+[; ;pic12f1822.h: 1876: unsigned ADPREF1 :1;
+[; ;pic12f1822.h: 1877: unsigned :2;
+[; ;pic12f1822.h: 1878: unsigned ADCS0 :1;
+[; ;pic12f1822.h: 1879: unsigned ADCS1 :1;
+[; ;pic12f1822.h: 1880: unsigned ADCS2 :1;
+[; ;pic12f1822.h: 1881: unsigned ADFM :1;
+[; ;pic12f1822.h: 1882: };
+[; ;pic12f1822.h: 1883: struct {
+[; ;pic12f1822.h: 1884: unsigned ADPREF :2;
+[; ;pic12f1822.h: 1885: unsigned :2;
+[; ;pic12f1822.h: 1886: unsigned ADCS :3;
+[; ;pic12f1822.h: 1887: };
+[; ;pic12f1822.h: 1888: } ADCON1bits_t;
+[; ;pic12f1822.h: 1889: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1822.h: 1933: extern volatile unsigned char LATA @ 0x10C;
+"1935
+[; ;pic12f1822.h: 1935: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1822.h: 1938: typedef union {
+[; ;pic12f1822.h: 1939: struct {
+[; ;pic12f1822.h: 1940: unsigned LATA0 :1;
+[; ;pic12f1822.h: 1941: unsigned LATA1 :1;
+[; ;pic12f1822.h: 1942: unsigned LATA2 :1;
+[; ;pic12f1822.h: 1943: unsigned :1;
+[; ;pic12f1822.h: 1944: unsigned LATA4 :1;
+[; ;pic12f1822.h: 1945: unsigned LATA5 :1;
+[; ;pic12f1822.h: 1946: };
+[; ;pic12f1822.h: 1947: } LATAbits_t;
+[; ;pic12f1822.h: 1948: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1822.h: 1977: extern volatile unsigned char CM1CON0 @ 0x111;
+"1979
+[; ;pic12f1822.h: 1979: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1822.h: 1982: typedef union {
+[; ;pic12f1822.h: 1983: struct {
+[; ;pic12f1822.h: 1984: unsigned C1SYNC :1;
+[; ;pic12f1822.h: 1985: unsigned C1HYS :1;
+[; ;pic12f1822.h: 1986: unsigned C1SP :1;
+[; ;pic12f1822.h: 1987: unsigned :1;
+[; ;pic12f1822.h: 1988: unsigned C1POL :1;
+[; ;pic12f1822.h: 1989: unsigned C1OE :1;
+[; ;pic12f1822.h: 1990: unsigned C1OUT :1;
+[; ;pic12f1822.h: 1991: unsigned C1ON :1;
+[; ;pic12f1822.h: 1992: };
+[; ;pic12f1822.h: 1993: } CM1CON0bits_t;
+[; ;pic12f1822.h: 1994: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1822.h: 2033: extern volatile unsigned char CM1CON1 @ 0x112;
+"2035
+[; ;pic12f1822.h: 2035: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1822.h: 2038: typedef union {
+[; ;pic12f1822.h: 2039: struct {
+[; ;pic12f1822.h: 2040: unsigned C1NCH0 :1;
+[; ;pic12f1822.h: 2041: unsigned :3;
+[; ;pic12f1822.h: 2042: unsigned C1PCH0 :1;
+[; ;pic12f1822.h: 2043: unsigned C1PCH1 :1;
+[; ;pic12f1822.h: 2044: unsigned C1INTN :1;
+[; ;pic12f1822.h: 2045: unsigned C1INTP :1;
+[; ;pic12f1822.h: 2046: };
+[; ;pic12f1822.h: 2047: struct {
+[; ;pic12f1822.h: 2048: unsigned :4;
+[; ;pic12f1822.h: 2049: unsigned C1PCH :2;
+[; ;pic12f1822.h: 2050: };
+[; ;pic12f1822.h: 2051: } CM1CON1bits_t;
+[; ;pic12f1822.h: 2052: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1822.h: 2086: extern volatile unsigned char CMOUT @ 0x115;
+"2088
+[; ;pic12f1822.h: 2088: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1822.h: 2091: typedef union {
+[; ;pic12f1822.h: 2092: struct {
+[; ;pic12f1822.h: 2093: unsigned MC1OUT :1;
+[; ;pic12f1822.h: 2094: };
+[; ;pic12f1822.h: 2095: } CMOUTbits_t;
+[; ;pic12f1822.h: 2096: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1822.h: 2105: extern volatile unsigned char BORCON @ 0x116;
+"2107
+[; ;pic12f1822.h: 2107: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1822.h: 2110: typedef union {
+[; ;pic12f1822.h: 2111: struct {
+[; ;pic12f1822.h: 2112: unsigned BORRDY :1;
+[; ;pic12f1822.h: 2113: unsigned :6;
+[; ;pic12f1822.h: 2114: unsigned SBOREN :1;
+[; ;pic12f1822.h: 2115: };
+[; ;pic12f1822.h: 2116: } BORCONbits_t;
+[; ;pic12f1822.h: 2117: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1822.h: 2131: extern volatile unsigned char FVRCON @ 0x117;
+"2133
+[; ;pic12f1822.h: 2133: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1822.h: 2136: typedef union {
+[; ;pic12f1822.h: 2137: struct {
+[; ;pic12f1822.h: 2138: unsigned ADFVR0 :1;
+[; ;pic12f1822.h: 2139: unsigned ADFVR1 :1;
+[; ;pic12f1822.h: 2140: unsigned CDAFVR0 :1;
+[; ;pic12f1822.h: 2141: unsigned CDAFVR1 :1;
+[; ;pic12f1822.h: 2142: unsigned TSRNG :1;
+[; ;pic12f1822.h: 2143: unsigned TSEN :1;
+[; ;pic12f1822.h: 2144: unsigned FVRRDY :1;
+[; ;pic12f1822.h: 2145: unsigned FVREN :1;
+[; ;pic12f1822.h: 2146: };
+[; ;pic12f1822.h: 2147: struct {
+[; ;pic12f1822.h: 2148: unsigned ADFVR :2;
+[; ;pic12f1822.h: 2149: unsigned CDAFVR :2;
+[; ;pic12f1822.h: 2150: };
+[; ;pic12f1822.h: 2151: } FVRCONbits_t;
+[; ;pic12f1822.h: 2152: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1822.h: 2206: extern volatile unsigned char DACCON0 @ 0x118;
+"2208
+[; ;pic12f1822.h: 2208: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1822.h: 2211: typedef union {
+[; ;pic12f1822.h: 2212: struct {
+[; ;pic12f1822.h: 2213: unsigned :2;
+[; ;pic12f1822.h: 2214: unsigned DACPSS0 :1;
+[; ;pic12f1822.h: 2215: unsigned DACPSS1 :1;
+[; ;pic12f1822.h: 2216: unsigned :1;
+[; ;pic12f1822.h: 2217: unsigned DACOE :1;
+[; ;pic12f1822.h: 2218: unsigned DACLPS :1;
+[; ;pic12f1822.h: 2219: unsigned DACEN :1;
+[; ;pic12f1822.h: 2220: };
+[; ;pic12f1822.h: 2221: struct {
+[; ;pic12f1822.h: 2222: unsigned :2;
+[; ;pic12f1822.h: 2223: unsigned DACPSS :2;
+[; ;pic12f1822.h: 2224: };
+[; ;pic12f1822.h: 2225: } DACCON0bits_t;
+[; ;pic12f1822.h: 2226: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1822.h: 2260: extern volatile unsigned char DACCON1 @ 0x119;
+"2262
+[; ;pic12f1822.h: 2262: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1822.h: 2265: typedef union {
+[; ;pic12f1822.h: 2266: struct {
+[; ;pic12f1822.h: 2267: unsigned DACR0 :1;
+[; ;pic12f1822.h: 2268: unsigned DACR1 :1;
+[; ;pic12f1822.h: 2269: unsigned DACR2 :1;
+[; ;pic12f1822.h: 2270: unsigned DACR3 :1;
+[; ;pic12f1822.h: 2271: unsigned DACR4 :1;
+[; ;pic12f1822.h: 2272: };
+[; ;pic12f1822.h: 2273: struct {
+[; ;pic12f1822.h: 2274: unsigned DACR :5;
+[; ;pic12f1822.h: 2275: };
+[; ;pic12f1822.h: 2276: } DACCON1bits_t;
+[; ;pic12f1822.h: 2277: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1822.h: 2311: extern volatile unsigned char SRCON0 @ 0x11A;
+"2313
+[; ;pic12f1822.h: 2313: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1822.h: 2316: typedef union {
+[; ;pic12f1822.h: 2317: struct {
+[; ;pic12f1822.h: 2318: unsigned SRPR :1;
+[; ;pic12f1822.h: 2319: unsigned SRPS :1;
+[; ;pic12f1822.h: 2320: unsigned SRNQEN :1;
+[; ;pic12f1822.h: 2321: unsigned SRQEN :1;
+[; ;pic12f1822.h: 2322: unsigned SRCLK0 :1;
+[; ;pic12f1822.h: 2323: unsigned SRCLK1 :1;
+[; ;pic12f1822.h: 2324: unsigned SRCLK2 :1;
+[; ;pic12f1822.h: 2325: unsigned SRLEN :1;
+[; ;pic12f1822.h: 2326: };
+[; ;pic12f1822.h: 2327: struct {
+[; ;pic12f1822.h: 2328: unsigned :4;
+[; ;pic12f1822.h: 2329: unsigned SRCLK :3;
+[; ;pic12f1822.h: 2330: };
+[; ;pic12f1822.h: 2331: } SRCON0bits_t;
+[; ;pic12f1822.h: 2332: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1822.h: 2381: extern volatile unsigned char SRCON1 @ 0x11B;
+"2383
+[; ;pic12f1822.h: 2383: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1822.h: 2386: typedef union {
+[; ;pic12f1822.h: 2387: struct {
+[; ;pic12f1822.h: 2388: unsigned SRRC1E :1;
+[; ;pic12f1822.h: 2389: unsigned :1;
+[; ;pic12f1822.h: 2390: unsigned SRRCKE :1;
+[; ;pic12f1822.h: 2391: unsigned SRRPE :1;
+[; ;pic12f1822.h: 2392: unsigned SRSC1E :1;
+[; ;pic12f1822.h: 2393: unsigned :1;
+[; ;pic12f1822.h: 2394: unsigned SRSCKE :1;
+[; ;pic12f1822.h: 2395: unsigned SRSPE :1;
+[; ;pic12f1822.h: 2396: };
+[; ;pic12f1822.h: 2397: } SRCON1bits_t;
+[; ;pic12f1822.h: 2398: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1822.h: 2432: extern volatile unsigned char APFCON @ 0x11D;
+"2434
+[; ;pic12f1822.h: 2434: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1822.h: 2437: extern volatile unsigned char APFCON0 @ 0x11D;
+"2439
+[; ;pic12f1822.h: 2439: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1822.h: 2442: typedef union {
+[; ;pic12f1822.h: 2443: struct {
+[; ;pic12f1822.h: 2444: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2445: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2446: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2447: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2448: unsigned :1;
+[; ;pic12f1822.h: 2449: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2450: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2451: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2452: };
+[; ;pic12f1822.h: 2453: struct {
+[; ;pic12f1822.h: 2454: unsigned :5;
+[; ;pic12f1822.h: 2455: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2456: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2457: };
+[; ;pic12f1822.h: 2458: } APFCONbits_t;
+[; ;pic12f1822.h: 2459: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1822.h: 2507: typedef union {
+[; ;pic12f1822.h: 2508: struct {
+[; ;pic12f1822.h: 2509: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2510: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2511: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2512: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2513: unsigned :1;
+[; ;pic12f1822.h: 2514: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2515: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2516: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2517: };
+[; ;pic12f1822.h: 2518: struct {
+[; ;pic12f1822.h: 2519: unsigned :5;
+[; ;pic12f1822.h: 2520: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2521: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2522: };
+[; ;pic12f1822.h: 2523: } APFCON0bits_t;
+[; ;pic12f1822.h: 2524: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1822.h: 2573: extern volatile unsigned char ANSELA @ 0x18C;
+"2575
+[; ;pic12f1822.h: 2575: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1822.h: 2578: typedef union {
+[; ;pic12f1822.h: 2579: struct {
+[; ;pic12f1822.h: 2580: unsigned ANSA0 :1;
+[; ;pic12f1822.h: 2581: unsigned ANSA1 :1;
+[; ;pic12f1822.h: 2582: unsigned ANSA2 :1;
+[; ;pic12f1822.h: 2583: unsigned :1;
+[; ;pic12f1822.h: 2584: unsigned ANSA4 :1;
+[; ;pic12f1822.h: 2585: };
+[; ;pic12f1822.h: 2586: struct {
+[; ;pic12f1822.h: 2587: unsigned ANSELA :5;
+[; ;pic12f1822.h: 2588: };
+[; ;pic12f1822.h: 2589: } ANSELAbits_t;
+[; ;pic12f1822.h: 2590: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1822.h: 2619: extern volatile unsigned short EEADR @ 0x191;
+"2621
+[; ;pic12f1822.h: 2621: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1822.h: 2625: extern volatile unsigned char EEADRL @ 0x191;
+"2627
+[; ;pic12f1822.h: 2627: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1822.h: 2630: typedef union {
+[; ;pic12f1822.h: 2631: struct {
+[; ;pic12f1822.h: 2632: unsigned EEADRL :8;
+[; ;pic12f1822.h: 2633: };
+[; ;pic12f1822.h: 2634: } EEADRLbits_t;
+[; ;pic12f1822.h: 2635: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1822.h: 2644: extern volatile unsigned char EEADRH @ 0x192;
+"2646
+[; ;pic12f1822.h: 2646: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1822.h: 2649: typedef union {
+[; ;pic12f1822.h: 2650: struct {
+[; ;pic12f1822.h: 2651: unsigned EEADRH :7;
+[; ;pic12f1822.h: 2652: };
+[; ;pic12f1822.h: 2653: } EEADRHbits_t;
+[; ;pic12f1822.h: 2654: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1822.h: 2663: extern volatile unsigned short EEDAT @ 0x193;
+"2665
+[; ;pic12f1822.h: 2665: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1822.h: 2669: extern volatile unsigned char EEDATL @ 0x193;
+"2671
+[; ;pic12f1822.h: 2671: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1822.h: 2674: extern volatile unsigned char EEDATA @ 0x193;
+"2676
+[; ;pic12f1822.h: 2676: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1822.h: 2679: typedef union {
+[; ;pic12f1822.h: 2680: struct {
+[; ;pic12f1822.h: 2681: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2682: };
+[; ;pic12f1822.h: 2683: } EEDATLbits_t;
+[; ;pic12f1822.h: 2684: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1822.h: 2692: typedef union {
+[; ;pic12f1822.h: 2693: struct {
+[; ;pic12f1822.h: 2694: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2695: };
+[; ;pic12f1822.h: 2696: } EEDATAbits_t;
+[; ;pic12f1822.h: 2697: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1822.h: 2706: extern volatile unsigned char EEDATH @ 0x194;
+"2708
+[; ;pic12f1822.h: 2708: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1822.h: 2711: typedef union {
+[; ;pic12f1822.h: 2712: struct {
+[; ;pic12f1822.h: 2713: unsigned EEDATH :6;
+[; ;pic12f1822.h: 2714: };
+[; ;pic12f1822.h: 2715: } EEDATHbits_t;
+[; ;pic12f1822.h: 2716: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1822.h: 2725: extern volatile unsigned char EECON1 @ 0x195;
+"2727
+[; ;pic12f1822.h: 2727: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1822.h: 2730: typedef union {
+[; ;pic12f1822.h: 2731: struct {
+[; ;pic12f1822.h: 2732: unsigned RD :1;
+[; ;pic12f1822.h: 2733: unsigned WR :1;
+[; ;pic12f1822.h: 2734: unsigned WREN :1;
+[; ;pic12f1822.h: 2735: unsigned WRERR :1;
+[; ;pic12f1822.h: 2736: unsigned FREE :1;
+[; ;pic12f1822.h: 2737: unsigned LWLO :1;
+[; ;pic12f1822.h: 2738: unsigned CFGS :1;
+[; ;pic12f1822.h: 2739: unsigned EEPGD :1;
+[; ;pic12f1822.h: 2740: };
+[; ;pic12f1822.h: 2741: } EECON1bits_t;
+[; ;pic12f1822.h: 2742: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1822.h: 2786: extern volatile unsigned char EECON2 @ 0x196;
+"2788
+[; ;pic12f1822.h: 2788: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1822.h: 2791: typedef union {
+[; ;pic12f1822.h: 2792: struct {
+[; ;pic12f1822.h: 2793: unsigned EECON2 :8;
+[; ;pic12f1822.h: 2794: };
+[; ;pic12f1822.h: 2795: } EECON2bits_t;
+[; ;pic12f1822.h: 2796: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1822.h: 2805: extern volatile unsigned char RCREG @ 0x199;
+"2807
+[; ;pic12f1822.h: 2807: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1822.h: 2810: typedef union {
+[; ;pic12f1822.h: 2811: struct {
+[; ;pic12f1822.h: 2812: unsigned RCREG :8;
+[; ;pic12f1822.h: 2813: };
+[; ;pic12f1822.h: 2814: } RCREGbits_t;
+[; ;pic12f1822.h: 2815: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1822.h: 2824: extern volatile unsigned char TXREG @ 0x19A;
+"2826
+[; ;pic12f1822.h: 2826: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1822.h: 2829: typedef union {
+[; ;pic12f1822.h: 2830: struct {
+[; ;pic12f1822.h: 2831: unsigned TXREG :8;
+[; ;pic12f1822.h: 2832: };
+[; ;pic12f1822.h: 2833: } TXREGbits_t;
+[; ;pic12f1822.h: 2834: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1822.h: 2843: extern volatile unsigned char SPBRGL @ 0x19B;
+"2845
+[; ;pic12f1822.h: 2845: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1822.h: 2848: extern volatile unsigned char SPBRG @ 0x19B;
+"2850
+[; ;pic12f1822.h: 2850: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1822.h: 2853: typedef union {
+[; ;pic12f1822.h: 2854: struct {
+[; ;pic12f1822.h: 2855: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2856: };
+[; ;pic12f1822.h: 2857: } SPBRGLbits_t;
+[; ;pic12f1822.h: 2858: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1822.h: 2866: typedef union {
+[; ;pic12f1822.h: 2867: struct {
+[; ;pic12f1822.h: 2868: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2869: };
+[; ;pic12f1822.h: 2870: } SPBRGbits_t;
+[; ;pic12f1822.h: 2871: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1822.h: 2880: extern volatile unsigned char SPBRGH @ 0x19C;
+"2882
+[; ;pic12f1822.h: 2882: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1822.h: 2885: typedef union {
+[; ;pic12f1822.h: 2886: struct {
+[; ;pic12f1822.h: 2887: unsigned SPBRGH :8;
+[; ;pic12f1822.h: 2888: };
+[; ;pic12f1822.h: 2889: } SPBRGHbits_t;
+[; ;pic12f1822.h: 2890: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1822.h: 2899: extern volatile unsigned char RCSTA @ 0x19D;
+"2901
+[; ;pic12f1822.h: 2901: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1822.h: 2904: typedef union {
+[; ;pic12f1822.h: 2905: struct {
+[; ;pic12f1822.h: 2906: unsigned RX9D :1;
+[; ;pic12f1822.h: 2907: unsigned OERR :1;
+[; ;pic12f1822.h: 2908: unsigned FERR :1;
+[; ;pic12f1822.h: 2909: unsigned ADDEN :1;
+[; ;pic12f1822.h: 2910: unsigned CREN :1;
+[; ;pic12f1822.h: 2911: unsigned SREN :1;
+[; ;pic12f1822.h: 2912: unsigned RX9 :1;
+[; ;pic12f1822.h: 2913: unsigned SPEN :1;
+[; ;pic12f1822.h: 2914: };
+[; ;pic12f1822.h: 2915: } RCSTAbits_t;
+[; ;pic12f1822.h: 2916: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1822.h: 2960: extern volatile unsigned char TXSTA @ 0x19E;
+"2962
+[; ;pic12f1822.h: 2962: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1822.h: 2965: typedef union {
+[; ;pic12f1822.h: 2966: struct {
+[; ;pic12f1822.h: 2967: unsigned TX9D :1;
+[; ;pic12f1822.h: 2968: unsigned TRMT :1;
+[; ;pic12f1822.h: 2969: unsigned BRGH :1;
+[; ;pic12f1822.h: 2970: unsigned SENDB :1;
+[; ;pic12f1822.h: 2971: unsigned SYNC :1;
+[; ;pic12f1822.h: 2972: unsigned TXEN :1;
+[; ;pic12f1822.h: 2973: unsigned TX9 :1;
+[; ;pic12f1822.h: 2974: unsigned CSRC :1;
+[; ;pic12f1822.h: 2975: };
+[; ;pic12f1822.h: 2976: } TXSTAbits_t;
+[; ;pic12f1822.h: 2977: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1822.h: 3021: extern volatile unsigned char BAUDCON @ 0x19F;
+"3023
+[; ;pic12f1822.h: 3023: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1822.h: 3026: typedef union {
+[; ;pic12f1822.h: 3027: struct {
+[; ;pic12f1822.h: 3028: unsigned ABDEN :1;
+[; ;pic12f1822.h: 3029: unsigned WUE :1;
+[; ;pic12f1822.h: 3030: unsigned :1;
+[; ;pic12f1822.h: 3031: unsigned BRG16 :1;
+[; ;pic12f1822.h: 3032: unsigned SCKP :1;
+[; ;pic12f1822.h: 3033: unsigned :1;
+[; ;pic12f1822.h: 3034: unsigned RCIDL :1;
+[; ;pic12f1822.h: 3035: unsigned ABDOVF :1;
+[; ;pic12f1822.h: 3036: };
+[; ;pic12f1822.h: 3037: } BAUDCONbits_t;
+[; ;pic12f1822.h: 3038: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1822.h: 3072: extern volatile unsigned char WPUA @ 0x20C;
+"3074
+[; ;pic12f1822.h: 3074: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1822.h: 3077: typedef union {
+[; ;pic12f1822.h: 3078: struct {
+[; ;pic12f1822.h: 3079: unsigned WPUA0 :1;
+[; ;pic12f1822.h: 3080: unsigned WPUA1 :1;
+[; ;pic12f1822.h: 3081: unsigned WPUA2 :1;
+[; ;pic12f1822.h: 3082: unsigned WPUA3 :1;
+[; ;pic12f1822.h: 3083: unsigned WPUA4 :1;
+[; ;pic12f1822.h: 3084: unsigned WPUA5 :1;
+[; ;pic12f1822.h: 3085: };
+[; ;pic12f1822.h: 3086: struct {
+[; ;pic12f1822.h: 3087: unsigned WPUA :6;
+[; ;pic12f1822.h: 3088: };
+[; ;pic12f1822.h: 3089: } WPUAbits_t;
+[; ;pic12f1822.h: 3090: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1822.h: 3129: extern volatile unsigned char SSP1BUF @ 0x211;
+"3131
+[; ;pic12f1822.h: 3131: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3134: extern volatile unsigned char SSPBUF @ 0x211;
+"3136
+[; ;pic12f1822.h: 3136: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3139: typedef union {
+[; ;pic12f1822.h: 3140: struct {
+[; ;pic12f1822.h: 3141: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3142: };
+[; ;pic12f1822.h: 3143: } SSP1BUFbits_t;
+[; ;pic12f1822.h: 3144: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1822.h: 3152: typedef union {
+[; ;pic12f1822.h: 3153: struct {
+[; ;pic12f1822.h: 3154: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3155: };
+[; ;pic12f1822.h: 3156: } SSPBUFbits_t;
+[; ;pic12f1822.h: 3157: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1822.h: 3166: extern volatile unsigned char SSP1ADD @ 0x212;
+"3168
+[; ;pic12f1822.h: 3168: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3171: extern volatile unsigned char SSPADD @ 0x212;
+"3173
+[; ;pic12f1822.h: 3173: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3176: typedef union {
+[; ;pic12f1822.h: 3177: struct {
+[; ;pic12f1822.h: 3178: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3179: };
+[; ;pic12f1822.h: 3180: } SSP1ADDbits_t;
+[; ;pic12f1822.h: 3181: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1822.h: 3189: typedef union {
+[; ;pic12f1822.h: 3190: struct {
+[; ;pic12f1822.h: 3191: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3192: };
+[; ;pic12f1822.h: 3193: } SSPADDbits_t;
+[; ;pic12f1822.h: 3194: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1822.h: 3203: extern volatile unsigned char SSP1MSK @ 0x213;
+"3205
+[; ;pic12f1822.h: 3205: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3208: extern volatile unsigned char SSPMSK @ 0x213;
+"3210
+[; ;pic12f1822.h: 3210: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3213: typedef union {
+[; ;pic12f1822.h: 3214: struct {
+[; ;pic12f1822.h: 3215: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3216: };
+[; ;pic12f1822.h: 3217: } SSP1MSKbits_t;
+[; ;pic12f1822.h: 3218: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1822.h: 3226: typedef union {
+[; ;pic12f1822.h: 3227: struct {
+[; ;pic12f1822.h: 3228: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3229: };
+[; ;pic12f1822.h: 3230: } SSPMSKbits_t;
+[; ;pic12f1822.h: 3231: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1822.h: 3240: extern volatile unsigned char SSP1STAT @ 0x214;
+"3242
+[; ;pic12f1822.h: 3242: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3245: extern volatile unsigned char SSPSTAT @ 0x214;
+"3247
+[; ;pic12f1822.h: 3247: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3250: typedef union {
+[; ;pic12f1822.h: 3251: struct {
+[; ;pic12f1822.h: 3252: unsigned BF :1;
+[; ;pic12f1822.h: 3253: unsigned UA :1;
+[; ;pic12f1822.h: 3254: unsigned R_nW :1;
+[; ;pic12f1822.h: 3255: unsigned S :1;
+[; ;pic12f1822.h: 3256: unsigned P :1;
+[; ;pic12f1822.h: 3257: unsigned D_nA :1;
+[; ;pic12f1822.h: 3258: unsigned CKE :1;
+[; ;pic12f1822.h: 3259: unsigned SMP :1;
+[; ;pic12f1822.h: 3260: };
+[; ;pic12f1822.h: 3261: } SSP1STATbits_t;
+[; ;pic12f1822.h: 3262: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1822.h: 3305: typedef union {
+[; ;pic12f1822.h: 3306: struct {
+[; ;pic12f1822.h: 3307: unsigned BF :1;
+[; ;pic12f1822.h: 3308: unsigned UA :1;
+[; ;pic12f1822.h: 3309: unsigned R_nW :1;
+[; ;pic12f1822.h: 3310: unsigned S :1;
+[; ;pic12f1822.h: 3311: unsigned P :1;
+[; ;pic12f1822.h: 3312: unsigned D_nA :1;
+[; ;pic12f1822.h: 3313: unsigned CKE :1;
+[; ;pic12f1822.h: 3314: unsigned SMP :1;
+[; ;pic12f1822.h: 3315: };
+[; ;pic12f1822.h: 3316: } SSPSTATbits_t;
+[; ;pic12f1822.h: 3317: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1822.h: 3361: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3363
+[; ;pic12f1822.h: 3363: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3366: extern volatile unsigned char SSPCON1 @ 0x215;
+"3368
+[; ;pic12f1822.h: 3368: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3370: extern volatile unsigned char SSPCON @ 0x215;
+"3372
+[; ;pic12f1822.h: 3372: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1822.h: 3375: typedef union {
+[; ;pic12f1822.h: 3376: struct {
+[; ;pic12f1822.h: 3377: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3378: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3379: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3380: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3381: unsigned CKP :1;
+[; ;pic12f1822.h: 3382: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3383: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3384: unsigned WCOL :1;
+[; ;pic12f1822.h: 3385: };
+[; ;pic12f1822.h: 3386: struct {
+[; ;pic12f1822.h: 3387: unsigned SSPM :4;
+[; ;pic12f1822.h: 3388: };
+[; ;pic12f1822.h: 3389: } SSP1CON1bits_t;
+[; ;pic12f1822.h: 3390: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1822.h: 3438: typedef union {
+[; ;pic12f1822.h: 3439: struct {
+[; ;pic12f1822.h: 3440: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3441: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3442: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3443: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3444: unsigned CKP :1;
+[; ;pic12f1822.h: 3445: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3446: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3447: unsigned WCOL :1;
+[; ;pic12f1822.h: 3448: };
+[; ;pic12f1822.h: 3449: struct {
+[; ;pic12f1822.h: 3450: unsigned SSPM :4;
+[; ;pic12f1822.h: 3451: };
+[; ;pic12f1822.h: 3452: } SSPCON1bits_t;
+[; ;pic12f1822.h: 3453: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1822.h: 3500: typedef union {
+[; ;pic12f1822.h: 3501: struct {
+[; ;pic12f1822.h: 3502: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3503: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3504: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3505: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3506: unsigned CKP :1;
+[; ;pic12f1822.h: 3507: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3508: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3509: unsigned WCOL :1;
+[; ;pic12f1822.h: 3510: };
+[; ;pic12f1822.h: 3511: struct {
+[; ;pic12f1822.h: 3512: unsigned SSPM :4;
+[; ;pic12f1822.h: 3513: };
+[; ;pic12f1822.h: 3514: } SSPCONbits_t;
+[; ;pic12f1822.h: 3515: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1822.h: 3564: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3566
+[; ;pic12f1822.h: 3566: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3569: extern volatile unsigned char SSPCON2 @ 0x216;
+"3571
+[; ;pic12f1822.h: 3571: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3574: typedef union {
+[; ;pic12f1822.h: 3575: struct {
+[; ;pic12f1822.h: 3576: unsigned SEN :1;
+[; ;pic12f1822.h: 3577: unsigned RSEN :1;
+[; ;pic12f1822.h: 3578: unsigned PEN :1;
+[; ;pic12f1822.h: 3579: unsigned RCEN :1;
+[; ;pic12f1822.h: 3580: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3581: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3582: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3583: unsigned GCEN :1;
+[; ;pic12f1822.h: 3584: };
+[; ;pic12f1822.h: 3585: } SSP1CON2bits_t;
+[; ;pic12f1822.h: 3586: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1822.h: 3629: typedef union {
+[; ;pic12f1822.h: 3630: struct {
+[; ;pic12f1822.h: 3631: unsigned SEN :1;
+[; ;pic12f1822.h: 3632: unsigned RSEN :1;
+[; ;pic12f1822.h: 3633: unsigned PEN :1;
+[; ;pic12f1822.h: 3634: unsigned RCEN :1;
+[; ;pic12f1822.h: 3635: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3636: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3637: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3638: unsigned GCEN :1;
+[; ;pic12f1822.h: 3639: };
+[; ;pic12f1822.h: 3640: } SSPCON2bits_t;
+[; ;pic12f1822.h: 3641: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1822.h: 3685: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3687
+[; ;pic12f1822.h: 3687: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3690: extern volatile unsigned char SSPCON3 @ 0x217;
+"3692
+[; ;pic12f1822.h: 3692: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3695: typedef union {
+[; ;pic12f1822.h: 3696: struct {
+[; ;pic12f1822.h: 3697: unsigned DHEN :1;
+[; ;pic12f1822.h: 3698: unsigned AHEN :1;
+[; ;pic12f1822.h: 3699: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3700: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3701: unsigned BOEN :1;
+[; ;pic12f1822.h: 3702: unsigned SCIE :1;
+[; ;pic12f1822.h: 3703: unsigned PCIE :1;
+[; ;pic12f1822.h: 3704: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3705: };
+[; ;pic12f1822.h: 3706: } SSP1CON3bits_t;
+[; ;pic12f1822.h: 3707: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1822.h: 3750: typedef union {
+[; ;pic12f1822.h: 3751: struct {
+[; ;pic12f1822.h: 3752: unsigned DHEN :1;
+[; ;pic12f1822.h: 3753: unsigned AHEN :1;
+[; ;pic12f1822.h: 3754: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3755: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3756: unsigned BOEN :1;
+[; ;pic12f1822.h: 3757: unsigned SCIE :1;
+[; ;pic12f1822.h: 3758: unsigned PCIE :1;
+[; ;pic12f1822.h: 3759: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3760: };
+[; ;pic12f1822.h: 3761: } SSPCON3bits_t;
+[; ;pic12f1822.h: 3762: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1822.h: 3806: extern volatile unsigned char CCPR1L @ 0x291;
+"3808
+[; ;pic12f1822.h: 3808: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1822.h: 3811: typedef union {
+[; ;pic12f1822.h: 3812: struct {
+[; ;pic12f1822.h: 3813: unsigned CCPR1L :8;
+[; ;pic12f1822.h: 3814: };
+[; ;pic12f1822.h: 3815: } CCPR1Lbits_t;
+[; ;pic12f1822.h: 3816: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1822.h: 3825: extern volatile unsigned char CCPR1H @ 0x292;
+"3827
+[; ;pic12f1822.h: 3827: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1822.h: 3830: typedef union {
+[; ;pic12f1822.h: 3831: struct {
+[; ;pic12f1822.h: 3832: unsigned CCPR1H :8;
+[; ;pic12f1822.h: 3833: };
+[; ;pic12f1822.h: 3834: } CCPR1Hbits_t;
+[; ;pic12f1822.h: 3835: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1822.h: 3844: extern volatile unsigned char CCP1CON @ 0x293;
+"3846
+[; ;pic12f1822.h: 3846: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1822.h: 3849: typedef union {
+[; ;pic12f1822.h: 3850: struct {
+[; ;pic12f1822.h: 3851: unsigned CCP1M0 :1;
+[; ;pic12f1822.h: 3852: unsigned CCP1M1 :1;
+[; ;pic12f1822.h: 3853: unsigned CCP1M2 :1;
+[; ;pic12f1822.h: 3854: unsigned CCP1M3 :1;
+[; ;pic12f1822.h: 3855: unsigned DC1B0 :1;
+[; ;pic12f1822.h: 3856: unsigned DC1B1 :1;
+[; ;pic12f1822.h: 3857: unsigned P1M0 :1;
+[; ;pic12f1822.h: 3858: unsigned P1M1 :1;
+[; ;pic12f1822.h: 3859: };
+[; ;pic12f1822.h: 3860: struct {
+[; ;pic12f1822.h: 3861: unsigned CCP1M :4;
+[; ;pic12f1822.h: 3862: unsigned DC1B :2;
+[; ;pic12f1822.h: 3863: unsigned P1M :2;
+[; ;pic12f1822.h: 3864: };
+[; ;pic12f1822.h: 3865: } CCP1CONbits_t;
+[; ;pic12f1822.h: 3866: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1822.h: 3925: extern volatile unsigned char PWM1CON @ 0x294;
+"3927
+[; ;pic12f1822.h: 3927: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1822.h: 3930: typedef union {
+[; ;pic12f1822.h: 3931: struct {
+[; ;pic12f1822.h: 3932: unsigned P1DC0 :1;
+[; ;pic12f1822.h: 3933: unsigned P1DC1 :1;
+[; ;pic12f1822.h: 3934: unsigned P1DC2 :1;
+[; ;pic12f1822.h: 3935: unsigned P1DC3 :1;
+[; ;pic12f1822.h: 3936: unsigned P1DC4 :1;
+[; ;pic12f1822.h: 3937: unsigned P1DC5 :1;
+[; ;pic12f1822.h: 3938: unsigned P1DC6 :1;
+[; ;pic12f1822.h: 3939: unsigned P1RSEN :1;
+[; ;pic12f1822.h: 3940: };
+[; ;pic12f1822.h: 3941: struct {
+[; ;pic12f1822.h: 3942: unsigned P1DC :7;
+[; ;pic12f1822.h: 3943: };
+[; ;pic12f1822.h: 3944: } PWM1CONbits_t;
+[; ;pic12f1822.h: 3945: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1822.h: 3994: extern volatile unsigned char CCP1AS @ 0x295;
+"3996
+[; ;pic12f1822.h: 3996: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 3999: extern volatile unsigned char ECCP1AS @ 0x295;
+"4001
+[; ;pic12f1822.h: 4001: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 4004: typedef union {
+[; ;pic12f1822.h: 4005: struct {
+[; ;pic12f1822.h: 4006: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4007: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4008: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4009: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4010: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4011: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4012: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4013: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4014: };
+[; ;pic12f1822.h: 4015: struct {
+[; ;pic12f1822.h: 4016: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4017: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4018: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4019: };
+[; ;pic12f1822.h: 4020: } CCP1ASbits_t;
+[; ;pic12f1822.h: 4021: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4079: typedef union {
+[; ;pic12f1822.h: 4080: struct {
+[; ;pic12f1822.h: 4081: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4082: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4083: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4084: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4085: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4086: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4087: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4088: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4089: };
+[; ;pic12f1822.h: 4090: struct {
+[; ;pic12f1822.h: 4091: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4092: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4093: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4094: };
+[; ;pic12f1822.h: 4095: } ECCP1ASbits_t;
+[; ;pic12f1822.h: 4096: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4155: extern volatile unsigned char PSTR1CON @ 0x296;
+"4157
+[; ;pic12f1822.h: 4157: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1822.h: 4160: typedef union {
+[; ;pic12f1822.h: 4161: struct {
+[; ;pic12f1822.h: 4162: unsigned STR1A :1;
+[; ;pic12f1822.h: 4163: unsigned STR1B :1;
+[; ;pic12f1822.h: 4164: unsigned STR1C :1;
+[; ;pic12f1822.h: 4165: unsigned STR1D :1;
+[; ;pic12f1822.h: 4166: unsigned STR1SYNC :1;
+[; ;pic12f1822.h: 4167: };
+[; ;pic12f1822.h: 4168: } PSTR1CONbits_t;
+[; ;pic12f1822.h: 4169: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1822.h: 4198: extern volatile unsigned char IOCAP @ 0x391;
+"4200
+[; ;pic12f1822.h: 4200: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1822.h: 4203: typedef union {
+[; ;pic12f1822.h: 4204: struct {
+[; ;pic12f1822.h: 4205: unsigned IOCAP0 :1;
+[; ;pic12f1822.h: 4206: unsigned IOCAP1 :1;
+[; ;pic12f1822.h: 4207: unsigned IOCAP2 :1;
+[; ;pic12f1822.h: 4208: unsigned IOCAP3 :1;
+[; ;pic12f1822.h: 4209: unsigned IOCAP4 :1;
+[; ;pic12f1822.h: 4210: unsigned IOCAP5 :1;
+[; ;pic12f1822.h: 4211: };
+[; ;pic12f1822.h: 4212: struct {
+[; ;pic12f1822.h: 4213: unsigned IOCAP :6;
+[; ;pic12f1822.h: 4214: };
+[; ;pic12f1822.h: 4215: } IOCAPbits_t;
+[; ;pic12f1822.h: 4216: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1822.h: 4255: extern volatile unsigned char IOCAN @ 0x392;
+"4257
+[; ;pic12f1822.h: 4257: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1822.h: 4260: typedef union {
+[; ;pic12f1822.h: 4261: struct {
+[; ;pic12f1822.h: 4262: unsigned IOCAN0 :1;
+[; ;pic12f1822.h: 4263: unsigned IOCAN1 :1;
+[; ;pic12f1822.h: 4264: unsigned IOCAN2 :1;
+[; ;pic12f1822.h: 4265: unsigned IOCAN3 :1;
+[; ;pic12f1822.h: 4266: unsigned IOCAN4 :1;
+[; ;pic12f1822.h: 4267: unsigned IOCAN5 :1;
+[; ;pic12f1822.h: 4268: };
+[; ;pic12f1822.h: 4269: struct {
+[; ;pic12f1822.h: 4270: unsigned IOCAN :6;
+[; ;pic12f1822.h: 4271: };
+[; ;pic12f1822.h: 4272: } IOCANbits_t;
+[; ;pic12f1822.h: 4273: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1822.h: 4312: extern volatile unsigned char IOCAF @ 0x393;
+"4314
+[; ;pic12f1822.h: 4314: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1822.h: 4317: typedef union {
+[; ;pic12f1822.h: 4318: struct {
+[; ;pic12f1822.h: 4319: unsigned IOCAF0 :1;
+[; ;pic12f1822.h: 4320: unsigned IOCAF1 :1;
+[; ;pic12f1822.h: 4321: unsigned IOCAF2 :1;
+[; ;pic12f1822.h: 4322: unsigned IOCAF3 :1;
+[; ;pic12f1822.h: 4323: unsigned IOCAF4 :1;
+[; ;pic12f1822.h: 4324: unsigned IOCAF5 :1;
+[; ;pic12f1822.h: 4325: };
+[; ;pic12f1822.h: 4326: struct {
+[; ;pic12f1822.h: 4327: unsigned IOCAF :6;
+[; ;pic12f1822.h: 4328: };
+[; ;pic12f1822.h: 4329: } IOCAFbits_t;
+[; ;pic12f1822.h: 4330: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1822.h: 4369: extern volatile unsigned char CLKRCON @ 0x39A;
+"4371
+[; ;pic12f1822.h: 4371: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1822.h: 4374: typedef union {
+[; ;pic12f1822.h: 4375: struct {
+[; ;pic12f1822.h: 4376: unsigned CLKRDIV0 :1;
+[; ;pic12f1822.h: 4377: unsigned CLKRDIV1 :1;
+[; ;pic12f1822.h: 4378: unsigned CLKRDIV2 :1;
+[; ;pic12f1822.h: 4379: unsigned CLKRDC0 :1;
+[; ;pic12f1822.h: 4380: unsigned CLKRDC1 :1;
+[; ;pic12f1822.h: 4381: unsigned CLKRSLR :1;
+[; ;pic12f1822.h: 4382: unsigned CLKROE :1;
+[; ;pic12f1822.h: 4383: unsigned CLKREN :1;
+[; ;pic12f1822.h: 4384: };
+[; ;pic12f1822.h: 4385: struct {
+[; ;pic12f1822.h: 4386: unsigned CLKRDIV :3;
+[; ;pic12f1822.h: 4387: unsigned CLKRDC :2;
+[; ;pic12f1822.h: 4388: };
+[; ;pic12f1822.h: 4389: } CLKRCONbits_t;
+[; ;pic12f1822.h: 4390: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1822.h: 4444: extern volatile unsigned char MDCON @ 0x39C;
+"4446
+[; ;pic12f1822.h: 4446: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1822.h: 4449: typedef union {
+[; ;pic12f1822.h: 4450: struct {
+[; ;pic12f1822.h: 4451: unsigned MDBIT :1;
+[; ;pic12f1822.h: 4452: unsigned :2;
+[; ;pic12f1822.h: 4453: unsigned MDOUT :1;
+[; ;pic12f1822.h: 4454: unsigned MDOPOL :1;
+[; ;pic12f1822.h: 4455: unsigned MDSLR :1;
+[; ;pic12f1822.h: 4456: unsigned MDOE :1;
+[; ;pic12f1822.h: 4457: unsigned MDEN :1;
+[; ;pic12f1822.h: 4458: };
+[; ;pic12f1822.h: 4459: } MDCONbits_t;
+[; ;pic12f1822.h: 4460: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1822.h: 4494: extern volatile unsigned char MDSRC @ 0x39D;
+"4496
+[; ;pic12f1822.h: 4496: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1822.h: 4499: typedef union {
+[; ;pic12f1822.h: 4500: struct {
+[; ;pic12f1822.h: 4501: unsigned MDMS0 :1;
+[; ;pic12f1822.h: 4502: unsigned MDMS1 :1;
+[; ;pic12f1822.h: 4503: unsigned MDMS2 :1;
+[; ;pic12f1822.h: 4504: unsigned MDMS3 :1;
+[; ;pic12f1822.h: 4505: unsigned :3;
+[; ;pic12f1822.h: 4506: unsigned MDMSODIS :1;
+[; ;pic12f1822.h: 4507: };
+[; ;pic12f1822.h: 4508: struct {
+[; ;pic12f1822.h: 4509: unsigned MDMS :4;
+[; ;pic12f1822.h: 4510: };
+[; ;pic12f1822.h: 4511: } MDSRCbits_t;
+[; ;pic12f1822.h: 4512: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1822.h: 4546: extern volatile unsigned char MDCARL @ 0x39E;
+"4548
+[; ;pic12f1822.h: 4548: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1822.h: 4551: typedef union {
+[; ;pic12f1822.h: 4552: struct {
+[; ;pic12f1822.h: 4553: unsigned MDCL0 :1;
+[; ;pic12f1822.h: 4554: unsigned MDCL1 :1;
+[; ;pic12f1822.h: 4555: unsigned MDCL2 :1;
+[; ;pic12f1822.h: 4556: unsigned MDCL3 :1;
+[; ;pic12f1822.h: 4557: unsigned :1;
+[; ;pic12f1822.h: 4558: unsigned MDCLSYNC :1;
+[; ;pic12f1822.h: 4559: unsigned MDCLPOL :1;
+[; ;pic12f1822.h: 4560: unsigned MDCLODIS :1;
+[; ;pic12f1822.h: 4561: };
+[; ;pic12f1822.h: 4562: struct {
+[; ;pic12f1822.h: 4563: unsigned MDCL :4;
+[; ;pic12f1822.h: 4564: };
+[; ;pic12f1822.h: 4565: } MDCARLbits_t;
+[; ;pic12f1822.h: 4566: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1822.h: 4610: extern volatile unsigned char MDCARH @ 0x39F;
+"4612
+[; ;pic12f1822.h: 4612: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1822.h: 4615: typedef union {
+[; ;pic12f1822.h: 4616: struct {
+[; ;pic12f1822.h: 4617: unsigned MDCH0 :1;
+[; ;pic12f1822.h: 4618: unsigned MDCH1 :1;
+[; ;pic12f1822.h: 4619: unsigned MDCH2 :1;
+[; ;pic12f1822.h: 4620: unsigned MDCH3 :1;
+[; ;pic12f1822.h: 4621: unsigned :1;
+[; ;pic12f1822.h: 4622: unsigned MDCHSYNC :1;
+[; ;pic12f1822.h: 4623: unsigned MDCHPOL :1;
+[; ;pic12f1822.h: 4624: unsigned MDCHODIS :1;
+[; ;pic12f1822.h: 4625: };
+[; ;pic12f1822.h: 4626: struct {
+[; ;pic12f1822.h: 4627: unsigned MDCH :4;
+[; ;pic12f1822.h: 4628: };
+[; ;pic12f1822.h: 4629: } MDCARHbits_t;
+[; ;pic12f1822.h: 4630: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1822.h: 4674: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4676
+[; ;pic12f1822.h: 4676: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1822.h: 4679: typedef union {
+[; ;pic12f1822.h: 4680: struct {
+[; ;pic12f1822.h: 4681: unsigned C_SHAD :1;
+[; ;pic12f1822.h: 4682: unsigned DC_SHAD :1;
+[; ;pic12f1822.h: 4683: unsigned Z_SHAD :1;
+[; ;pic12f1822.h: 4684: };
+[; ;pic12f1822.h: 4685: } STATUS_SHADbits_t;
+[; ;pic12f1822.h: 4686: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1822.h: 4705: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4707
+[; ;pic12f1822.h: 4707: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1822.h: 4710: typedef union {
+[; ;pic12f1822.h: 4711: struct {
+[; ;pic12f1822.h: 4712: unsigned WREG_SHAD :8;
+[; ;pic12f1822.h: 4713: };
+[; ;pic12f1822.h: 4714: } WREG_SHADbits_t;
+[; ;pic12f1822.h: 4715: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1822.h: 4724: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4726
+[; ;pic12f1822.h: 4726: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1822.h: 4729: typedef union {
+[; ;pic12f1822.h: 4730: struct {
+[; ;pic12f1822.h: 4731: unsigned BSR_SHAD :5;
+[; ;pic12f1822.h: 4732: };
+[; ;pic12f1822.h: 4733: } BSR_SHADbits_t;
+[; ;pic12f1822.h: 4734: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1822.h: 4743: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4745
+[; ;pic12f1822.h: 4745: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1822.h: 4748: typedef union {
+[; ;pic12f1822.h: 4749: struct {
+[; ;pic12f1822.h: 4750: unsigned PCLATH_SHAD :7;
+[; ;pic12f1822.h: 4751: };
+[; ;pic12f1822.h: 4752: } PCLATH_SHADbits_t;
+[; ;pic12f1822.h: 4753: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1822.h: 4762: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4764
+[; ;pic12f1822.h: 4764: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1822.h: 4767: typedef union {
+[; ;pic12f1822.h: 4768: struct {
+[; ;pic12f1822.h: 4769: unsigned FSR0L_SHAD :8;
+[; ;pic12f1822.h: 4770: };
+[; ;pic12f1822.h: 4771: } FSR0L_SHADbits_t;
+[; ;pic12f1822.h: 4772: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1822.h: 4781: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4783
+[; ;pic12f1822.h: 4783: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1822.h: 4786: typedef union {
+[; ;pic12f1822.h: 4787: struct {
+[; ;pic12f1822.h: 4788: unsigned FSR0H_SHAD :8;
+[; ;pic12f1822.h: 4789: };
+[; ;pic12f1822.h: 4790: } FSR0H_SHADbits_t;
+[; ;pic12f1822.h: 4791: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1822.h: 4800: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4802
+[; ;pic12f1822.h: 4802: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1822.h: 4805: typedef union {
+[; ;pic12f1822.h: 4806: struct {
+[; ;pic12f1822.h: 4807: unsigned FSR1L_SHAD :8;
+[; ;pic12f1822.h: 4808: };
+[; ;pic12f1822.h: 4809: } FSR1L_SHADbits_t;
+[; ;pic12f1822.h: 4810: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1822.h: 4819: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4821
+[; ;pic12f1822.h: 4821: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1822.h: 4824: typedef union {
+[; ;pic12f1822.h: 4825: struct {
+[; ;pic12f1822.h: 4826: unsigned FSR1H_SHAD :8;
+[; ;pic12f1822.h: 4827: };
+[; ;pic12f1822.h: 4828: } FSR1H_SHADbits_t;
+[; ;pic12f1822.h: 4829: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1822.h: 4838: extern volatile unsigned char STKPTR @ 0xFED;
+"4840
+[; ;pic12f1822.h: 4840: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1822.h: 4843: typedef union {
+[; ;pic12f1822.h: 4844: struct {
+[; ;pic12f1822.h: 4845: unsigned STKPTR :5;
+[; ;pic12f1822.h: 4846: };
+[; ;pic12f1822.h: 4847: } STKPTRbits_t;
+[; ;pic12f1822.h: 4848: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1822.h: 4857: extern volatile unsigned char TOSL @ 0xFEE;
+"4859
+[; ;pic12f1822.h: 4859: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1822.h: 4862: typedef union {
+[; ;pic12f1822.h: 4863: struct {
+[; ;pic12f1822.h: 4864: unsigned TOSL :8;
+[; ;pic12f1822.h: 4865: };
+[; ;pic12f1822.h: 4866: } TOSLbits_t;
+[; ;pic12f1822.h: 4867: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1822.h: 4876: extern volatile unsigned char TOSH @ 0xFEF;
+"4878
+[; ;pic12f1822.h: 4878: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1822.h: 4881: typedef union {
+[; ;pic12f1822.h: 4882: struct {
+[; ;pic12f1822.h: 4883: unsigned TOSH :7;
+[; ;pic12f1822.h: 4884: };
+[; ;pic12f1822.h: 4885: } TOSHbits_t;
+[; ;pic12f1822.h: 4886: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1822.h: 4901: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1822.h: 4903: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1822.h: 4905: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1822.h: 4907: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1822.h: 4909: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1822.h: 4911: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1822.h: 4913: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1822.h: 4915: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1822.h: 4917: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1822.h: 4919: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1822.h: 4921: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1822.h: 4923: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1822.h: 4925: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1822.h: 4927: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 4929: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1822.h: 4931: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1822.h: 4933: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1822.h: 4935: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1822.h: 4937: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1822.h: 4939: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1822.h: 4941: extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4943: extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4945: extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 4947: extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4949: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1822.h: 4951: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1822.h: 4953: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1822.h: 4955: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1822.h: 4957: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1822.h: 4959: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1822.h: 4961: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1822.h: 4963: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1822.h: 4965: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1822.h: 4967: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1822.h: 4969: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1822.h: 4971: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1822.h: 4973: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1822.h: 4975: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1822.h: 4977: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1822.h: 4979: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1822.h: 4981: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1822.h: 4983: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1822.h: 4985: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1822.h: 4987: extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4989: extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4991: extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4993: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1822.h: 4995: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1822.h: 4997: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1822.h: 4999: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1822.h: 5001: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1822.h: 5003: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1822.h: 5005: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1822.h: 5007: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1822.h: 5009: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1822.h: 5011: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1822.h: 5013: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1822.h: 5015: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1822.h: 5017: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1822.h: 5019: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1822.h: 5021: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1822.h: 5023: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1822.h: 5025: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1822.h: 5027: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1822.h: 5029: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1822.h: 5031: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1822.h: 5033: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1822.h: 5035: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1822.h: 5037: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1822.h: 5039: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1822.h: 5041: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1822.h: 5043: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1822.h: 5045: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1822.h: 5047: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1822.h: 5049: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1822.h: 5051: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1822.h: 5053: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1822.h: 5055: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1822.h: 5057: extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5059: extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5061: extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5063: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1822.h: 5065: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1822.h: 5067: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1822.h: 5069: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1822.h: 5071: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1822.h: 5073: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1822.h: 5075: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1822.h: 5077: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1822.h: 5079: extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5081: extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5083: extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5085: extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5087: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1822.h: 5089: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1822.h: 5091: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1822.h: 5093: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1822.h: 5095: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1822.h: 5097: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1822.h: 5099: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1822.h: 5101: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1822.h: 5103: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1822.h: 5105: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1822.h: 5107: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1822.h: 5109: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1822.h: 5111: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1822.h: 5113: extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5115: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1822.h: 5117: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1822.h: 5119: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1822.h: 5121: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1822.h: 5123: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1822.h: 5125: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1822.h: 5127: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1822.h: 5129: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1822.h: 5131: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1822.h: 5133: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1822.h: 5135: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1822.h: 5137: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1822.h: 5139: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1822.h: 5141: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1822.h: 5143: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1822.h: 5145: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1822.h: 5147: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1822.h: 5149: extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5151: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1822.h: 5153: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1822.h: 5155: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1822.h: 5157: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1822.h: 5159: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1822.h: 5161: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5163: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5165: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1822.h: 5167: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1822.h: 5169: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1822.h: 5171: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1822.h: 5173: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1822.h: 5175: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1822.h: 5177: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1822.h: 5179: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1822.h: 5181: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1822.h: 5183: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1822.h: 5185: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1822.h: 5187: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1822.h: 5189: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1822.h: 5191: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1822.h: 5193: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1822.h: 5195: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1822.h: 5197: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1822.h: 5199: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1822.h: 5201: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1822.h: 5203: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1822.h: 5205: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1822.h: 5207: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1822.h: 5209: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1822.h: 5211: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1822.h: 5213: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1822.h: 5215: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1822.h: 5217: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1822.h: 5219: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1822.h: 5221: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1822.h: 5223: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1822.h: 5225: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1822.h: 5227: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1822.h: 5229: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1822.h: 5231: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1822.h: 5233: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1822.h: 5235: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1822.h: 5237: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1822.h: 5239: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1822.h: 5241: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1822.h: 5243: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1822.h: 5245: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1822.h: 5247: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1822.h: 5249: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1822.h: 5251: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1822.h: 5253: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1822.h: 5255: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1822.h: 5257: extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5259: extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5261: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1822.h: 5263: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1822.h: 5265: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1822.h: 5267: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1822.h: 5269: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1822.h: 5271: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1822.h: 5273: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1822.h: 5275: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1822.h: 5277: extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5279: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1822.h: 5281: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1822.h: 5283: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1822.h: 5285: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1822.h: 5287: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1822.h: 5289: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1822.h: 5291: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1822.h: 5293: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1822.h: 5295: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1822.h: 5297: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1822.h: 5299: extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5301: extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5303: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1822.h: 5305: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1822.h: 5307: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1822.h: 5309: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1822.h: 5311: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1822.h: 5313: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1822.h: 5315: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1822.h: 5317: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1822.h: 5319: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1822.h: 5321: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1822.h: 5323: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1822.h: 5325: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1822.h: 5327: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1822.h: 5329: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1822.h: 5331: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1822.h: 5333: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1822.h: 5335: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1822.h: 5337: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1822.h: 5339: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1822.h: 5341: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1822.h: 5343: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1822.h: 5345: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1822.h: 5347: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1822.h: 5349: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1822.h: 5351: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1822.h: 5353: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1822.h: 5355: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5357: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5359: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5361: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5363: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5365: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5367: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1822.h: 5369: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1822.h: 5371: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1822.h: 5373: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1822.h: 5375: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1822.h: 5377: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1822.h: 5379: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1822.h: 5381: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1822.h: 5383: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1822.h: 5385: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1822.h: 5387: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1822.h: 5389: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1822.h: 5391: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1822.h: 5393: extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5395: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1822.h: 5397: extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5399: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1822.h: 5401: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1822.h: 5403: extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5405: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1822.h: 5407: extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5409: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5411: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5413: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1822.h: 5415: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1822.h: 5417: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1822.h: 5419: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1822.h: 5421: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1822.h: 5423: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1822.h: 5425: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1822.h: 5427: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1822.h: 5429: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1822.h: 5431: extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5433: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1822.h: 5435: extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5437: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1822.h: 5439: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1822.h: 5441: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1822.h: 5443: extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5445: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1822.h: 5447: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1822.h: 5449: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1822.h: 5451: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1822.h: 5453: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1822.h: 5455: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1822.h: 5457: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1822.h: 5459: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5461: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1822.h: 5463: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1822.h: 5465: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1822.h: 5467: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1822.h: 5469: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1822.h: 5471: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1822.h: 5473: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1822.h: 5475: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1822.h: 5477: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5479: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1822.h: 5481: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1822.h: 5483: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1822.h: 5485: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1822.h: 5487: extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+[; ;pic12f1822.h: 5489: extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+[; ;pic12f1822.h: 5491: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1822.h: 5493: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1822.h: 5495: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1822.h: 5497: extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5499: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5501: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5503: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5505: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5507: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1822.h: 5509: extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5511: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1822.h: 5513: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1822.h: 5515: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5517: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5519: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1822.h: 5521: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1822.h: 5523: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1822.h: 5525: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1822.h: 5527: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1822.h: 5529: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1822.h: 5531: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1822.h: 5533: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1822.h: 5535: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1822.h: 5537: extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5539: extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5541: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1822.h: 5543: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1822.h: 5545: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1822.h: 5547: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1822.h: 5549: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1822.h: 5551: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1822.h: 5553: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5555: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5557: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5559: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5561: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1822.h: 5563: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1822.h: 5565: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1822.h: 5567: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1822.h: 5569: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1822.h: 5571: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1822.h: 5573: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1822.h: 5575: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1822.h: 5577: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1822.h: 5579: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1822.h: 5581: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1822.h: 5583: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1822.h: 5585: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1822.h: 5587: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1822.h: 5589: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1822.h: 5591: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1822.h: 5593: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1822.h: 5595: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1822.h: 5597: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1822.h: 5599: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1822.h: 5601: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1822.h: 5603: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1822.h: 5605: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1822.h: 5607: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1822.h: 5609: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1822.h: 5611: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1822.h: 5613: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1822.h: 5615: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1822.h: 5617: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1822.h: 5619: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1822.h: 5621: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1822.h: 5623: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1822.h: 5625: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1822.h: 5627: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1822.h: 5629: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1822.h: 5631: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1822.h: 5633: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1822.h: 5635: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1822.h: 5637: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1822.h: 5639: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1822.h: 5641: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1822.h: 5643: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1822.h: 5645: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1822.h: 5647: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1822.h: 5649: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1822.h: 5651: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1822.h: 5653: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1822.h: 5655: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1822.h: 5657: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1822.h: 5659: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1822.h: 5661: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1822.h: 5663: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1822.h: 5665: extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5667: extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5669: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1822.h: 5671: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1822.h: 5673: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1822.h: 5675: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1822.h: 5677: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1822.h: 5679: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1822.h: 5681: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;system.h: 31: void ConfigureOscillator(void);
+[; ;user.h: 13: void InitApp(void);
+[; ;user.h: 14: bool msg_empty(void);
+[; ;user.h: 15: void msg_write(const char *msg);
+[; ;user.h: 16: void msg_writebyte(const char msg);
+[; ;user.h: 17: void msg_sendnext(void);
+[; ;user.h: 18: void tohex(char val[3], char i);
+[; ;user.h: 19: void msg_recvnext(void);
+[; ;user.h: 20: bool msg_recvready(void);
+[; ;user.h: 21: char msg_recv(void);
+[; ;user.h: 22: void putch(char);
+[; ;user.h: 24: void int_disable(void);
+[; ;user.h: 25: void int_enable(void);
+[; ;onewire.h: 11: bool OW_reset(void);
+[; ;onewire.h: 12: void OW_write_bit(bool val);
+[; ;onewire.h: 13: bool OW_read_bit();
+[; ;onewire.h: 14: void OW_write_byte(unsigned char byte);
+[; ;onewire.h: 15: unsigned char OW_read_byte(void);
+[; ;onewire.h: 17: void OW_search_init();
+[; ;onewire.h: 18: bool OW_search(void);
+[; ;onewire.h: 19: void OW_start(void);
+[; ;onewire.h: 21: void OW_identify();
+[; ;onewire.h: 22: bool OW_parasite(void);
+[; ;onewire.h: 23: void OW_read_block(uint8_t code, uint8_t * data, uint8_t len);
+[; ;onewire.h: 24: void OW_convert();
+[; ;onewire.h: 27: inline void drive_OW_low(void);
+[; ;onewire.h: 28: inline void drive_OW_high(void);
+[; ;onewire.h: 29: inline void float_OW(void);
+[; ;onewire.h: 30: inline bool read_OW(void);
+[; ;onewire.h: 32: extern unsigned char romid[8];
+"27 onewire.h
+[v F3573 `(v ~T0 @X0 1 tf ]
+"25 onewire.c
+[v _drive_OW_low `TF3573 ~T0 @X0 1 e ]
+{
+[; ;onewire.c: 24: inline void drive_OW_low(void)
+[; ;onewire.c: 25: {
+[e :U _drive_OW_low ]
+[f ]
+[; ;onewire.c: 26: PORTAbits.RA5 = 0;
+"26
+[e = . . _PORTAbits 0 5 -> -> 0 `i `uc ]
+[; ;onewire.c: 27: TRISAbits.TRISA5 = 0;
+"27
+[e = . . _TRISAbits 0 5 -> -> 0 `i `uc ]
+[; ;onewire.c: 28: }
+"28
+[e :UE 524 ]
+}
+"28 onewire.h
+[v F3576 `(v ~T0 @X0 1 tf ]
+"31 onewire.c
+[v _drive_OW_high `TF3576 ~T0 @X0 1 e ]
+{
+[; ;onewire.c: 30: inline void drive_OW_high(void)
+[; ;onewire.c: 31: {
+[e :U _drive_OW_high ]
+[f ]
+[; ;onewire.c: 32: PORTAbits.RA5 = 1;
+"32
+[e = . . _PORTAbits 0 5 -> -> 1 `i `uc ]
+[; ;onewire.c: 33: TRISAbits.TRISA5 = 0;
+"33
+[e = . . _TRISAbits 0 5 -> -> 0 `i `uc ]
+[; ;onewire.c: 34: }
+"34
+[e :UE 525 ]
+}
+"29 onewire.h
+[v F3579 `(v ~T0 @X0 1 tf ]
+"37 onewire.c
+[v _float_OW `TF3579 ~T0 @X0 1 e ]
+{
+[; ;onewire.c: 36: inline void float_OW(void)
+[; ;onewire.c: 37: {
+[e :U _float_OW ]
+[f ]
+[; ;onewire.c: 38: TRISAbits.TRISA5 = 1;
+"38
+[e = . . _TRISAbits 0 5 -> -> 1 `i `uc ]
+[; ;onewire.c: 39: }
+"39
+[e :UE 526 ]
+}
+"30 onewire.h
+[v F3582 `(uc ~T0 @X0 1 tf ]
+"42 onewire.c
+[v _read_OW `TF3582 ~T0 @X0 1 e ]
+{
+[; ;onewire.c: 41: inline bool read_OW(void)
+[; ;onewire.c: 42: {
+[e :U _read_OW ]
+[f ]
+[; ;onewire.c: 43: TRISAbits.TRISA5 = 1;
+"43
+[e = . . _TRISAbits 0 5 -> -> 1 `i `uc ]
+[; ;onewire.c: 44: return PORTAbits.RA5;
+"44
+[e ) . . _PORTAbits 0 5 ]
+[e $UE 527  ]
+[; ;onewire.c: 45: }
+"45
+[e :UE 527 ]
+}
+"52
+[v _OW_start `(v ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 51: void OW_start(void)
+[; ;onewire.c: 52: {
+[e :U _OW_start ]
+[f ]
+[; ;onewire.c: 54: float_OW();
+"54
+[e ( _float_OW ..  ]
+[; ;onewire.c: 55: }
+"55
+[e :UE 528 ]
+}
+"59
+[v _OW_reset `(uc ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 58: bool OW_reset(void)
+[; ;onewire.c: 59: {
+[e :U _OW_reset ]
+[f ]
+"60
+[v _presence `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 60: bool presence = 0;
+[e = _presence -> -> 0 `i `uc ]
+[; ;onewire.c: 62: { PORTAbits.RA5 = 0; TRISAbits.TRISA5 = 0; };
+"62
+{
+[e = . . _PORTAbits 0 5 -> -> 0 `i `uc ]
+[e = . . _TRISAbits 0 5 -> -> 0 `i `uc ]
+}
+[; ;onewire.c: 63: _delay(250);
+"63
+[e ( __delay (1 -> -> -> 250 `i `l `ul ]
+[; ;onewire.c: 64: _delay(250);
+"64
+[e ( __delay (1 -> -> -> 250 `i `l `ul ]
+[; ;onewire.c: 65: { TRISAbits.TRISA5 = 1; };
+"65
+{
+[e = . . _TRISAbits 0 5 -> -> 1 `i `uc ]
+}
+[; ;onewire.c: 66: _delay(70);
+"66
+[e ( __delay (1 -> -> -> 70 `i `l `ul ]
+[; ;onewire.c: 67: presence = (PORTAbits.RA5);
+"67
+[e = _presence . . _PORTAbits 0 5 ]
+[; ;onewire.c: 68: _delay(215);
+"68
+[e ( __delay (1 -> -> -> 215 `i `l `ul ]
+[; ;onewire.c: 69: _delay(215);
+"69
+[e ( __delay (1 -> -> -> 215 `i `l `ul ]
+[; ;onewire.c: 71: return ! presence;
+"71
+[e ) -> -> ! != -> _presence `i -> -> -> 0 `i `uc `i `i `uc ]
+[e $UE 529  ]
+[; ;onewire.c: 72: }
+"72
+[e :UE 529 ]
+}
+"75
+[v _OW_write_bit `(v ~T0 @X0 1 ef1`uc ]
+{
+[; ;onewire.c: 74: void OW_write_bit(bool val)
+[; ;onewire.c: 75: {
+[e :U _OW_write_bit ]
+[v _val `uc ~T0 @X0 1 r1 ]
+[f ]
+[; ;onewire.c: 84: { PORTAbits.RA5 = 0; TRISAbits.TRISA5 = 0; };
+"84
+{
+[e = . . _PORTAbits 0 5 -> -> 0 `i `uc ]
+[e = . . _TRISAbits 0 5 -> -> 0 `i `uc ]
+}
+[; ;onewire.c: 85: _nop();
+"85
+[e ( __nop ..  ]
+[; ;onewire.c: 86: _nop();
+"86
+[e ( __nop ..  ]
+[; ;onewire.c: 88: if (val) { TRISAbits.TRISA5 = 1; };
+"88
+[e $ ! != -> _val `i -> -> -> 0 `i `uc `i 531  ]
+{
+[e = . . _TRISAbits 0 5 -> -> 1 `i `uc ]
+}
+[e :U 531 ]
+[; ;onewire.c: 89: _delay(60);
+"89
+[e ( __delay (1 -> -> -> 60 `i `l `ul ]
+[; ;onewire.c: 90: { TRISAbits.TRISA5 = 1; };
+"90
+{
+[e = . . _TRISAbits 0 5 -> -> 1 `i `uc ]
+}
+[; ;onewire.c: 91: _nop();
+"91
+[e ( __nop ..  ]
+[; ;onewire.c: 92: _nop();
+"92
+[e ( __nop ..  ]
+[; ;onewire.c: 94: }
+"94
+[e :UE 530 ]
+}
+"97
+[v _OW_read_bit `(uc ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 96: bool OW_read_bit()
+[; ;onewire.c: 97: {
+[e :U _OW_read_bit ]
+[f ]
+"98
+[v _val `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 98: bool val;
+[; ;onewire.c: 107: { PORTAbits.RA5 = 0; TRISAbits.TRISA5 = 0; };
+"107
+{
+[e = . . _PORTAbits 0 5 -> -> 0 `i `uc ]
+[e = . . _TRISAbits 0 5 -> -> 0 `i `uc ]
+}
+[; ;onewire.c: 109: _nop();
+"109
+[e ( __nop ..  ]
+[; ;onewire.c: 110: _nop();
+"110
+[e ( __nop ..  ]
+[; ;onewire.c: 111: _nop();
+"111
+[e ( __nop ..  ]
+[; ;onewire.c: 112: _nop();
+"112
+[e ( __nop ..  ]
+[; ;onewire.c: 113: _nop();
+"113
+[e ( __nop ..  ]
+[; ;onewire.c: 114: { TRISAbits.TRISA5 = 1; };
+"114
+{
+[e = . . _TRISAbits 0 5 -> -> 1 `i `uc ]
+}
+[; ;onewire.c: 116: _nop();
+"116
+[e ( __nop ..  ]
+[; ;onewire.c: 117: _nop();
+"117
+[e ( __nop ..  ]
+[; ;onewire.c: 118: _nop();
+"118
+[e ( __nop ..  ]
+[; ;onewire.c: 119: val = read_OW();
+"119
+[e = _val ( _read_OW ..  ]
+[; ;onewire.c: 120: _delay(50);
+"120
+[e ( __delay (1 -> -> -> 50 `i `l `ul ]
+[; ;onewire.c: 123: return val;
+"123
+[e ) _val ]
+[e $UE 532  ]
+[; ;onewire.c: 124: }
+"124
+[e :UE 532 ]
+}
+"127
+[v _OW_write_byte `(v ~T0 @X0 1 ef1`uc ]
+{
+[; ;onewire.c: 126: void OW_write_byte(unsigned char byte)
+[; ;onewire.c: 127: {
+[e :U _OW_write_byte ]
+[v _byte `uc ~T0 @X0 1 r1 ]
+[f ]
+[; ;onewire.c: 128: for (char i=8; i!=0; i--)
+"128
+{
+[v _i `uc ~T0 @X0 1 a ]
+[e = _i -> -> 8 `i `uc ]
+[e $ != -> _i `i -> 0 `i 534  ]
+[e $U 535  ]
+"129
+[e :U 534 ]
+[; ;onewire.c: 129: {
+{
+[; ;onewire.c: 130: OW_write_bit( byte & 0x01 );
+"130
+[e ( _OW_write_bit (1 -> & -> _byte `i -> 1 `i `uc ]
+[; ;onewire.c: 131: byte >>= 1;
+"131
+[e =>> _byte -> 1 `i ]
+"132
+}
+"128
+[e -- _i -> -> 1 `i `uc ]
+[e $ != -> _i `i -> 0 `i 534  ]
+[e :U 535 ]
+"132
+}
+[; ;onewire.c: 132: }
+[; ;onewire.c: 133: }
+"133
+[e :UE 533 ]
+}
+"136
+[v _OW_read_byte `(uc ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 135: unsigned char OW_read_byte(void)
+[; ;onewire.c: 136: {
+[e :U _OW_read_byte ]
+[f ]
+"137
+[v _byte `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 137: unsigned char byte = 0;
+[e = _byte -> -> 0 `i `uc ]
+[; ;onewire.c: 138: for (char i=8; i!=0; i--)
+"138
+{
+[v _i `uc ~T0 @X0 1 a ]
+[e = _i -> -> 8 `i `uc ]
+[e $ != -> _i `i -> 0 `i 538  ]
+[e $U 539  ]
+"139
+[e :U 538 ]
+[; ;onewire.c: 139: {
+{
+[; ;onewire.c: 140: byte >>= 1;
+"140
+[e =>> _byte -> 1 `i ]
+[; ;onewire.c: 141: if (OW_read_bit())
+"141
+[e $ ! != -> ( _OW_read_bit ..  `i -> -> -> 0 `i `uc `i 541  ]
+[; ;onewire.c: 142: byte |= 0x80;
+"142
+[e =| _byte -> -> 128 `i `uc ]
+[e :U 541 ]
+"144
+}
+"138
+[e -- _i -> -> 1 `i `uc ]
+[e $ != -> _i `i -> 0 `i 538  ]
+[e :U 539 ]
+"144
+}
+[; ;onewire.c: 144: }
+[; ;onewire.c: 145: return byte;
+"145
+[e ) _byte ]
+[e $UE 537  ]
+[; ;onewire.c: 146: }
+"146
+[e :UE 537 ]
+}
+"148
+[v _dscrc_table `Cuc ~T0 @X0 -> 0 `x s ]
+[i _dscrc_table
+:U ..
+"149
+-> -> 0 `i `uc
+-> -> 94 `i `uc
+-> -> 188 `i `uc
+-> -> 226 `i `uc
+-> -> 97 `i `uc
+-> -> 63 `i `uc
+-> -> 221 `i `uc
+-> -> 131 `i `uc
+-> -> 194 `i `uc
+-> -> 156 `i `uc
+-> -> 126 `i `uc
+-> -> 32 `i `uc
+-> -> 163 `i `uc
+-> -> 253 `i `uc
+-> -> 31 `i `uc
+-> -> 65 `i `uc
+"150
+-> -> 157 `i `uc
+-> -> 195 `i `uc
+-> -> 33 `i `uc
+-> -> 127 `i `uc
+-> -> 252 `i `uc
+-> -> 162 `i `uc
+-> -> 64 `i `uc
+-> -> 30 `i `uc
+-> -> 95 `i `uc
+-> -> 1 `i `uc
+-> -> 227 `i `uc
+-> -> 189 `i `uc
+-> -> 62 `i `uc
+-> -> 96 `i `uc
+-> -> 130 `i `uc
+-> -> 220 `i `uc
+"151
+-> -> 35 `i `uc
+-> -> 125 `i `uc
+-> -> 159 `i `uc
+-> -> 193 `i `uc
+-> -> 66 `i `uc
+-> -> 28 `i `uc
+-> -> 254 `i `uc
+-> -> 160 `i `uc
+-> -> 225 `i `uc
+-> -> 191 `i `uc
+-> -> 93 `i `uc
+-> -> 3 `i `uc
+-> -> 128 `i `uc
+-> -> 222 `i `uc
+-> -> 60 `i `uc
+-> -> 98 `i `uc
+"152
+-> -> 190 `i `uc
+-> -> 224 `i `uc
+-> -> 2 `i `uc
+-> -> 92 `i `uc
+-> -> 223 `i `uc
+-> -> 129 `i `uc
+-> -> 99 `i `uc
+-> -> 61 `i `uc
+-> -> 124 `i `uc
+-> -> 34 `i `uc
+-> -> 192 `i `uc
+-> -> 158 `i `uc
+-> -> 29 `i `uc
+-> -> 67 `i `uc
+-> -> 161 `i `uc
+-> -> 255 `i `uc
+"153
+-> -> 70 `i `uc
+-> -> 24 `i `uc
+-> -> 250 `i `uc
+-> -> 164 `i `uc
+-> -> 39 `i `uc
+-> -> 121 `i `uc
+-> -> 155 `i `uc
+-> -> 197 `i `uc
+-> -> 132 `i `uc
+-> -> 218 `i `uc
+-> -> 56 `i `uc
+-> -> 102 `i `uc
+-> -> 229 `i `uc
+-> -> 187 `i `uc
+-> -> 89 `i `uc
+-> -> 7 `i `uc
+"154
+-> -> 219 `i `uc
+-> -> 133 `i `uc
+-> -> 103 `i `uc
+-> -> 57 `i `uc
+-> -> 186 `i `uc
+-> -> 228 `i `uc
+-> -> 6 `i `uc
+-> -> 88 `i `uc
+-> -> 25 `i `uc
+-> -> 71 `i `uc
+-> -> 165 `i `uc
+-> -> 251 `i `uc
+-> -> 120 `i `uc
+-> -> 38 `i `uc
+-> -> 196 `i `uc
+-> -> 154 `i `uc
+"155
+-> -> 101 `i `uc
+-> -> 59 `i `uc
+-> -> 217 `i `uc
+-> -> 135 `i `uc
+-> -> 4 `i `uc
+-> -> 90 `i `uc
+-> -> 184 `i `uc
+-> -> 230 `i `uc
+-> -> 167 `i `uc
+-> -> 249 `i `uc
+-> -> 27 `i `uc
+-> -> 69 `i `uc
+-> -> 198 `i `uc
+-> -> 152 `i `uc
+-> -> 122 `i `uc
+-> -> 36 `i `uc
+"156
+-> -> 248 `i `uc
+-> -> 166 `i `uc
+-> -> 68 `i `uc
+-> -> 26 `i `uc
+-> -> 153 `i `uc
+-> -> 199 `i `uc
+-> -> 37 `i `uc
+-> -> 123 `i `uc
+-> -> 58 `i `uc
+-> -> 100 `i `uc
+-> -> 134 `i `uc
+-> -> 216 `i `uc
+-> -> 91 `i `uc
+-> -> 5 `i `uc
+-> -> 231 `i `uc
+-> -> 185 `i `uc
+"157
+-> -> 140 `i `uc
+-> -> 210 `i `uc
+-> -> 48 `i `uc
+-> -> 110 `i `uc
+-> -> 237 `i `uc
+-> -> 179 `i `uc
+-> -> 81 `i `uc
+-> -> 15 `i `uc
+-> -> 78 `i `uc
+-> -> 16 `i `uc
+-> -> 242 `i `uc
+-> -> 172 `i `uc
+-> -> 47 `i `uc
+-> -> 113 `i `uc
+-> -> 147 `i `uc
+-> -> 205 `i `uc
+"158
+-> -> 17 `i `uc
+-> -> 79 `i `uc
+-> -> 173 `i `uc
+-> -> 243 `i `uc
+-> -> 112 `i `uc
+-> -> 46 `i `uc
+-> -> 204 `i `uc
+-> -> 146 `i `uc
+-> -> 211 `i `uc
+-> -> 141 `i `uc
+-> -> 111 `i `uc
+-> -> 49 `i `uc
+-> -> 178 `i `uc
+-> -> 236 `i `uc
+-> -> 14 `i `uc
+-> -> 80 `i `uc
+"159
+-> -> 175 `i `uc
+-> -> 241 `i `uc
+-> -> 19 `i `uc
+-> -> 77 `i `uc
+-> -> 206 `i `uc
+-> -> 144 `i `uc
+-> -> 114 `i `uc
+-> -> 44 `i `uc
+-> -> 109 `i `uc
+-> -> 51 `i `uc
+-> -> 209 `i `uc
+-> -> 143 `i `uc
+-> -> 12 `i `uc
+-> -> 82 `i `uc
+-> -> 176 `i `uc
+-> -> 238 `i `uc
+"160
+-> -> 50 `i `uc
+-> -> 108 `i `uc
+-> -> 142 `i `uc
+-> -> 208 `i `uc
+-> -> 83 `i `uc
+-> -> 13 `i `uc
+-> -> 239 `i `uc
+-> -> 177 `i `uc
+-> -> 240 `i `uc
+-> -> 174 `i `uc
+-> -> 76 `i `uc
+-> -> 18 `i `uc
+-> -> 145 `i `uc
+-> -> 207 `i `uc
+-> -> 45 `i `uc
+-> -> 115 `i `uc
+"161
+-> -> 202 `i `uc
+-> -> 148 `i `uc
+-> -> 118 `i `uc
+-> -> 40 `i `uc
+-> -> 171 `i `uc
+-> -> 245 `i `uc
+-> -> 23 `i `uc
+-> -> 73 `i `uc
+-> -> 8 `i `uc
+-> -> 86 `i `uc
+-> -> 180 `i `uc
+-> -> 234 `i `uc
+-> -> 105 `i `uc
+-> -> 55 `i `uc
+-> -> 213 `i `uc
+-> -> 139 `i `uc
+"162
+-> -> 87 `i `uc
+-> -> 9 `i `uc
+-> -> 235 `i `uc
+-> -> 181 `i `uc
+-> -> 54 `i `uc
+-> -> 104 `i `uc
+-> -> 138 `i `uc
+-> -> 212 `i `uc
+-> -> 149 `i `uc
+-> -> 203 `i `uc
+-> -> 41 `i `uc
+-> -> 119 `i `uc
+-> -> 244 `i `uc
+-> -> 170 `i `uc
+-> -> 72 `i `uc
+-> -> 22 `i `uc
+"163
+-> -> 233 `i `uc
+-> -> 183 `i `uc
+-> -> 85 `i `uc
+-> -> 11 `i `uc
+-> -> 136 `i `uc
+-> -> 214 `i `uc
+-> -> 52 `i `uc
+-> -> 106 `i `uc
+-> -> 43 `i `uc
+-> -> 117 `i `uc
+-> -> 151 `i `uc
+-> -> 201 `i `uc
+-> -> 74 `i `uc
+-> -> 20 `i `uc
+-> -> 246 `i `uc
+-> -> 168 `i `uc
+"164
+-> -> 116 `i `uc
+-> -> 42 `i `uc
+-> -> 200 `i `uc
+-> -> 150 `i `uc
+-> -> 21 `i `uc
+-> -> 75 `i `uc
+-> -> 169 `i `uc
+-> -> 247 `i `uc
+-> -> 182 `i `uc
+-> -> 232 `i `uc
+-> -> 10 `i `uc
+-> -> 84 `i `uc
+-> -> 215 `i `uc
+-> -> 137 `i `uc
+-> -> 107 `i `uc
+"165
+-> -> 53 `i `uc
+..
+]
+[; ;onewire.c: 148: static const unsigned char dscrc_table[] = {
+[; ;onewire.c: 149: 0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,
+[; ;onewire.c: 150: 157,195, 33,127,252,162, 64, 30, 95, 1,227,189, 62, 96,130,220,
+[; ;onewire.c: 151: 35,125,159,193, 66, 28,254,160,225,191, 93, 3,128,222, 60, 98,
+[; ;onewire.c: 152: 190,224, 2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,
+[; ;onewire.c: 153: 70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89, 7,
+[; ;onewire.c: 154: 219,133,103, 57,186,228, 6, 88, 25, 71,165,251,120, 38,196,154,
+[; ;onewire.c: 155: 101, 59,217,135, 4, 90,184,230,167,249, 27, 69,198,152,122, 36,
+[; ;onewire.c: 156: 248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91, 5,231,185,
+[; ;onewire.c: 157: 140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,
+[; ;onewire.c: 158: 17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,
+[; ;onewire.c: 159: 175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,
+[; ;onewire.c: 160: 50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,
+[; ;onewire.c: 161: 202,148,118, 40,171,245, 23, 73, 8, 86,180,234,105, 55,213,139,
+[; ;onewire.c: 162: 87, 9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,
+[; ;onewire.c: 163: 233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,
+[; ;onewire.c: 164: 116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53
+[; ;onewire.c: 165: };
+"167
+[v _romid `uc ~T0 @X0 -> 8 `i e ]
+[; ;onewire.c: 167: unsigned char romid[8];
+"168
+[v _LastDiscrepancy `uc ~T0 @X0 1 e ]
+[i _LastDiscrepancy
+-> -> 0 `i `uc
+]
+[; ;onewire.c: 168: char LastDiscrepancy = 0;
+"169
+[v _LastFamilyDiscrepancy `uc ~T0 @X0 1 e ]
+[i _LastFamilyDiscrepancy
+-> -> 0 `i `uc
+]
+[; ;onewire.c: 169: char LastFamilyDiscrepancy = 0;
+"170
+[v _LastDeviceFlag `uc ~T0 @X0 1 e ]
+[i _LastDeviceFlag
+-> -> 0 `i `uc
+]
+[; ;onewire.c: 170: char LastDeviceFlag = 0;
+"171
+[v _crc8 `uc ~T0 @X0 1 e ]
+[; ;onewire.c: 171: unsigned char crc8;
+"174
+[v _docrc8 `(uc ~T0 @X0 1 sf1`uc ]
+{
+[; ;onewire.c: 173: static unsigned char docrc8(unsigned char value)
+[; ;onewire.c: 174: {
+[e :U _docrc8 ]
+[v _value `uc ~T0 @X0 1 r1 ]
+[f ]
+[; ;onewire.c: 175: crc8 = dscrc_table[crc8 ^ value];
+"175
+[e = _crc8 *U + &U _dscrc_table * -> -> ^ -> _crc8 `i -> _value `i `ui `ux -> -> # *U &U _dscrc_table `ui `ux ]
+[; ;onewire.c: 176: return crc8;
+"176
+[e ) _crc8 ]
+[e $UE 542  ]
+[; ;onewire.c: 177: }
+"177
+[e :UE 542 ]
+}
+"181
+[v _OW_search `(uc ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 180: bool OW_search()
+[; ;onewire.c: 181: {
+[e :U _OW_search ]
+[f ]
+"182
+[v _id_bit_number `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 182: char id_bit_number = 1;
+[e = _id_bit_number -> -> 1 `i `uc ]
+"183
+[v _last_zero `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 183: char last_zero = 0;
+[e = _last_zero -> -> 0 `i `uc ]
+"184
+[v _rom_byte_number `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 184: char rom_byte_number = 0;
+[e = _rom_byte_number -> -> 0 `i `uc ]
+"185
+[v _search_result `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 185: char search_result = 0;
+[e = _search_result -> -> 0 `i `uc ]
+"186
+[v _rom_byte_mask `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 186: unsigned char rom_byte_mask = 1;
+[e = _rom_byte_mask -> -> 1 `i `uc ]
+"187
+[v _search_direction `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 187: unsigned char search_direction;
+[; ;onewire.c: 189: crc8 = 0;
+"189
+[e = _crc8 -> -> 0 `i `uc ]
+[; ;onewire.c: 192: int_disable();
+"192
+[e ( _int_disable ..  ]
+[; ;onewire.c: 195: if (!LastDeviceFlag) {
+"195
+[e $ ! ! != -> _LastDeviceFlag `i -> -> -> 0 `i `uc `i 544  ]
+{
+[; ;onewire.c: 196: if (!OW_reset())
+"196
+[e $ ! ! != -> ( _OW_reset ..  `i -> -> -> 0 `i `uc `i 545  ]
+[; ;onewire.c: 197: {
+"197
+{
+[; ;onewire.c: 198: msg_write("Reset said nothing there.\r\n");
+"198
+[e ( _msg_write (1 :s 1C ]
+[; ;onewire.c: 200: LastDiscrepancy = 0;
+"200
+[e = _LastDiscrepancy -> -> 0 `i `uc ]
+[; ;onewire.c: 201: LastDeviceFlag = 0;
+"201
+[e = _LastDeviceFlag -> -> 0 `i `uc ]
+[; ;onewire.c: 202: LastFamilyDiscrepancy = 0;
+"202
+[e = _LastFamilyDiscrepancy -> -> 0 `i `uc ]
+[; ;onewire.c: 203: int_enable();
+"203
+[e ( _int_enable ..  ]
+[; ;onewire.c: 204: return 0;
+"204
+[e ) -> -> 0 `i `uc ]
+[e $UE 543  ]
+"205
+}
+[e :U 545 ]
+[; ;onewire.c: 205: }
+[; ;onewire.c: 208: OW_write_byte(0xF0);
+"208
+[e ( _OW_write_byte (1 -> -> 240 `i `uc ]
+[; ;onewire.c: 211: do {
+"211
+[e :U 548 ]
+{
+"213
+[v _id_bit `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 213: bool id_bit = OW_read_bit();
+[e = _id_bit ( _OW_read_bit ..  ]
+[; ;onewire.c: 214: _delay(6);
+"214
+[e ( __delay (1 -> -> -> 6 `i `l `ul ]
+"215
+[v _cmp_id_bit `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 215: bool cmp_id_bit = OW_read_bit();
+[e = _cmp_id_bit ( _OW_read_bit ..  ]
+[; ;onewire.c: 218: if (id_bit && cmp_id_bit) {
+"218
+[e $ ! && != -> _id_bit `i -> -> -> 0 `i `uc `i != -> _cmp_id_bit `i -> -> -> 0 `i `uc `i 549  ]
+{
+[; ;onewire.c: 219: break;
+"219
+[e $U 547  ]
+"220
+}
+[e :U 549 ]
+[; ;onewire.c: 220: }
+[; ;onewire.c: 222: if (id_bit != cmp_id_bit) {
+"222
+[e $ ! != -> _id_bit `i -> _cmp_id_bit `i 550  ]
+{
+[; ;onewire.c: 224: search_direction = id_bit;
+"224
+[e = _search_direction _id_bit ]
+"225
+}
+[; ;onewire.c: 225: } else {
+[e $U 551  ]
+[e :U 550 ]
+{
+[; ;onewire.c: 230: if (id_bit_number < LastDiscrepancy) {
+"230
+[e $ ! < -> _id_bit_number `i -> _LastDiscrepancy `i 552  ]
+{
+[; ;onewire.c: 231: search_direction = ((romid[rom_byte_number] & rom_byte_mask) > 0);
+"231
+[e = _search_direction -> -> > & -> *U + &U _romid * -> _rom_byte_number `ux -> -> # *U &U _romid `ui `ux `i -> _rom_byte_mask `i -> 0 `i `i `uc ]
+"232
+}
+[; ;onewire.c: 232: } else {
+[e $U 553  ]
+[e :U 552 ]
+{
+[; ;onewire.c: 234: search_direction = (id_bit_number == LastDiscrepancy);
+"234
+[e = _search_direction -> -> == -> _id_bit_number `i -> _LastDiscrepancy `i `i `uc ]
+"235
+}
+[e :U 553 ]
+[; ;onewire.c: 235: }
+[; ;onewire.c: 238: if (search_direction == 0)
+"238
+[e $ ! == -> _search_direction `i -> 0 `i 554  ]
+[; ;onewire.c: 239: {
+"239
+{
+[; ;onewire.c: 240: last_zero = id_bit_number;
+"240
+[e = _last_zero _id_bit_number ]
+[; ;onewire.c: 242: if (last_zero < 9)
+"242
+[e $ ! < -> _last_zero `i -> 9 `i 555  ]
+[; ;onewire.c: 243: LastFamilyDiscrepancy = last_zero;
+"243
+[e = _LastFamilyDiscrepancy _last_zero ]
+[e :U 555 ]
+"244
+}
+[e :U 554 ]
+"245
+}
+[e :U 551 ]
+[; ;onewire.c: 244: }
+[; ;onewire.c: 245: }
+[; ;onewire.c: 249: if (search_direction == 1)
+"249
+[e $ ! == -> _search_direction `i -> 1 `i 556  ]
+[; ;onewire.c: 250: romid[rom_byte_number] |= rom_byte_mask;
+"250
+[e =| *U + &U _romid * -> _rom_byte_number `ux -> -> # *U &U _romid `ui `ux _rom_byte_mask ]
+[e $U 557  ]
+"251
+[e :U 556 ]
+[; ;onewire.c: 251: else
+[; ;onewire.c: 252: romid[rom_byte_number] &= ~rom_byte_mask;
+"252
+[e =& *U + &U _romid * -> _rom_byte_number `ux -> -> # *U &U _romid `ui `ux -> ~ -> _rom_byte_mask `i `uc ]
+[e :U 557 ]
+[; ;onewire.c: 255: OW_write_bit(search_direction);
+"255
+[e ( _OW_write_bit (1 _search_direction ]
+[; ;onewire.c: 259: id_bit_number++;
+"259
+[e ++ _id_bit_number -> -> 1 `i `uc ]
+[; ;onewire.c: 260: rom_byte_mask <<= 1;
+"260
+[e =<< _rom_byte_mask -> 1 `i ]
+[; ;onewire.c: 263: if (rom_byte_mask == 0)
+"263
+[e $ ! == -> _rom_byte_mask `i -> 0 `i 558  ]
+[; ;onewire.c: 264: {
+"264
+{
+[; ;onewire.c: 265: docrc8(romid[rom_byte_number]);
+"265
+[e ( _docrc8 (1 *U + &U _romid * -> _rom_byte_number `ux -> -> # *U &U _romid `ui `ux ]
+[; ;onewire.c: 266: rom_byte_number++;
+"266
+[e ++ _rom_byte_number -> -> 1 `i `uc ]
+[; ;onewire.c: 267: rom_byte_mask = 1;
+"267
+[e = _rom_byte_mask -> -> 1 `i `uc ]
+"268
+}
+[e :U 558 ]
+"269
+}
+[; ;onewire.c: 268: }
+[; ;onewire.c: 269: } while (rom_byte_number < 8);
+[e $ < -> _rom_byte_number `i -> 8 `i 548  ]
+[e :U 547 ]
+"270
+}
+[e :U 544 ]
+[; ;onewire.c: 270: }
+[; ;onewire.c: 273: if (!(id_bit_number < 65 || crc8 != 0))
+"273
+[e $ ! ! || < -> _id_bit_number `i -> 65 `i != -> _crc8 `i -> 0 `i 559  ]
+[; ;onewire.c: 274: {
+"274
+{
+[; ;onewire.c: 276: LastDiscrepancy = last_zero;
+"276
+[e = _LastDiscrepancy _last_zero ]
+[; ;onewire.c: 279: if (LastDiscrepancy == 0)
+"279
+[e $ ! == -> _LastDiscrepancy `i -> 0 `i 560  ]
+[; ;onewire.c: 280: LastDeviceFlag = 1;
+"280
+[e = _LastDeviceFlag -> -> 1 `i `uc ]
+[e :U 560 ]
+[; ;onewire.c: 282: search_result = 1;
+"282
+[e = _search_result -> -> 1 `i `uc ]
+"283
+}
+[e :U 559 ]
+[; ;onewire.c: 283: }
+[; ;onewire.c: 285: if (!search_result || !romid[0])
+"285
+[e $ ! || ! != -> _search_result `i -> -> -> 0 `i `uc `i ! != -> *U + &U _romid * -> -> -> 0 `i `ui `ux -> -> # *U &U _romid `ui `ux `i -> -> -> 0 `i `uc `i 561  ]
+[; ;onewire.c: 286: {
+"286
+{
+[; ;onewire.c: 287: LastDiscrepancy = 0;
+"287
+[e = _LastDiscrepancy -> -> 0 `i `uc ]
+[; ;onewire.c: 288: LastDeviceFlag = 0;
+"288
+[e = _LastDeviceFlag -> -> 0 `i `uc ]
+[; ;onewire.c: 289: LastFamilyDiscrepancy = 0;
+"289
+[e = _LastFamilyDiscrepancy -> -> 0 `i `uc ]
+[; ;onewire.c: 290: search_result = 0;
+"290
+[e = _search_result -> -> 0 `i `uc ]
+"291
+}
+[e :U 561 ]
+[; ;onewire.c: 291: }
+[; ;onewire.c: 293: int_enable();
+"293
+[e ( _int_enable ..  ]
+[; ;onewire.c: 294: return search_result;
+"294
+[e ) _search_result ]
+[e $UE 543  ]
+[; ;onewire.c: 295: }
+"295
+[e :UE 543 ]
+}
+"299
+[v _OW_search_init `(v ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 298: void OW_search_init()
+[; ;onewire.c: 299: {
+[e :U _OW_search_init ]
+[f ]
+[; ;onewire.c: 300: LastDiscrepancy = 0;
+"300
+[e = _LastDiscrepancy -> -> 0 `i `uc ]
+[; ;onewire.c: 301: LastDeviceFlag = 0;
+"301
+[e = _LastDeviceFlag -> -> 0 `i `uc ]
+[; ;onewire.c: 302: LastFamilyDiscrepancy = 0;
+"302
+[e = _LastFamilyDiscrepancy -> -> 0 `i `uc ]
+[; ;onewire.c: 304: for (int j=0; j<8; j++) romid[j]=0;
+"304
+{
+[v _j `i ~T0 @X0 1 a ]
+[e = _j -> 0 `i ]
+[e $ < _j -> 8 `i 563  ]
+[e $U 564  ]
+[e :U 563 ]
+[e = *U + &U _romid * -> -> _j `ui `ux -> -> # *U &U _romid `ui `ux -> -> 0 `i `uc ]
+[e ++ _j -> 1 `i ]
+[e $ < _j -> 8 `i 563  ]
+[e :U 564 ]
+}
+[; ;onewire.c: 305: }
+"305
+[e :UE 562 ]
+}
+"310
+[v _OW_identify `(v ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 309: void OW_identify()
+[; ;onewire.c: 310: {
+[e :U _OW_identify ]
+[f ]
+[; ;onewire.c: 311: int_disable();
+"311
+[e ( _int_disable ..  ]
+[; ;onewire.c: 312: OW_reset();
+"312
+[e ( _OW_reset ..  ]
+[; ;onewire.c: 314: OW_write_byte(0x33);
+"314
+[e ( _OW_write_byte (1 -> -> 51 `i `uc ]
+[; ;onewire.c: 315: for (int j=0; j<8; j++)
+"315
+{
+[v _j `i ~T0 @X0 1 a ]
+[e = _j -> 0 `i ]
+[e $ < _j -> 8 `i 567  ]
+[e $U 568  ]
+"316
+[e :U 567 ]
+[; ;onewire.c: 316: romid[j] = OW_read_byte();
+[e = *U + &U _romid * -> -> _j `ui `ux -> -> # *U &U _romid `ui `ux ( _OW_read_byte ..  ]
+"315
+[e ++ _j -> 1 `i ]
+[e $ < _j -> 8 `i 567  ]
+[e :U 568 ]
+"316
+}
+[; ;onewire.c: 317: int_enable();
+"317
+[e ( _int_enable ..  ]
+[; ;onewire.c: 318: }
+"318
+[e :UE 566 ]
+}
+"322
+[v _OW_parasite `(uc ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 321: bool OW_parasite(void)
+[; ;onewire.c: 322: {
+[e :U _OW_parasite ]
+[f ]
+[; ;onewire.c: 323: int_disable();
+"323
+[e ( _int_disable ..  ]
+[; ;onewire.c: 324: OW_reset();
+"324
+[e ( _OW_reset ..  ]
+[; ;onewire.c: 325: OW_write_byte(0xCC);
+"325
+[e ( _OW_write_byte (1 -> -> 204 `i `uc ]
+[; ;onewire.c: 326: OW_write_byte(0xB4);
+"326
+[e ( _OW_write_byte (1 -> -> 180 `i `uc ]
+"327
+[v _no `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 327: bool no = OW_read_bit();
+[e = _no ( _OW_read_bit ..  ]
+[; ;onewire.c: 328: int_enable();
+"328
+[e ( _int_enable ..  ]
+[; ;onewire.c: 329: return !no;
+"329
+[e ) -> -> ! != -> _no `i -> -> -> 0 `i `uc `i `i `uc ]
+[e $UE 570  ]
+[; ;onewire.c: 330: }
+"330
+[e :UE 570 ]
+}
+"336
+[v _OW_select_id `(v ~T0 @X0 1 sf ]
+{
+[; ;onewire.c: 335: static void OW_select_id(void)
+[; ;onewire.c: 336: {
+[e :U _OW_select_id ]
+[f ]
+[; ;onewire.c: 337: if (romid[0] == 0) {
+"337
+[e $ ! == -> *U + &U _romid * -> -> -> 0 `i `ui `ux -> -> # *U &U _romid `ui `ux `i -> 0 `i 572  ]
+{
+[; ;onewire.c: 338: OW_write_byte(0xCC);
+"338
+[e ( _OW_write_byte (1 -> -> 204 `i `uc ]
+"339
+}
+[; ;onewire.c: 339: } else {
+[e $U 573  ]
+[e :U 572 ]
+{
+[; ;onewire.c: 340: OW_write_byte(0x55);
+"340
+[e ( _OW_write_byte (1 -> -> 85 `i `uc ]
+[; ;onewire.c: 341: for (int8_t j=0; j<8; j++) {
+"341
+{
+[v _j `c ~T0 @X0 1 a ]
+[e = _j -> -> 0 `i `c ]
+[e $ < -> _j `i -> 8 `i 574  ]
+[e $U 575  ]
+[e :U 574 ]
+{
+[; ;onewire.c: 342: OW_write_byte(romid[j]);
+"342
+[e ( _OW_write_byte (1 *U + &U _romid * -> -> _j `uc `ux -> -> # *U &U _romid `ui `ux ]
+"343
+}
+"341
+[e ++ _j -> -> 1 `i `c ]
+[e $ < -> _j `i -> 8 `i 574  ]
+[e :U 575 ]
+"343
+}
+"344
+}
+[e :U 573 ]
+[; ;onewire.c: 343: }
+[; ;onewire.c: 344: }
+[; ;onewire.c: 345: }
+"345
+[e :UE 571 ]
+}
+"350
+[v _OW_read_block `(v ~T0 @X0 1 ef3`uc`*uc`uc ]
+{
+[; ;onewire.c: 349: void OW_read_block(uint8_t code, uint8_t * data, uint8_t len)
+[; ;onewire.c: 350: {
+[e :U _OW_read_block ]
+[v _code `uc ~T0 @X0 1 r1 ]
+[v _data `*uc ~T0 @X0 1 r2 ]
+[v _len `uc ~T0 @X0 1 r3 ]
+[f ]
+[; ;onewire.c: 351: int_disable();
+"351
+[e ( _int_disable ..  ]
+[; ;onewire.c: 352: OW_reset();
+"352
+[e ( _OW_reset ..  ]
+[; ;onewire.c: 353: OW_select_id();
+"353
+[e ( _OW_select_id ..  ]
+[; ;onewire.c: 354: OW_write_byte(code);
+"354
+[e ( _OW_write_byte (1 _code ]
+[; ;onewire.c: 355: for (int8_t j=0; j<len; j++)
+"355
+{
+[v _j `c ~T0 @X0 1 a ]
+[e = _j -> -> 0 `i `c ]
+[e $U 581  ]
+"356
+[e :U 578 ]
+[; ;onewire.c: 356: data[j] = OW_read_byte();
+[e = *U + _data * -> _j `x -> -> # *U _data `i `x ( _OW_read_byte ..  ]
+"355
+[e ++ _j -> -> 1 `i `c ]
+[e :U 581 ]
+[e $ < -> _j `i -> _len `i 578  ]
+[e :U 579 ]
+"356
+}
+[; ;onewire.c: 357: int_enable();
+"357
+[e ( _int_enable ..  ]
+[; ;onewire.c: 358: }
+"358
+[e :UE 577 ]
+}
+"362
+[v _OW_write_block `(v ~T0 @X0 1 ef3`uc`*uc`uc ]
+{
+[; ;onewire.c: 361: void OW_write_block(uint8_t code, uint8_t * data, uint8_t len)
+[; ;onewire.c: 362: {
+[e :U _OW_write_block ]
+[v _code `uc ~T0 @X0 1 r1 ]
+[v _data `*uc ~T0 @X0 1 r2 ]
+[v _len `uc ~T0 @X0 1 r3 ]
+[f ]
+[; ;onewire.c: 363: int_disable();
+"363
+[e ( _int_disable ..  ]
+[; ;onewire.c: 364: OW_reset();
+"364
+[e ( _OW_reset ..  ]
+[; ;onewire.c: 365: OW_select_id();
+"365
+[e ( _OW_select_id ..  ]
+[; ;onewire.c: 366: OW_write_byte(code);
+"366
+[e ( _OW_write_byte (1 _code ]
+[; ;onewire.c: 367: for (int8_t j=0; j<len; j++) {
+"367
+{
+[v _j `c ~T0 @X0 1 a ]
+[e = _j -> -> 0 `i `c ]
+[e $U 586  ]
+[e :U 583 ]
+{
+[; ;onewire.c: 368: OW_write_byte(data[j]);
+"368
+[e ( _OW_write_byte (1 *U + _data * -> _j `x -> -> # *U _data `i `x ]
+"369
+}
+"367
+[e ++ _j -> -> 1 `i `c ]
+[e :U 586 ]
+[e $ < -> _j `i -> _len `i 583  ]
+[e :U 584 ]
+"369
+}
+[; ;onewire.c: 369: }
+[; ;onewire.c: 370: int_enable();
+"370
+[e ( _int_enable ..  ]
+[; ;onewire.c: 371: }
+"371
+[e :UE 582 ]
+}
+"376
+[v _OW_convert `(v ~T0 @X0 1 ef ]
+{
+[; ;onewire.c: 375: void OW_convert()
+[; ;onewire.c: 376: {
+[e :U _OW_convert ]
+[f ]
+"378
+[v _para `uc ~T0 @X0 1 a ]
+[; ;onewire.c: 378: bool para = OW_parasite();
+[e = _para ( _OW_parasite ..  ]
+[; ;onewire.c: 380: int_disable();
+"380
+[e ( _int_disable ..  ]
+[; ;onewire.c: 381: OW_reset();
+"381
+[e ( _OW_reset ..  ]
+[; ;onewire.c: 382: OW_select_id();
+"382
+[e ( _OW_select_id ..  ]
+[; ;onewire.c: 384: OW_write_byte(0x44);
+"384
+[e ( _OW_write_byte (1 -> -> 68 `i `uc ]
+[; ;onewire.c: 385: if (para) {
+"385
+[e $ ! != -> _para `i -> -> -> 0 `i `uc `i 588  ]
+{
+[; ;onewire.c: 387: { PORTAbits.RA5 = 1; TRISAbits.TRISA5 = 0; };
+"387
+{
+[e = . . _PORTAbits 0 5 -> -> 1 `i `uc ]
+[e = . . _TRISAbits 0 5 -> -> 0 `i `uc ]
+}
+[; ;onewire.c: 388: _delay(250000);
+"388
+[e ( __delay (1 -> -> 250000 `l `ul ]
+[; ;onewire.c: 389: _delay(250000);
+"389
+[e ( __delay (1 -> -> 250000 `l `ul ]
+[; ;onewire.c: 390: _delay(250000);
+"390
+[e ( __delay (1 -> -> 250000 `l `ul ]
+[; ;onewire.c: 391: _delay(250000);
+"391
+[e ( __delay (1 -> -> 250000 `l `ul ]
+"392
+}
+[; ;onewire.c: 392: } else {
+[e $U 589  ]
+[e :U 588 ]
+{
+[; ;onewire.c: 395: do {
+"395
+[e :U 592 ]
+{
+[; ;onewire.c: 396: _delay(1000);
+"396
+[e ( __delay (1 -> -> -> 1000 `i `l `ul ]
+"397
+}
+[; ;onewire.c: 397: } while (!OW_read_bit());
+[e $ ! != -> ( _OW_read_bit ..  `i -> -> -> 0 `i `uc `i 592  ]
+[e :U 591 ]
+"398
+}
+[e :U 589 ]
+[; ;onewire.c: 398: }
+[; ;onewire.c: 399: int_enable();
+"399
+[e ( _int_enable ..  ]
+[; ;onewire.c: 400: }
+"400
+[e :UE 587 ]
+}
+[a 1C 82 101 115 101 116 32 115 97 105 100 32 110 111 116 104 105 110 103 32 116 104 101 114 101 46 13 10 0 ]
+

diff --git a/build/XC8_12F1822/production/onewire.p1.d b/build/XC8_12F1822/production/onewire.p1.d
new file mode 100644 (file)
index 0000000..ecd8b0d
--- /dev/null
+++ b/build/XC8_12F1822/production/onewire.p1.d
@@ -0,0 +1,6 @@
+ build/XC8_12F1822/production/onewire.d  \
+ build/XC8_12F1822/production/onewire.p1:  \
+ onewire.c  \
+onewire.h  \
+user.h  \
+system.h 
\ No newline at end of file

diff --git a/build/XC8_12F1822/production/onewire.pre b/build/XC8_12F1822/production/onewire.pre
new file mode 100644 (file)
index 0000000..c4c66ec
--- /dev/null
+++ b/build/XC8_12F1822/production/onewire.pre
@@ -0,0 +1,6027 @@
+
+# 1 "onewire.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1822.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+struct {
+unsigned AN0 :1;
+unsigned AN1 :1;
+unsigned AN2 :1;
+unsigned :1;
+unsigned AN3 :1;
+};
+struct {
+unsigned CPS0 :1;
+unsigned CPS1 :1;
+unsigned CPS2 :1;
+unsigned :1;
+unsigned CPS3 :1;
+};
+struct {
+unsigned C1INP :1;
+unsigned C1IN0N :1;
+unsigned C1OUT :1;
+unsigned :1;
+unsigned C1IN1N :1;
+};
+struct {
+unsigned DACOUT :1;
+unsigned SRI :1;
+unsigned SRQ :1;
+unsigned :2;
+unsigned SRNQ :1;
+};
+struct {
+unsigned :1;
+unsigned SCK :1;
+unsigned T0CKI :1;
+unsigned :1;
+unsigned T1OSO :1;
+unsigned T1CKI :1;
+};
+struct {
+unsigned :1;
+unsigned SCL :1;
+unsigned SDA :1;
+unsigned nMCLR :1;
+unsigned CLKR :1;
+unsigned T1OSI :1;
+};
+struct {
+unsigned MDOUT :1;
+unsigned MDMIN :1;
+unsigned MDCIN1 :1;
+unsigned :1;
+unsigned MDCIN2 :1;
+};
+struct {
+unsigned :2;
+unsigned SDI :1;
+unsigned :1;
+unsigned OSC2 :1;
+unsigned OSC1 :1;
+};
+struct {
+unsigned :2;
+unsigned FLT0 :1;
+unsigned :1;
+unsigned CLKOUT :1;
+unsigned CLKIN :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 698
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 759
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 798
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 817
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 842
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 861
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 932
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 1008
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 1027
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 1046
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 1116
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 1175
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 1208
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1257
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1318
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1357
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1439
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1489
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1547
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1604
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1675
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1736
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1761
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1780
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+struct {
+unsigned :1;
+unsigned nDONE :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1868
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1933
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1977
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 2033
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned :4;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 2086
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 2105
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :6;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 2131
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 2206
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2260
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2311
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2381
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2432
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2507
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2573
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2619
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2644
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2663
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2692
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2706
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2725
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2786
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2805
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2824
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2843
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2866
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2880
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2899
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2960
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 3021
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 3072
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 3129
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 3152
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 3166
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 3189
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 3203
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3226
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3240
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3305
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3361
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3438
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3500
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3564
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3629
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3685
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3750
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3806
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3825
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3844
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3925
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3994
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 4079
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 4155
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned STR1C :1;
+unsigned STR1D :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 4198
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4255
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4312
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4369
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4444
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4494
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4546
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4610
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4674
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4705
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4724
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4743
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4762
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4781
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4800
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4819
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4838
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4857
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4876
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4901
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+
+extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+# 31 "system.h"
+void ConfigureOscillator(void);
+
+# 13 "user.h"
+void InitApp(void);
+bool msg_empty(void);
+void msg_write(const char *msg);
+void msg_writebyte(const char msg);
+void msg_sendnext(void);
+void tohex(char val[3], char i);
+void msg_recvnext(void);
+bool msg_recvready(void);
+char msg_recv(void);
+void putch(char);
+
+void int_disable(void);
+void int_enable(void);
+
+# 11 "onewire.h"
+bool OW_reset(void);
+void OW_write_bit(bool val);
+bool OW_read_bit();
+void OW_write_byte(unsigned char byte);
+unsigned char OW_read_byte(void);
+
+void OW_search_init();
+bool OW_search(void);
+void OW_start(void);
+
+void OW_identify();
+bool OW_parasite(void);
+void OW_read_block(uint8_t code, uint8_t * data, uint8_t len);
+void OW_convert();
+
+
+inline void drive_OW_low(void);
+inline void drive_OW_high(void);
+inline void float_OW(void);
+inline bool read_OW(void);
+
+extern unsigned char romid[8];
+
+# 24 "onewire.c"
+inline void drive_OW_low(void)
+{
+PORTAbits.RA5 = 0;
+TRISAbits.TRISA5 = 0;
+}
+
+inline void drive_OW_high(void)
+{
+PORTAbits.RA5 = 1;
+TRISAbits.TRISA5 = 0;
+}
+
+inline void float_OW(void)
+{
+TRISAbits.TRISA5 = 1;
+}
+
+inline bool read_OW(void)
+{
+TRISAbits.TRISA5 = 1;
+return PORTAbits.RA5;
+}
+
+# 51
+void OW_start(void)
+{
+
+float_OW();
+}
+
+
+bool OW_reset(void)
+{
+bool presence = 0;
+
+{ PORTAbits.RA5 = 0; TRISAbits.TRISA5 = 0; };
+_delay(250);
+_delay(250);
+{ TRISAbits.TRISA5 = 1; };
+_delay(70);
+presence = (PORTAbits.RA5);
+_delay(215);
+_delay(215);
+
+return ! presence;
+}
+
+void OW_write_bit(bool val)
+{
+
+# 84
+{ PORTAbits.RA5 = 0; TRISAbits.TRISA5 = 0; };
+_nop();
+_nop();
+
+if (val) { TRISAbits.TRISA5 = 1; };
+_delay(60);
+{ TRISAbits.TRISA5 = 1; };
+_nop();
+_nop();
+
+}
+
+bool OW_read_bit()
+{
+bool val;
+
+# 107
+{ PORTAbits.RA5 = 0; TRISAbits.TRISA5 = 0; };
+
+_nop();
+_nop();
+_nop();
+_nop();
+_nop();
+{ TRISAbits.TRISA5 = 1; };
+
+_nop();
+_nop();
+_nop();
+val = read_OW();
+_delay(50);
+
+
+return val;
+}
+
+void OW_write_byte(unsigned char byte)
+{
+for (char i=8; i!=0; i--)
+{
+OW_write_bit( byte & 0x01 );
+byte >>= 1;
+}
+}
+
+unsigned char OW_read_byte(void)
+{
+unsigned char byte = 0;
+for (char i=8; i!=0; i--)
+{
+byte >>= 1;
+if (OW_read_bit())
+byte |= 0x80;
+
+}
+return byte;
+}
+
+static const unsigned char dscrc_table[] = {
+0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,
+157,195, 33,127,252,162, 64, 30, 95, 1,227,189, 62, 96,130,220,
+35,125,159,193, 66, 28,254,160,225,191, 93, 3,128,222, 60, 98,
+190,224, 2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,
+70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89, 7,
+219,133,103, 57,186,228, 6, 88, 25, 71,165,251,120, 38,196,154,
+101, 59,217,135, 4, 90,184,230,167,249, 27, 69,198,152,122, 36,
+248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91, 5,231,185,
+140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,
+17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,
+175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,
+50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,
+202,148,118, 40,171,245, 23, 73, 8, 86,180,234,105, 55,213,139,
+87, 9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,
+233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,
+116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53
+};
+
+unsigned char romid[8];
+char LastDiscrepancy = 0;
+char LastFamilyDiscrepancy = 0;
+char LastDeviceFlag = 0;
+unsigned char crc8;
+
+static unsigned char docrc8(unsigned char value)
+{
+crc8 = dscrc_table[crc8 ^ value];
+return crc8;
+}
+
+
+bool OW_search()
+{
+char id_bit_number = 1;
+char last_zero = 0;
+char rom_byte_number = 0;
+char search_result = 0;
+unsigned char rom_byte_mask = 1;
+unsigned char search_direction;
+
+crc8 = 0;
+
+
+int_disable();
+
+
+if (!LastDeviceFlag) {
+if (!OW_reset())
+{
+msg_write("Reset said nothing there.\r\n");
+
+LastDiscrepancy = 0;
+LastDeviceFlag = 0;
+LastFamilyDiscrepancy = 0;
+int_enable();
+return 0;
+}
+
+
+OW_write_byte(0xF0);
+
+
+do {
+
+bool id_bit = OW_read_bit();
+_delay(6);
+bool cmp_id_bit = OW_read_bit();
+
+
+if (id_bit && cmp_id_bit) {
+break;
+}
+
+if (id_bit != cmp_id_bit) {
+
+search_direction = id_bit;
+} else {
+
+
+
+
+if (id_bit_number < LastDiscrepancy) {
+search_direction = ((romid[rom_byte_number] & rom_byte_mask) > 0);
+} else {
+
+search_direction = (id_bit_number == LastDiscrepancy);
+}
+
+
+if (search_direction == 0)
+{
+last_zero = id_bit_number;
+
+if (last_zero < 9)
+LastFamilyDiscrepancy = last_zero;
+}
+}
+
+
+
+if (search_direction == 1)
+romid[rom_byte_number] |= rom_byte_mask;
+else
+romid[rom_byte_number] &= ~rom_byte_mask;
+
+
+OW_write_bit(search_direction);
+
+
+
+id_bit_number++;
+rom_byte_mask <<= 1;
+
+
+if (rom_byte_mask == 0)
+{
+docrc8(romid[rom_byte_number]);
+rom_byte_number++;
+rom_byte_mask = 1;
+}
+} while (rom_byte_number < 8);
+}
+
+
+if (!(id_bit_number < 65 || crc8 != 0))
+{
+
+LastDiscrepancy = last_zero;
+
+
+if (LastDiscrepancy == 0)
+LastDeviceFlag = 1;
+
+search_result = 1;
+}
+
+if (!search_result || !romid[0])
+{
+LastDiscrepancy = 0;
+LastDeviceFlag = 0;
+LastFamilyDiscrepancy = 0;
+search_result = 0;
+}
+
+int_enable();
+return search_result;
+}
+
+
+void OW_search_init()
+{
+LastDiscrepancy = 0;
+LastDeviceFlag = 0;
+LastFamilyDiscrepancy = 0;
+
+for (int j=0; j<8; j++) romid[j]=0;
+}
+
+
+
+void OW_identify()
+{
+int_disable();
+OW_reset();
+
+OW_write_byte(0x33);
+for (int j=0; j<8; j++)
+romid[j] = OW_read_byte();
+int_enable();
+}
+
+
+bool OW_parasite(void)
+{
+int_disable();
+OW_reset();
+OW_write_byte(0xCC);
+OW_write_byte(0xB4);
+bool no = OW_read_bit();
+int_enable();
+return !no;
+}
+
+# 335
+static void OW_select_id(void)
+{
+if (romid[0] == 0) {
+OW_write_byte(0xCC);
+} else {
+OW_write_byte(0x55);
+for (int8_t j=0; j<8; j++) {
+OW_write_byte(romid[j]);
+}
+}
+}
+
+
+
+void OW_read_block(uint8_t code, uint8_t * data, uint8_t len)
+{
+int_disable();
+OW_reset();
+OW_select_id();
+OW_write_byte(code);
+for (int8_t j=0; j<len; j++)
+data[j] = OW_read_byte();
+int_enable();
+}
+
+
+void OW_write_block(uint8_t code, uint8_t * data, uint8_t len)
+{
+int_disable();
+OW_reset();
+OW_select_id();
+OW_write_byte(code);
+for (int8_t j=0; j<len; j++) {
+OW_write_byte(data[j]);
+}
+int_enable();
+}
+
+
+
+void OW_convert()
+{
+
+bool para = OW_parasite();
+
+int_disable();
+OW_reset();
+OW_select_id();
+
+OW_write_byte(0x44);
+if (para) {
+
+{ PORTAbits.RA5 = 1; TRISAbits.TRISA5 = 0; };
+_delay(250000);
+_delay(250000);
+_delay(250000);
+_delay(250000);
+} else {
+
+
+do {
+_delay(1000);
+} while (!OW_read_bit());
+}
+int_enable();
+}
+

diff --git a/build/XC8_12F1822/production/system.p1 b/build/XC8_12F1822/production/system.p1
new file mode 100644 (file)
index 0000000..3f3f341
--- /dev/null
+++ b/build/XC8_12F1822/production/system.p1
@@ -0,0 +1,4147 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[s S87 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S87 . SCS0 SCS1 . IRCF0 IRCF1 IRCF2 IRCF3 SPLLEN ]
+[s S88 :2 `uc 1 :1 `uc 1 :4 `uc 1 ]
+[n S88 . SCS . IRCF ]
+[u S86 `S87 1 `S88 1 ]
+[n S86 . . . ]
+"1626 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[v _OSCCONbits `VS86 ~T0 @X0 0 e@153 ]
+[; ;pic12f1822.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[; ;pic12f1822.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1822.h: 49: typedef union {
+[; ;pic12f1822.h: 50: struct {
+[; ;pic12f1822.h: 51: unsigned INDF0 :8;
+[; ;pic12f1822.h: 52: };
+[; ;pic12f1822.h: 53: } INDF0bits_t;
+[; ;pic12f1822.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1822.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1822.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1822.h: 68: typedef union {
+[; ;pic12f1822.h: 69: struct {
+[; ;pic12f1822.h: 70: unsigned INDF1 :8;
+[; ;pic12f1822.h: 71: };
+[; ;pic12f1822.h: 72: } INDF1bits_t;
+[; ;pic12f1822.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1822.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1822.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1822.h: 87: typedef union {
+[; ;pic12f1822.h: 88: struct {
+[; ;pic12f1822.h: 89: unsigned PCL :8;
+[; ;pic12f1822.h: 90: };
+[; ;pic12f1822.h: 91: } PCLbits_t;
+[; ;pic12f1822.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1822.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1822.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1822.h: 106: typedef union {
+[; ;pic12f1822.h: 107: struct {
+[; ;pic12f1822.h: 108: unsigned C :1;
+[; ;pic12f1822.h: 109: unsigned DC :1;
+[; ;pic12f1822.h: 110: unsigned Z :1;
+[; ;pic12f1822.h: 111: unsigned nPD :1;
+[; ;pic12f1822.h: 112: unsigned nTO :1;
+[; ;pic12f1822.h: 113: };
+[; ;pic12f1822.h: 114: struct {
+[; ;pic12f1822.h: 115: unsigned CARRY :1;
+[; ;pic12f1822.h: 116: };
+[; ;pic12f1822.h: 117: struct {
+[; ;pic12f1822.h: 118: unsigned :2;
+[; ;pic12f1822.h: 119: unsigned ZERO :1;
+[; ;pic12f1822.h: 120: };
+[; ;pic12f1822.h: 121: } STATUSbits_t;
+[; ;pic12f1822.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1822.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1822.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1822.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1822.h: 169: typedef union {
+[; ;pic12f1822.h: 170: struct {
+[; ;pic12f1822.h: 171: unsigned FSR0L :8;
+[; ;pic12f1822.h: 172: };
+[; ;pic12f1822.h: 173: } FSR0Lbits_t;
+[; ;pic12f1822.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1822.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1822.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1822.h: 188: typedef union {
+[; ;pic12f1822.h: 189: struct {
+[; ;pic12f1822.h: 190: unsigned FSR0H :8;
+[; ;pic12f1822.h: 191: };
+[; ;pic12f1822.h: 192: } FSR0Hbits_t;
+[; ;pic12f1822.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1822.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1822.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1822.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1822.h: 210: typedef union {
+[; ;pic12f1822.h: 211: struct {
+[; ;pic12f1822.h: 212: unsigned FSR1L :8;
+[; ;pic12f1822.h: 213: };
+[; ;pic12f1822.h: 214: } FSR1Lbits_t;
+[; ;pic12f1822.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1822.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1822.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1822.h: 229: typedef union {
+[; ;pic12f1822.h: 230: struct {
+[; ;pic12f1822.h: 231: unsigned FSR1H :8;
+[; ;pic12f1822.h: 232: };
+[; ;pic12f1822.h: 233: } FSR1Hbits_t;
+[; ;pic12f1822.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1822.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1822.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1822.h: 248: typedef union {
+[; ;pic12f1822.h: 249: struct {
+[; ;pic12f1822.h: 250: unsigned BSR0 :1;
+[; ;pic12f1822.h: 251: unsigned BSR1 :1;
+[; ;pic12f1822.h: 252: unsigned BSR2 :1;
+[; ;pic12f1822.h: 253: unsigned BSR3 :1;
+[; ;pic12f1822.h: 254: unsigned BSR4 :1;
+[; ;pic12f1822.h: 255: };
+[; ;pic12f1822.h: 256: struct {
+[; ;pic12f1822.h: 257: unsigned BSR :5;
+[; ;pic12f1822.h: 258: };
+[; ;pic12f1822.h: 259: } BSRbits_t;
+[; ;pic12f1822.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1822.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1822.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1822.h: 299: typedef union {
+[; ;pic12f1822.h: 300: struct {
+[; ;pic12f1822.h: 301: unsigned WREG0 :8;
+[; ;pic12f1822.h: 302: };
+[; ;pic12f1822.h: 303: } WREGbits_t;
+[; ;pic12f1822.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1822.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1822.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1822.h: 318: typedef union {
+[; ;pic12f1822.h: 319: struct {
+[; ;pic12f1822.h: 320: unsigned PCLATH :7;
+[; ;pic12f1822.h: 321: };
+[; ;pic12f1822.h: 322: } PCLATHbits_t;
+[; ;pic12f1822.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1822.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1822.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1822.h: 337: typedef union {
+[; ;pic12f1822.h: 338: struct {
+[; ;pic12f1822.h: 339: unsigned IOCIF :1;
+[; ;pic12f1822.h: 340: unsigned INTF :1;
+[; ;pic12f1822.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1822.h: 342: unsigned IOCIE :1;
+[; ;pic12f1822.h: 343: unsigned INTE :1;
+[; ;pic12f1822.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1822.h: 345: unsigned PEIE :1;
+[; ;pic12f1822.h: 346: unsigned GIE :1;
+[; ;pic12f1822.h: 347: };
+[; ;pic12f1822.h: 348: struct {
+[; ;pic12f1822.h: 349: unsigned :2;
+[; ;pic12f1822.h: 350: unsigned T0IF :1;
+[; ;pic12f1822.h: 351: unsigned :2;
+[; ;pic12f1822.h: 352: unsigned T0IE :1;
+[; ;pic12f1822.h: 353: };
+[; ;pic12f1822.h: 354: } INTCONbits_t;
+[; ;pic12f1822.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1822.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1822.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1822.h: 414: typedef union {
+[; ;pic12f1822.h: 415: struct {
+[; ;pic12f1822.h: 416: unsigned RA0 :1;
+[; ;pic12f1822.h: 417: unsigned RA1 :1;
+[; ;pic12f1822.h: 418: unsigned RA2 :1;
+[; ;pic12f1822.h: 419: unsigned RA3 :1;
+[; ;pic12f1822.h: 420: unsigned RA4 :1;
+[; ;pic12f1822.h: 421: unsigned RA5 :1;
+[; ;pic12f1822.h: 422: };
+[; ;pic12f1822.h: 423: struct {
+[; ;pic12f1822.h: 424: unsigned AN0 :1;
+[; ;pic12f1822.h: 425: unsigned AN1 :1;
+[; ;pic12f1822.h: 426: unsigned AN2 :1;
+[; ;pic12f1822.h: 427: unsigned :1;
+[; ;pic12f1822.h: 428: unsigned AN3 :1;
+[; ;pic12f1822.h: 429: };
+[; ;pic12f1822.h: 430: struct {
+[; ;pic12f1822.h: 431: unsigned CPS0 :1;
+[; ;pic12f1822.h: 432: unsigned CPS1 :1;
+[; ;pic12f1822.h: 433: unsigned CPS2 :1;
+[; ;pic12f1822.h: 434: unsigned :1;
+[; ;pic12f1822.h: 435: unsigned CPS3 :1;
+[; ;pic12f1822.h: 436: };
+[; ;pic12f1822.h: 437: struct {
+[; ;pic12f1822.h: 438: unsigned C1INP :1;
+[; ;pic12f1822.h: 439: unsigned C1IN0N :1;
+[; ;pic12f1822.h: 440: unsigned C1OUT :1;
+[; ;pic12f1822.h: 441: unsigned :1;
+[; ;pic12f1822.h: 442: unsigned C1IN1N :1;
+[; ;pic12f1822.h: 443: };
+[; ;pic12f1822.h: 444: struct {
+[; ;pic12f1822.h: 445: unsigned DACOUT :1;
+[; ;pic12f1822.h: 446: unsigned SRI :1;
+[; ;pic12f1822.h: 447: unsigned SRQ :1;
+[; ;pic12f1822.h: 448: unsigned :2;
+[; ;pic12f1822.h: 449: unsigned SRNQ :1;
+[; ;pic12f1822.h: 450: };
+[; ;pic12f1822.h: 451: struct {
+[; ;pic12f1822.h: 452: unsigned :1;
+[; ;pic12f1822.h: 453: unsigned SCK :1;
+[; ;pic12f1822.h: 454: unsigned T0CKI :1;
+[; ;pic12f1822.h: 455: unsigned :1;
+[; ;pic12f1822.h: 456: unsigned T1OSO :1;
+[; ;pic12f1822.h: 457: unsigned T1CKI :1;
+[; ;pic12f1822.h: 458: };
+[; ;pic12f1822.h: 459: struct {
+[; ;pic12f1822.h: 460: unsigned :1;
+[; ;pic12f1822.h: 461: unsigned SCL :1;
+[; ;pic12f1822.h: 462: unsigned SDA :1;
+[; ;pic12f1822.h: 463: unsigned nMCLR :1;
+[; ;pic12f1822.h: 464: unsigned CLKR :1;
+[; ;pic12f1822.h: 465: unsigned T1OSI :1;
+[; ;pic12f1822.h: 466: };
+[; ;pic12f1822.h: 467: struct {
+[; ;pic12f1822.h: 468: unsigned MDOUT :1;
+[; ;pic12f1822.h: 469: unsigned MDMIN :1;
+[; ;pic12f1822.h: 470: unsigned MDCIN1 :1;
+[; ;pic12f1822.h: 471: unsigned :1;
+[; ;pic12f1822.h: 472: unsigned MDCIN2 :1;
+[; ;pic12f1822.h: 473: };
+[; ;pic12f1822.h: 474: struct {
+[; ;pic12f1822.h: 475: unsigned :2;
+[; ;pic12f1822.h: 476: unsigned SDI :1;
+[; ;pic12f1822.h: 477: unsigned :1;
+[; ;pic12f1822.h: 478: unsigned OSC2 :1;
+[; ;pic12f1822.h: 479: unsigned OSC1 :1;
+[; ;pic12f1822.h: 480: };
+[; ;pic12f1822.h: 481: struct {
+[; ;pic12f1822.h: 482: unsigned :2;
+[; ;pic12f1822.h: 483: unsigned FLT0 :1;
+[; ;pic12f1822.h: 484: unsigned :1;
+[; ;pic12f1822.h: 485: unsigned CLKOUT :1;
+[; ;pic12f1822.h: 486: unsigned CLKIN :1;
+[; ;pic12f1822.h: 487: };
+[; ;pic12f1822.h: 488: } PORTAbits_t;
+[; ;pic12f1822.h: 489: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1822.h: 698: extern volatile unsigned char PIR1 @ 0x011;
+"700
+[; ;pic12f1822.h: 700: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1822.h: 703: typedef union {
+[; ;pic12f1822.h: 704: struct {
+[; ;pic12f1822.h: 705: unsigned TMR1IF :1;
+[; ;pic12f1822.h: 706: unsigned TMR2IF :1;
+[; ;pic12f1822.h: 707: unsigned CCP1IF :1;
+[; ;pic12f1822.h: 708: unsigned SSP1IF :1;
+[; ;pic12f1822.h: 709: unsigned TXIF :1;
+[; ;pic12f1822.h: 710: unsigned RCIF :1;
+[; ;pic12f1822.h: 711: unsigned ADIF :1;
+[; ;pic12f1822.h: 712: unsigned TMR1GIF :1;
+[; ;pic12f1822.h: 713: };
+[; ;pic12f1822.h: 714: } PIR1bits_t;
+[; ;pic12f1822.h: 715: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1822.h: 759: extern volatile unsigned char PIR2 @ 0x012;
+"761
+[; ;pic12f1822.h: 761: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1822.h: 764: typedef union {
+[; ;pic12f1822.h: 765: struct {
+[; ;pic12f1822.h: 766: unsigned :3;
+[; ;pic12f1822.h: 767: unsigned BCL1IF :1;
+[; ;pic12f1822.h: 768: unsigned EEIF :1;
+[; ;pic12f1822.h: 769: unsigned C1IF :1;
+[; ;pic12f1822.h: 770: unsigned :1;
+[; ;pic12f1822.h: 771: unsigned OSFIF :1;
+[; ;pic12f1822.h: 772: };
+[; ;pic12f1822.h: 773: } PIR2bits_t;
+[; ;pic12f1822.h: 774: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1822.h: 798: extern volatile unsigned char TMR0 @ 0x015;
+"800
+[; ;pic12f1822.h: 800: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1822.h: 803: typedef union {
+[; ;pic12f1822.h: 804: struct {
+[; ;pic12f1822.h: 805: unsigned TMR0 :8;
+[; ;pic12f1822.h: 806: };
+[; ;pic12f1822.h: 807: } TMR0bits_t;
+[; ;pic12f1822.h: 808: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1822.h: 817: extern volatile unsigned short TMR1 @ 0x016;
+"819
+[; ;pic12f1822.h: 819: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1822.h: 823: extern volatile unsigned char TMR1L @ 0x016;
+"825
+[; ;pic12f1822.h: 825: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1822.h: 828: typedef union {
+[; ;pic12f1822.h: 829: struct {
+[; ;pic12f1822.h: 830: unsigned TMR1L :8;
+[; ;pic12f1822.h: 831: };
+[; ;pic12f1822.h: 832: } TMR1Lbits_t;
+[; ;pic12f1822.h: 833: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1822.h: 842: extern volatile unsigned char TMR1H @ 0x017;
+"844
+[; ;pic12f1822.h: 844: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1822.h: 847: typedef union {
+[; ;pic12f1822.h: 848: struct {
+[; ;pic12f1822.h: 849: unsigned TMR1H :8;
+[; ;pic12f1822.h: 850: };
+[; ;pic12f1822.h: 851: } TMR1Hbits_t;
+[; ;pic12f1822.h: 852: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1822.h: 861: extern volatile unsigned char T1CON @ 0x018;
+"863
+[; ;pic12f1822.h: 863: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1822.h: 866: typedef union {
+[; ;pic12f1822.h: 867: struct {
+[; ;pic12f1822.h: 868: unsigned TMR1ON :1;
+[; ;pic12f1822.h: 869: unsigned :1;
+[; ;pic12f1822.h: 870: unsigned nT1SYNC :1;
+[; ;pic12f1822.h: 871: unsigned T1OSCEN :1;
+[; ;pic12f1822.h: 872: unsigned T1CKPS0 :1;
+[; ;pic12f1822.h: 873: unsigned T1CKPS1 :1;
+[; ;pic12f1822.h: 874: unsigned TMR1CS0 :1;
+[; ;pic12f1822.h: 875: unsigned TMR1CS1 :1;
+[; ;pic12f1822.h: 876: };
+[; ;pic12f1822.h: 877: struct {
+[; ;pic12f1822.h: 878: unsigned :4;
+[; ;pic12f1822.h: 879: unsigned T1CKPS :2;
+[; ;pic12f1822.h: 880: unsigned TMR1CS :2;
+[; ;pic12f1822.h: 881: };
+[; ;pic12f1822.h: 882: } T1CONbits_t;
+[; ;pic12f1822.h: 883: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1822.h: 932: extern volatile unsigned char T1GCON @ 0x019;
+"934
+[; ;pic12f1822.h: 934: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1822.h: 937: typedef union {
+[; ;pic12f1822.h: 938: struct {
+[; ;pic12f1822.h: 939: unsigned T1GSS0 :1;
+[; ;pic12f1822.h: 940: unsigned T1GSS1 :1;
+[; ;pic12f1822.h: 941: unsigned T1GVAL :1;
+[; ;pic12f1822.h: 942: unsigned T1GGO_nDONE :1;
+[; ;pic12f1822.h: 943: unsigned T1GSPM :1;
+[; ;pic12f1822.h: 944: unsigned T1GTM :1;
+[; ;pic12f1822.h: 945: unsigned T1GPOL :1;
+[; ;pic12f1822.h: 946: unsigned TMR1GE :1;
+[; ;pic12f1822.h: 947: };
+[; ;pic12f1822.h: 948: struct {
+[; ;pic12f1822.h: 949: unsigned T1GSS :2;
+[; ;pic12f1822.h: 950: unsigned :1;
+[; ;pic12f1822.h: 951: unsigned T1GGO :1;
+[; ;pic12f1822.h: 952: };
+[; ;pic12f1822.h: 953: } T1GCONbits_t;
+[; ;pic12f1822.h: 954: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1822.h: 1008: extern volatile unsigned char TMR2 @ 0x01A;
+"1010
+[; ;pic12f1822.h: 1010: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1822.h: 1013: typedef union {
+[; ;pic12f1822.h: 1014: struct {
+[; ;pic12f1822.h: 1015: unsigned TMR2 :8;
+[; ;pic12f1822.h: 1016: };
+[; ;pic12f1822.h: 1017: } TMR2bits_t;
+[; ;pic12f1822.h: 1018: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1822.h: 1027: extern volatile unsigned char PR2 @ 0x01B;
+"1029
+[; ;pic12f1822.h: 1029: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1822.h: 1032: typedef union {
+[; ;pic12f1822.h: 1033: struct {
+[; ;pic12f1822.h: 1034: unsigned PR2 :8;
+[; ;pic12f1822.h: 1035: };
+[; ;pic12f1822.h: 1036: } PR2bits_t;
+[; ;pic12f1822.h: 1037: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1822.h: 1046: extern volatile unsigned char T2CON @ 0x01C;
+"1048
+[; ;pic12f1822.h: 1048: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1822.h: 1051: typedef union {
+[; ;pic12f1822.h: 1052: struct {
+[; ;pic12f1822.h: 1053: unsigned T2CKPS0 :1;
+[; ;pic12f1822.h: 1054: unsigned T2CKPS1 :1;
+[; ;pic12f1822.h: 1055: unsigned TMR2ON :1;
+[; ;pic12f1822.h: 1056: unsigned T2OUTPS0 :1;
+[; ;pic12f1822.h: 1057: unsigned T2OUTPS1 :1;
+[; ;pic12f1822.h: 1058: unsigned T2OUTPS2 :1;
+[; ;pic12f1822.h: 1059: unsigned T2OUTPS3 :1;
+[; ;pic12f1822.h: 1060: };
+[; ;pic12f1822.h: 1061: struct {
+[; ;pic12f1822.h: 1062: unsigned T2CKPS :2;
+[; ;pic12f1822.h: 1063: unsigned :1;
+[; ;pic12f1822.h: 1064: unsigned T2OUTPS :4;
+[; ;pic12f1822.h: 1065: };
+[; ;pic12f1822.h: 1066: } T2CONbits_t;
+[; ;pic12f1822.h: 1067: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1822.h: 1116: extern volatile unsigned char CPSCON0 @ 0x01E;
+"1118
+[; ;pic12f1822.h: 1118: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1822.h: 1121: typedef union {
+[; ;pic12f1822.h: 1122: struct {
+[; ;pic12f1822.h: 1123: unsigned T0XCS :1;
+[; ;pic12f1822.h: 1124: unsigned CPSOUT :1;
+[; ;pic12f1822.h: 1125: unsigned CPSRNG0 :1;
+[; ;pic12f1822.h: 1126: unsigned CPSRNG1 :1;
+[; ;pic12f1822.h: 1127: unsigned :2;
+[; ;pic12f1822.h: 1128: unsigned CPSRM :1;
+[; ;pic12f1822.h: 1129: unsigned CPSON :1;
+[; ;pic12f1822.h: 1130: };
+[; ;pic12f1822.h: 1131: struct {
+[; ;pic12f1822.h: 1132: unsigned :2;
+[; ;pic12f1822.h: 1133: unsigned CPSRNG :2;
+[; ;pic12f1822.h: 1134: };
+[; ;pic12f1822.h: 1135: } CPSCON0bits_t;
+[; ;pic12f1822.h: 1136: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1822.h: 1175: extern volatile unsigned char CPSCON1 @ 0x01F;
+"1177
+[; ;pic12f1822.h: 1177: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1822.h: 1180: typedef union {
+[; ;pic12f1822.h: 1181: struct {
+[; ;pic12f1822.h: 1182: unsigned CPSCH0 :1;
+[; ;pic12f1822.h: 1183: unsigned CPSCH1 :1;
+[; ;pic12f1822.h: 1184: };
+[; ;pic12f1822.h: 1185: struct {
+[; ;pic12f1822.h: 1186: unsigned CPSCH :2;
+[; ;pic12f1822.h: 1187: };
+[; ;pic12f1822.h: 1188: } CPSCON1bits_t;
+[; ;pic12f1822.h: 1189: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1822.h: 1208: extern volatile unsigned char TRISA @ 0x08C;
+"1210
+[; ;pic12f1822.h: 1210: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1822.h: 1213: typedef union {
+[; ;pic12f1822.h: 1214: struct {
+[; ;pic12f1822.h: 1215: unsigned TRISA0 :1;
+[; ;pic12f1822.h: 1216: unsigned TRISA1 :1;
+[; ;pic12f1822.h: 1217: unsigned TRISA2 :1;
+[; ;pic12f1822.h: 1218: unsigned TRISA3 :1;
+[; ;pic12f1822.h: 1219: unsigned TRISA4 :1;
+[; ;pic12f1822.h: 1220: unsigned TRISA5 :1;
+[; ;pic12f1822.h: 1221: };
+[; ;pic12f1822.h: 1222: } TRISAbits_t;
+[; ;pic12f1822.h: 1223: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1822.h: 1257: extern volatile unsigned char PIE1 @ 0x091;
+"1259
+[; ;pic12f1822.h: 1259: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1822.h: 1262: typedef union {
+[; ;pic12f1822.h: 1263: struct {
+[; ;pic12f1822.h: 1264: unsigned TMR1IE :1;
+[; ;pic12f1822.h: 1265: unsigned TMR2IE :1;
+[; ;pic12f1822.h: 1266: unsigned CCP1IE :1;
+[; ;pic12f1822.h: 1267: unsigned SSP1IE :1;
+[; ;pic12f1822.h: 1268: unsigned TXIE :1;
+[; ;pic12f1822.h: 1269: unsigned RCIE :1;
+[; ;pic12f1822.h: 1270: unsigned ADIE :1;
+[; ;pic12f1822.h: 1271: unsigned TMR1GIE :1;
+[; ;pic12f1822.h: 1272: };
+[; ;pic12f1822.h: 1273: } PIE1bits_t;
+[; ;pic12f1822.h: 1274: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1822.h: 1318: extern volatile unsigned char PIE2 @ 0x092;
+"1320
+[; ;pic12f1822.h: 1320: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1822.h: 1323: typedef union {
+[; ;pic12f1822.h: 1324: struct {
+[; ;pic12f1822.h: 1325: unsigned :3;
+[; ;pic12f1822.h: 1326: unsigned BCL1IE :1;
+[; ;pic12f1822.h: 1327: unsigned EEIE :1;
+[; ;pic12f1822.h: 1328: unsigned C1IE :1;
+[; ;pic12f1822.h: 1329: unsigned :1;
+[; ;pic12f1822.h: 1330: unsigned OSFIE :1;
+[; ;pic12f1822.h: 1331: };
+[; ;pic12f1822.h: 1332: } PIE2bits_t;
+[; ;pic12f1822.h: 1333: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1822.h: 1357: extern volatile unsigned char OPTION_REG @ 0x095;
+"1359
+[; ;pic12f1822.h: 1359: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1822.h: 1362: typedef union {
+[; ;pic12f1822.h: 1363: struct {
+[; ;pic12f1822.h: 1364: unsigned PS0 :1;
+[; ;pic12f1822.h: 1365: unsigned PS1 :1;
+[; ;pic12f1822.h: 1366: unsigned PS2 :1;
+[; ;pic12f1822.h: 1367: unsigned PSA :1;
+[; ;pic12f1822.h: 1368: unsigned TMR0SE :1;
+[; ;pic12f1822.h: 1369: unsigned TMR0CS :1;
+[; ;pic12f1822.h: 1370: unsigned INTEDG :1;
+[; ;pic12f1822.h: 1371: unsigned nWPUEN :1;
+[; ;pic12f1822.h: 1372: };
+[; ;pic12f1822.h: 1373: struct {
+[; ;pic12f1822.h: 1374: unsigned PS :3;
+[; ;pic12f1822.h: 1375: unsigned :1;
+[; ;pic12f1822.h: 1376: unsigned T0SE :1;
+[; ;pic12f1822.h: 1377: unsigned T0CS :1;
+[; ;pic12f1822.h: 1378: };
+[; ;pic12f1822.h: 1379: } OPTION_REGbits_t;
+[; ;pic12f1822.h: 1380: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1822.h: 1439: extern volatile unsigned char PCON @ 0x096;
+"1441
+[; ;pic12f1822.h: 1441: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1822.h: 1444: typedef union {
+[; ;pic12f1822.h: 1445: struct {
+[; ;pic12f1822.h: 1446: unsigned nBOR :1;
+[; ;pic12f1822.h: 1447: unsigned nPOR :1;
+[; ;pic12f1822.h: 1448: unsigned nRI :1;
+[; ;pic12f1822.h: 1449: unsigned nRMCLR :1;
+[; ;pic12f1822.h: 1450: unsigned :2;
+[; ;pic12f1822.h: 1451: unsigned STKUNF :1;
+[; ;pic12f1822.h: 1452: unsigned STKOVF :1;
+[; ;pic12f1822.h: 1453: };
+[; ;pic12f1822.h: 1454: } PCONbits_t;
+[; ;pic12f1822.h: 1455: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1822.h: 1489: extern volatile unsigned char WDTCON @ 0x097;
+"1491
+[; ;pic12f1822.h: 1491: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1822.h: 1494: typedef union {
+[; ;pic12f1822.h: 1495: struct {
+[; ;pic12f1822.h: 1496: unsigned SWDTEN :1;
+[; ;pic12f1822.h: 1497: unsigned WDTPS0 :1;
+[; ;pic12f1822.h: 1498: unsigned WDTPS1 :1;
+[; ;pic12f1822.h: 1499: unsigned WDTPS2 :1;
+[; ;pic12f1822.h: 1500: unsigned WDTPS3 :1;
+[; ;pic12f1822.h: 1501: unsigned WDTPS4 :1;
+[; ;pic12f1822.h: 1502: };
+[; ;pic12f1822.h: 1503: struct {
+[; ;pic12f1822.h: 1504: unsigned :1;
+[; ;pic12f1822.h: 1505: unsigned WDTPS :5;
+[; ;pic12f1822.h: 1506: };
+[; ;pic12f1822.h: 1507: } WDTCONbits_t;
+[; ;pic12f1822.h: 1508: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1822.h: 1547: extern volatile unsigned char OSCTUNE @ 0x098;
+"1549
+[; ;pic12f1822.h: 1549: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1822.h: 1552: typedef union {
+[; ;pic12f1822.h: 1553: struct {
+[; ;pic12f1822.h: 1554: unsigned TUN0 :1;
+[; ;pic12f1822.h: 1555: unsigned TUN1 :1;
+[; ;pic12f1822.h: 1556: unsigned TUN2 :1;
+[; ;pic12f1822.h: 1557: unsigned TUN3 :1;
+[; ;pic12f1822.h: 1558: unsigned TUN4 :1;
+[; ;pic12f1822.h: 1559: unsigned TUN5 :1;
+[; ;pic12f1822.h: 1560: };
+[; ;pic12f1822.h: 1561: struct {
+[; ;pic12f1822.h: 1562: unsigned TUN :6;
+[; ;pic12f1822.h: 1563: };
+[; ;pic12f1822.h: 1564: } OSCTUNEbits_t;
+[; ;pic12f1822.h: 1565: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1822.h: 1604: extern volatile unsigned char OSCCON @ 0x099;
+"1606
+[; ;pic12f1822.h: 1606: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1822.h: 1609: typedef union {
+[; ;pic12f1822.h: 1610: struct {
+[; ;pic12f1822.h: 1611: unsigned SCS0 :1;
+[; ;pic12f1822.h: 1612: unsigned SCS1 :1;
+[; ;pic12f1822.h: 1613: unsigned :1;
+[; ;pic12f1822.h: 1614: unsigned IRCF0 :1;
+[; ;pic12f1822.h: 1615: unsigned IRCF1 :1;
+[; ;pic12f1822.h: 1616: unsigned IRCF2 :1;
+[; ;pic12f1822.h: 1617: unsigned IRCF3 :1;
+[; ;pic12f1822.h: 1618: unsigned SPLLEN :1;
+[; ;pic12f1822.h: 1619: };
+[; ;pic12f1822.h: 1620: struct {
+[; ;pic12f1822.h: 1621: unsigned SCS :2;
+[; ;pic12f1822.h: 1622: unsigned :1;
+[; ;pic12f1822.h: 1623: unsigned IRCF :4;
+[; ;pic12f1822.h: 1624: };
+[; ;pic12f1822.h: 1625: } OSCCONbits_t;
+[; ;pic12f1822.h: 1626: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1822.h: 1675: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1677
+[; ;pic12f1822.h: 1677: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1822.h: 1680: typedef union {
+[; ;pic12f1822.h: 1681: struct {
+[; ;pic12f1822.h: 1682: unsigned HFIOFS :1;
+[; ;pic12f1822.h: 1683: unsigned LFIOFR :1;
+[; ;pic12f1822.h: 1684: unsigned MFIOFR :1;
+[; ;pic12f1822.h: 1685: unsigned HFIOFL :1;
+[; ;pic12f1822.h: 1686: unsigned HFIOFR :1;
+[; ;pic12f1822.h: 1687: unsigned OSTS :1;
+[; ;pic12f1822.h: 1688: unsigned PLLR :1;
+[; ;pic12f1822.h: 1689: unsigned T1OSCR :1;
+[; ;pic12f1822.h: 1690: };
+[; ;pic12f1822.h: 1691: } OSCSTATbits_t;
+[; ;pic12f1822.h: 1692: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1822.h: 1736: extern volatile unsigned short ADRES @ 0x09B;
+"1738
+[; ;pic12f1822.h: 1738: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1822.h: 1742: extern volatile unsigned char ADRESL @ 0x09B;
+"1744
+[; ;pic12f1822.h: 1744: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1822.h: 1747: typedef union {
+[; ;pic12f1822.h: 1748: struct {
+[; ;pic12f1822.h: 1749: unsigned ADRESL :8;
+[; ;pic12f1822.h: 1750: };
+[; ;pic12f1822.h: 1751: } ADRESLbits_t;
+[; ;pic12f1822.h: 1752: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1822.h: 1761: extern volatile unsigned char ADRESH @ 0x09C;
+"1763
+[; ;pic12f1822.h: 1763: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1822.h: 1766: typedef union {
+[; ;pic12f1822.h: 1767: struct {
+[; ;pic12f1822.h: 1768: unsigned ADRESH :8;
+[; ;pic12f1822.h: 1769: };
+[; ;pic12f1822.h: 1770: } ADRESHbits_t;
+[; ;pic12f1822.h: 1771: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1822.h: 1780: extern volatile unsigned char ADCON0 @ 0x09D;
+"1782
+[; ;pic12f1822.h: 1782: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1822.h: 1785: typedef union {
+[; ;pic12f1822.h: 1786: struct {
+[; ;pic12f1822.h: 1787: unsigned ADON :1;
+[; ;pic12f1822.h: 1788: unsigned GO_nDONE :1;
+[; ;pic12f1822.h: 1789: unsigned CHS0 :1;
+[; ;pic12f1822.h: 1790: unsigned CHS1 :1;
+[; ;pic12f1822.h: 1791: unsigned CHS2 :1;
+[; ;pic12f1822.h: 1792: unsigned CHS3 :1;
+[; ;pic12f1822.h: 1793: unsigned CHS4 :1;
+[; ;pic12f1822.h: 1794: };
+[; ;pic12f1822.h: 1795: struct {
+[; ;pic12f1822.h: 1796: unsigned :1;
+[; ;pic12f1822.h: 1797: unsigned ADGO :1;
+[; ;pic12f1822.h: 1798: unsigned CHS :5;
+[; ;pic12f1822.h: 1799: };
+[; ;pic12f1822.h: 1800: struct {
+[; ;pic12f1822.h: 1801: unsigned :1;
+[; ;pic12f1822.h: 1802: unsigned GO :1;
+[; ;pic12f1822.h: 1803: };
+[; ;pic12f1822.h: 1804: struct {
+[; ;pic12f1822.h: 1805: unsigned :1;
+[; ;pic12f1822.h: 1806: unsigned nDONE :1;
+[; ;pic12f1822.h: 1807: };
+[; ;pic12f1822.h: 1808: } ADCON0bits_t;
+[; ;pic12f1822.h: 1809: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1822.h: 1868: extern volatile unsigned char ADCON1 @ 0x09E;
+"1870
+[; ;pic12f1822.h: 1870: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1822.h: 1873: typedef union {
+[; ;pic12f1822.h: 1874: struct {
+[; ;pic12f1822.h: 1875: unsigned ADPREF0 :1;
+[; ;pic12f1822.h: 1876: unsigned ADPREF1 :1;
+[; ;pic12f1822.h: 1877: unsigned :2;
+[; ;pic12f1822.h: 1878: unsigned ADCS0 :1;
+[; ;pic12f1822.h: 1879: unsigned ADCS1 :1;
+[; ;pic12f1822.h: 1880: unsigned ADCS2 :1;
+[; ;pic12f1822.h: 1881: unsigned ADFM :1;
+[; ;pic12f1822.h: 1882: };
+[; ;pic12f1822.h: 1883: struct {
+[; ;pic12f1822.h: 1884: unsigned ADPREF :2;
+[; ;pic12f1822.h: 1885: unsigned :2;
+[; ;pic12f1822.h: 1886: unsigned ADCS :3;
+[; ;pic12f1822.h: 1887: };
+[; ;pic12f1822.h: 1888: } ADCON1bits_t;
+[; ;pic12f1822.h: 1889: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1822.h: 1933: extern volatile unsigned char LATA @ 0x10C;
+"1935
+[; ;pic12f1822.h: 1935: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1822.h: 1938: typedef union {
+[; ;pic12f1822.h: 1939: struct {
+[; ;pic12f1822.h: 1940: unsigned LATA0 :1;
+[; ;pic12f1822.h: 1941: unsigned LATA1 :1;
+[; ;pic12f1822.h: 1942: unsigned LATA2 :1;
+[; ;pic12f1822.h: 1943: unsigned :1;
+[; ;pic12f1822.h: 1944: unsigned LATA4 :1;
+[; ;pic12f1822.h: 1945: unsigned LATA5 :1;
+[; ;pic12f1822.h: 1946: };
+[; ;pic12f1822.h: 1947: } LATAbits_t;
+[; ;pic12f1822.h: 1948: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1822.h: 1977: extern volatile unsigned char CM1CON0 @ 0x111;
+"1979
+[; ;pic12f1822.h: 1979: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1822.h: 1982: typedef union {
+[; ;pic12f1822.h: 1983: struct {
+[; ;pic12f1822.h: 1984: unsigned C1SYNC :1;
+[; ;pic12f1822.h: 1985: unsigned C1HYS :1;
+[; ;pic12f1822.h: 1986: unsigned C1SP :1;
+[; ;pic12f1822.h: 1987: unsigned :1;
+[; ;pic12f1822.h: 1988: unsigned C1POL :1;
+[; ;pic12f1822.h: 1989: unsigned C1OE :1;
+[; ;pic12f1822.h: 1990: unsigned C1OUT :1;
+[; ;pic12f1822.h: 1991: unsigned C1ON :1;
+[; ;pic12f1822.h: 1992: };
+[; ;pic12f1822.h: 1993: } CM1CON0bits_t;
+[; ;pic12f1822.h: 1994: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1822.h: 2033: extern volatile unsigned char CM1CON1 @ 0x112;
+"2035
+[; ;pic12f1822.h: 2035: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1822.h: 2038: typedef union {
+[; ;pic12f1822.h: 2039: struct {
+[; ;pic12f1822.h: 2040: unsigned C1NCH0 :1;
+[; ;pic12f1822.h: 2041: unsigned :3;
+[; ;pic12f1822.h: 2042: unsigned C1PCH0 :1;
+[; ;pic12f1822.h: 2043: unsigned C1PCH1 :1;
+[; ;pic12f1822.h: 2044: unsigned C1INTN :1;
+[; ;pic12f1822.h: 2045: unsigned C1INTP :1;
+[; ;pic12f1822.h: 2046: };
+[; ;pic12f1822.h: 2047: struct {
+[; ;pic12f1822.h: 2048: unsigned :4;
+[; ;pic12f1822.h: 2049: unsigned C1PCH :2;
+[; ;pic12f1822.h: 2050: };
+[; ;pic12f1822.h: 2051: } CM1CON1bits_t;
+[; ;pic12f1822.h: 2052: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1822.h: 2086: extern volatile unsigned char CMOUT @ 0x115;
+"2088
+[; ;pic12f1822.h: 2088: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1822.h: 2091: typedef union {
+[; ;pic12f1822.h: 2092: struct {
+[; ;pic12f1822.h: 2093: unsigned MC1OUT :1;
+[; ;pic12f1822.h: 2094: };
+[; ;pic12f1822.h: 2095: } CMOUTbits_t;
+[; ;pic12f1822.h: 2096: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1822.h: 2105: extern volatile unsigned char BORCON @ 0x116;
+"2107
+[; ;pic12f1822.h: 2107: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1822.h: 2110: typedef union {
+[; ;pic12f1822.h: 2111: struct {
+[; ;pic12f1822.h: 2112: unsigned BORRDY :1;
+[; ;pic12f1822.h: 2113: unsigned :6;
+[; ;pic12f1822.h: 2114: unsigned SBOREN :1;
+[; ;pic12f1822.h: 2115: };
+[; ;pic12f1822.h: 2116: } BORCONbits_t;
+[; ;pic12f1822.h: 2117: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1822.h: 2131: extern volatile unsigned char FVRCON @ 0x117;
+"2133
+[; ;pic12f1822.h: 2133: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1822.h: 2136: typedef union {
+[; ;pic12f1822.h: 2137: struct {
+[; ;pic12f1822.h: 2138: unsigned ADFVR0 :1;
+[; ;pic12f1822.h: 2139: unsigned ADFVR1 :1;
+[; ;pic12f1822.h: 2140: unsigned CDAFVR0 :1;
+[; ;pic12f1822.h: 2141: unsigned CDAFVR1 :1;
+[; ;pic12f1822.h: 2142: unsigned TSRNG :1;
+[; ;pic12f1822.h: 2143: unsigned TSEN :1;
+[; ;pic12f1822.h: 2144: unsigned FVRRDY :1;
+[; ;pic12f1822.h: 2145: unsigned FVREN :1;
+[; ;pic12f1822.h: 2146: };
+[; ;pic12f1822.h: 2147: struct {
+[; ;pic12f1822.h: 2148: unsigned ADFVR :2;
+[; ;pic12f1822.h: 2149: unsigned CDAFVR :2;
+[; ;pic12f1822.h: 2150: };
+[; ;pic12f1822.h: 2151: } FVRCONbits_t;
+[; ;pic12f1822.h: 2152: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1822.h: 2206: extern volatile unsigned char DACCON0 @ 0x118;
+"2208
+[; ;pic12f1822.h: 2208: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1822.h: 2211: typedef union {
+[; ;pic12f1822.h: 2212: struct {
+[; ;pic12f1822.h: 2213: unsigned :2;
+[; ;pic12f1822.h: 2214: unsigned DACPSS0 :1;
+[; ;pic12f1822.h: 2215: unsigned DACPSS1 :1;
+[; ;pic12f1822.h: 2216: unsigned :1;
+[; ;pic12f1822.h: 2217: unsigned DACOE :1;
+[; ;pic12f1822.h: 2218: unsigned DACLPS :1;
+[; ;pic12f1822.h: 2219: unsigned DACEN :1;
+[; ;pic12f1822.h: 2220: };
+[; ;pic12f1822.h: 2221: struct {
+[; ;pic12f1822.h: 2222: unsigned :2;
+[; ;pic12f1822.h: 2223: unsigned DACPSS :2;
+[; ;pic12f1822.h: 2224: };
+[; ;pic12f1822.h: 2225: } DACCON0bits_t;
+[; ;pic12f1822.h: 2226: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1822.h: 2260: extern volatile unsigned char DACCON1 @ 0x119;
+"2262
+[; ;pic12f1822.h: 2262: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1822.h: 2265: typedef union {
+[; ;pic12f1822.h: 2266: struct {
+[; ;pic12f1822.h: 2267: unsigned DACR0 :1;
+[; ;pic12f1822.h: 2268: unsigned DACR1 :1;
+[; ;pic12f1822.h: 2269: unsigned DACR2 :1;
+[; ;pic12f1822.h: 2270: unsigned DACR3 :1;
+[; ;pic12f1822.h: 2271: unsigned DACR4 :1;
+[; ;pic12f1822.h: 2272: };
+[; ;pic12f1822.h: 2273: struct {
+[; ;pic12f1822.h: 2274: unsigned DACR :5;
+[; ;pic12f1822.h: 2275: };
+[; ;pic12f1822.h: 2276: } DACCON1bits_t;
+[; ;pic12f1822.h: 2277: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1822.h: 2311: extern volatile unsigned char SRCON0 @ 0x11A;
+"2313
+[; ;pic12f1822.h: 2313: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1822.h: 2316: typedef union {
+[; ;pic12f1822.h: 2317: struct {
+[; ;pic12f1822.h: 2318: unsigned SRPR :1;
+[; ;pic12f1822.h: 2319: unsigned SRPS :1;
+[; ;pic12f1822.h: 2320: unsigned SRNQEN :1;
+[; ;pic12f1822.h: 2321: unsigned SRQEN :1;
+[; ;pic12f1822.h: 2322: unsigned SRCLK0 :1;
+[; ;pic12f1822.h: 2323: unsigned SRCLK1 :1;
+[; ;pic12f1822.h: 2324: unsigned SRCLK2 :1;
+[; ;pic12f1822.h: 2325: unsigned SRLEN :1;
+[; ;pic12f1822.h: 2326: };
+[; ;pic12f1822.h: 2327: struct {
+[; ;pic12f1822.h: 2328: unsigned :4;
+[; ;pic12f1822.h: 2329: unsigned SRCLK :3;
+[; ;pic12f1822.h: 2330: };
+[; ;pic12f1822.h: 2331: } SRCON0bits_t;
+[; ;pic12f1822.h: 2332: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1822.h: 2381: extern volatile unsigned char SRCON1 @ 0x11B;
+"2383
+[; ;pic12f1822.h: 2383: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1822.h: 2386: typedef union {
+[; ;pic12f1822.h: 2387: struct {
+[; ;pic12f1822.h: 2388: unsigned SRRC1E :1;
+[; ;pic12f1822.h: 2389: unsigned :1;
+[; ;pic12f1822.h: 2390: unsigned SRRCKE :1;
+[; ;pic12f1822.h: 2391: unsigned SRRPE :1;
+[; ;pic12f1822.h: 2392: unsigned SRSC1E :1;
+[; ;pic12f1822.h: 2393: unsigned :1;
+[; ;pic12f1822.h: 2394: unsigned SRSCKE :1;
+[; ;pic12f1822.h: 2395: unsigned SRSPE :1;
+[; ;pic12f1822.h: 2396: };
+[; ;pic12f1822.h: 2397: } SRCON1bits_t;
+[; ;pic12f1822.h: 2398: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1822.h: 2432: extern volatile unsigned char APFCON @ 0x11D;
+"2434
+[; ;pic12f1822.h: 2434: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1822.h: 2437: extern volatile unsigned char APFCON0 @ 0x11D;
+"2439
+[; ;pic12f1822.h: 2439: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1822.h: 2442: typedef union {
+[; ;pic12f1822.h: 2443: struct {
+[; ;pic12f1822.h: 2444: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2445: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2446: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2447: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2448: unsigned :1;
+[; ;pic12f1822.h: 2449: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2450: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2451: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2452: };
+[; ;pic12f1822.h: 2453: struct {
+[; ;pic12f1822.h: 2454: unsigned :5;
+[; ;pic12f1822.h: 2455: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2456: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2457: };
+[; ;pic12f1822.h: 2458: } APFCONbits_t;
+[; ;pic12f1822.h: 2459: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1822.h: 2507: typedef union {
+[; ;pic12f1822.h: 2508: struct {
+[; ;pic12f1822.h: 2509: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2510: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2511: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2512: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2513: unsigned :1;
+[; ;pic12f1822.h: 2514: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2515: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2516: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2517: };
+[; ;pic12f1822.h: 2518: struct {
+[; ;pic12f1822.h: 2519: unsigned :5;
+[; ;pic12f1822.h: 2520: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2521: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2522: };
+[; ;pic12f1822.h: 2523: } APFCON0bits_t;
+[; ;pic12f1822.h: 2524: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1822.h: 2573: extern volatile unsigned char ANSELA @ 0x18C;
+"2575
+[; ;pic12f1822.h: 2575: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1822.h: 2578: typedef union {
+[; ;pic12f1822.h: 2579: struct {
+[; ;pic12f1822.h: 2580: unsigned ANSA0 :1;
+[; ;pic12f1822.h: 2581: unsigned ANSA1 :1;
+[; ;pic12f1822.h: 2582: unsigned ANSA2 :1;
+[; ;pic12f1822.h: 2583: unsigned :1;
+[; ;pic12f1822.h: 2584: unsigned ANSA4 :1;
+[; ;pic12f1822.h: 2585: };
+[; ;pic12f1822.h: 2586: struct {
+[; ;pic12f1822.h: 2587: unsigned ANSELA :5;
+[; ;pic12f1822.h: 2588: };
+[; ;pic12f1822.h: 2589: } ANSELAbits_t;
+[; ;pic12f1822.h: 2590: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1822.h: 2619: extern volatile unsigned short EEADR @ 0x191;
+"2621
+[; ;pic12f1822.h: 2621: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1822.h: 2625: extern volatile unsigned char EEADRL @ 0x191;
+"2627
+[; ;pic12f1822.h: 2627: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1822.h: 2630: typedef union {
+[; ;pic12f1822.h: 2631: struct {
+[; ;pic12f1822.h: 2632: unsigned EEADRL :8;
+[; ;pic12f1822.h: 2633: };
+[; ;pic12f1822.h: 2634: } EEADRLbits_t;
+[; ;pic12f1822.h: 2635: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1822.h: 2644: extern volatile unsigned char EEADRH @ 0x192;
+"2646
+[; ;pic12f1822.h: 2646: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1822.h: 2649: typedef union {
+[; ;pic12f1822.h: 2650: struct {
+[; ;pic12f1822.h: 2651: unsigned EEADRH :7;
+[; ;pic12f1822.h: 2652: };
+[; ;pic12f1822.h: 2653: } EEADRHbits_t;
+[; ;pic12f1822.h: 2654: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1822.h: 2663: extern volatile unsigned short EEDAT @ 0x193;
+"2665
+[; ;pic12f1822.h: 2665: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1822.h: 2669: extern volatile unsigned char EEDATL @ 0x193;
+"2671
+[; ;pic12f1822.h: 2671: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1822.h: 2674: extern volatile unsigned char EEDATA @ 0x193;
+"2676
+[; ;pic12f1822.h: 2676: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1822.h: 2679: typedef union {
+[; ;pic12f1822.h: 2680: struct {
+[; ;pic12f1822.h: 2681: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2682: };
+[; ;pic12f1822.h: 2683: } EEDATLbits_t;
+[; ;pic12f1822.h: 2684: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1822.h: 2692: typedef union {
+[; ;pic12f1822.h: 2693: struct {
+[; ;pic12f1822.h: 2694: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2695: };
+[; ;pic12f1822.h: 2696: } EEDATAbits_t;
+[; ;pic12f1822.h: 2697: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1822.h: 2706: extern volatile unsigned char EEDATH @ 0x194;
+"2708
+[; ;pic12f1822.h: 2708: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1822.h: 2711: typedef union {
+[; ;pic12f1822.h: 2712: struct {
+[; ;pic12f1822.h: 2713: unsigned EEDATH :6;
+[; ;pic12f1822.h: 2714: };
+[; ;pic12f1822.h: 2715: } EEDATHbits_t;
+[; ;pic12f1822.h: 2716: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1822.h: 2725: extern volatile unsigned char EECON1 @ 0x195;
+"2727
+[; ;pic12f1822.h: 2727: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1822.h: 2730: typedef union {
+[; ;pic12f1822.h: 2731: struct {
+[; ;pic12f1822.h: 2732: unsigned RD :1;
+[; ;pic12f1822.h: 2733: unsigned WR :1;
+[; ;pic12f1822.h: 2734: unsigned WREN :1;
+[; ;pic12f1822.h: 2735: unsigned WRERR :1;
+[; ;pic12f1822.h: 2736: unsigned FREE :1;
+[; ;pic12f1822.h: 2737: unsigned LWLO :1;
+[; ;pic12f1822.h: 2738: unsigned CFGS :1;
+[; ;pic12f1822.h: 2739: unsigned EEPGD :1;
+[; ;pic12f1822.h: 2740: };
+[; ;pic12f1822.h: 2741: } EECON1bits_t;
+[; ;pic12f1822.h: 2742: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1822.h: 2786: extern volatile unsigned char EECON2 @ 0x196;
+"2788
+[; ;pic12f1822.h: 2788: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1822.h: 2791: typedef union {
+[; ;pic12f1822.h: 2792: struct {
+[; ;pic12f1822.h: 2793: unsigned EECON2 :8;
+[; ;pic12f1822.h: 2794: };
+[; ;pic12f1822.h: 2795: } EECON2bits_t;
+[; ;pic12f1822.h: 2796: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1822.h: 2805: extern volatile unsigned char RCREG @ 0x199;
+"2807
+[; ;pic12f1822.h: 2807: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1822.h: 2810: typedef union {
+[; ;pic12f1822.h: 2811: struct {
+[; ;pic12f1822.h: 2812: unsigned RCREG :8;
+[; ;pic12f1822.h: 2813: };
+[; ;pic12f1822.h: 2814: } RCREGbits_t;
+[; ;pic12f1822.h: 2815: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1822.h: 2824: extern volatile unsigned char TXREG @ 0x19A;
+"2826
+[; ;pic12f1822.h: 2826: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1822.h: 2829: typedef union {
+[; ;pic12f1822.h: 2830: struct {
+[; ;pic12f1822.h: 2831: unsigned TXREG :8;
+[; ;pic12f1822.h: 2832: };
+[; ;pic12f1822.h: 2833: } TXREGbits_t;
+[; ;pic12f1822.h: 2834: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1822.h: 2843: extern volatile unsigned char SPBRGL @ 0x19B;
+"2845
+[; ;pic12f1822.h: 2845: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1822.h: 2848: extern volatile unsigned char SPBRG @ 0x19B;
+"2850
+[; ;pic12f1822.h: 2850: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1822.h: 2853: typedef union {
+[; ;pic12f1822.h: 2854: struct {
+[; ;pic12f1822.h: 2855: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2856: };
+[; ;pic12f1822.h: 2857: } SPBRGLbits_t;
+[; ;pic12f1822.h: 2858: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1822.h: 2866: typedef union {
+[; ;pic12f1822.h: 2867: struct {
+[; ;pic12f1822.h: 2868: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2869: };
+[; ;pic12f1822.h: 2870: } SPBRGbits_t;
+[; ;pic12f1822.h: 2871: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1822.h: 2880: extern volatile unsigned char SPBRGH @ 0x19C;
+"2882
+[; ;pic12f1822.h: 2882: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1822.h: 2885: typedef union {
+[; ;pic12f1822.h: 2886: struct {
+[; ;pic12f1822.h: 2887: unsigned SPBRGH :8;
+[; ;pic12f1822.h: 2888: };
+[; ;pic12f1822.h: 2889: } SPBRGHbits_t;
+[; ;pic12f1822.h: 2890: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1822.h: 2899: extern volatile unsigned char RCSTA @ 0x19D;
+"2901
+[; ;pic12f1822.h: 2901: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1822.h: 2904: typedef union {
+[; ;pic12f1822.h: 2905: struct {
+[; ;pic12f1822.h: 2906: unsigned RX9D :1;
+[; ;pic12f1822.h: 2907: unsigned OERR :1;
+[; ;pic12f1822.h: 2908: unsigned FERR :1;
+[; ;pic12f1822.h: 2909: unsigned ADDEN :1;
+[; ;pic12f1822.h: 2910: unsigned CREN :1;
+[; ;pic12f1822.h: 2911: unsigned SREN :1;
+[; ;pic12f1822.h: 2912: unsigned RX9 :1;
+[; ;pic12f1822.h: 2913: unsigned SPEN :1;
+[; ;pic12f1822.h: 2914: };
+[; ;pic12f1822.h: 2915: } RCSTAbits_t;
+[; ;pic12f1822.h: 2916: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1822.h: 2960: extern volatile unsigned char TXSTA @ 0x19E;
+"2962
+[; ;pic12f1822.h: 2962: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1822.h: 2965: typedef union {
+[; ;pic12f1822.h: 2966: struct {
+[; ;pic12f1822.h: 2967: unsigned TX9D :1;
+[; ;pic12f1822.h: 2968: unsigned TRMT :1;
+[; ;pic12f1822.h: 2969: unsigned BRGH :1;
+[; ;pic12f1822.h: 2970: unsigned SENDB :1;
+[; ;pic12f1822.h: 2971: unsigned SYNC :1;
+[; ;pic12f1822.h: 2972: unsigned TXEN :1;
+[; ;pic12f1822.h: 2973: unsigned TX9 :1;
+[; ;pic12f1822.h: 2974: unsigned CSRC :1;
+[; ;pic12f1822.h: 2975: };
+[; ;pic12f1822.h: 2976: } TXSTAbits_t;
+[; ;pic12f1822.h: 2977: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1822.h: 3021: extern volatile unsigned char BAUDCON @ 0x19F;
+"3023
+[; ;pic12f1822.h: 3023: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1822.h: 3026: typedef union {
+[; ;pic12f1822.h: 3027: struct {
+[; ;pic12f1822.h: 3028: unsigned ABDEN :1;
+[; ;pic12f1822.h: 3029: unsigned WUE :1;
+[; ;pic12f1822.h: 3030: unsigned :1;
+[; ;pic12f1822.h: 3031: unsigned BRG16 :1;
+[; ;pic12f1822.h: 3032: unsigned SCKP :1;
+[; ;pic12f1822.h: 3033: unsigned :1;
+[; ;pic12f1822.h: 3034: unsigned RCIDL :1;
+[; ;pic12f1822.h: 3035: unsigned ABDOVF :1;
+[; ;pic12f1822.h: 3036: };
+[; ;pic12f1822.h: 3037: } BAUDCONbits_t;
+[; ;pic12f1822.h: 3038: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1822.h: 3072: extern volatile unsigned char WPUA @ 0x20C;
+"3074
+[; ;pic12f1822.h: 3074: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1822.h: 3077: typedef union {
+[; ;pic12f1822.h: 3078: struct {
+[; ;pic12f1822.h: 3079: unsigned WPUA0 :1;
+[; ;pic12f1822.h: 3080: unsigned WPUA1 :1;
+[; ;pic12f1822.h: 3081: unsigned WPUA2 :1;
+[; ;pic12f1822.h: 3082: unsigned WPUA3 :1;
+[; ;pic12f1822.h: 3083: unsigned WPUA4 :1;
+[; ;pic12f1822.h: 3084: unsigned WPUA5 :1;
+[; ;pic12f1822.h: 3085: };
+[; ;pic12f1822.h: 3086: struct {
+[; ;pic12f1822.h: 3087: unsigned WPUA :6;
+[; ;pic12f1822.h: 3088: };
+[; ;pic12f1822.h: 3089: } WPUAbits_t;
+[; ;pic12f1822.h: 3090: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1822.h: 3129: extern volatile unsigned char SSP1BUF @ 0x211;
+"3131
+[; ;pic12f1822.h: 3131: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3134: extern volatile unsigned char SSPBUF @ 0x211;
+"3136
+[; ;pic12f1822.h: 3136: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3139: typedef union {
+[; ;pic12f1822.h: 3140: struct {
+[; ;pic12f1822.h: 3141: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3142: };
+[; ;pic12f1822.h: 3143: } SSP1BUFbits_t;
+[; ;pic12f1822.h: 3144: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1822.h: 3152: typedef union {
+[; ;pic12f1822.h: 3153: struct {
+[; ;pic12f1822.h: 3154: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3155: };
+[; ;pic12f1822.h: 3156: } SSPBUFbits_t;
+[; ;pic12f1822.h: 3157: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1822.h: 3166: extern volatile unsigned char SSP1ADD @ 0x212;
+"3168
+[; ;pic12f1822.h: 3168: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3171: extern volatile unsigned char SSPADD @ 0x212;
+"3173
+[; ;pic12f1822.h: 3173: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3176: typedef union {
+[; ;pic12f1822.h: 3177: struct {
+[; ;pic12f1822.h: 3178: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3179: };
+[; ;pic12f1822.h: 3180: } SSP1ADDbits_t;
+[; ;pic12f1822.h: 3181: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1822.h: 3189: typedef union {
+[; ;pic12f1822.h: 3190: struct {
+[; ;pic12f1822.h: 3191: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3192: };
+[; ;pic12f1822.h: 3193: } SSPADDbits_t;
+[; ;pic12f1822.h: 3194: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1822.h: 3203: extern volatile unsigned char SSP1MSK @ 0x213;
+"3205
+[; ;pic12f1822.h: 3205: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3208: extern volatile unsigned char SSPMSK @ 0x213;
+"3210
+[; ;pic12f1822.h: 3210: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3213: typedef union {
+[; ;pic12f1822.h: 3214: struct {
+[; ;pic12f1822.h: 3215: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3216: };
+[; ;pic12f1822.h: 3217: } SSP1MSKbits_t;
+[; ;pic12f1822.h: 3218: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1822.h: 3226: typedef union {
+[; ;pic12f1822.h: 3227: struct {
+[; ;pic12f1822.h: 3228: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3229: };
+[; ;pic12f1822.h: 3230: } SSPMSKbits_t;
+[; ;pic12f1822.h: 3231: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1822.h: 3240: extern volatile unsigned char SSP1STAT @ 0x214;
+"3242
+[; ;pic12f1822.h: 3242: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3245: extern volatile unsigned char SSPSTAT @ 0x214;
+"3247
+[; ;pic12f1822.h: 3247: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3250: typedef union {
+[; ;pic12f1822.h: 3251: struct {
+[; ;pic12f1822.h: 3252: unsigned BF :1;
+[; ;pic12f1822.h: 3253: unsigned UA :1;
+[; ;pic12f1822.h: 3254: unsigned R_nW :1;
+[; ;pic12f1822.h: 3255: unsigned S :1;
+[; ;pic12f1822.h: 3256: unsigned P :1;
+[; ;pic12f1822.h: 3257: unsigned D_nA :1;
+[; ;pic12f1822.h: 3258: unsigned CKE :1;
+[; ;pic12f1822.h: 3259: unsigned SMP :1;
+[; ;pic12f1822.h: 3260: };
+[; ;pic12f1822.h: 3261: } SSP1STATbits_t;
+[; ;pic12f1822.h: 3262: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1822.h: 3305: typedef union {
+[; ;pic12f1822.h: 3306: struct {
+[; ;pic12f1822.h: 3307: unsigned BF :1;
+[; ;pic12f1822.h: 3308: unsigned UA :1;
+[; ;pic12f1822.h: 3309: unsigned R_nW :1;
+[; ;pic12f1822.h: 3310: unsigned S :1;
+[; ;pic12f1822.h: 3311: unsigned P :1;
+[; ;pic12f1822.h: 3312: unsigned D_nA :1;
+[; ;pic12f1822.h: 3313: unsigned CKE :1;
+[; ;pic12f1822.h: 3314: unsigned SMP :1;
+[; ;pic12f1822.h: 3315: };
+[; ;pic12f1822.h: 3316: } SSPSTATbits_t;
+[; ;pic12f1822.h: 3317: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1822.h: 3361: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3363
+[; ;pic12f1822.h: 3363: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3366: extern volatile unsigned char SSPCON1 @ 0x215;
+"3368
+[; ;pic12f1822.h: 3368: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3370: extern volatile unsigned char SSPCON @ 0x215;
+"3372
+[; ;pic12f1822.h: 3372: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1822.h: 3375: typedef union {
+[; ;pic12f1822.h: 3376: struct {
+[; ;pic12f1822.h: 3377: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3378: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3379: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3380: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3381: unsigned CKP :1;
+[; ;pic12f1822.h: 3382: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3383: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3384: unsigned WCOL :1;
+[; ;pic12f1822.h: 3385: };
+[; ;pic12f1822.h: 3386: struct {
+[; ;pic12f1822.h: 3387: unsigned SSPM :4;
+[; ;pic12f1822.h: 3388: };
+[; ;pic12f1822.h: 3389: } SSP1CON1bits_t;
+[; ;pic12f1822.h: 3390: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1822.h: 3438: typedef union {
+[; ;pic12f1822.h: 3439: struct {
+[; ;pic12f1822.h: 3440: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3441: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3442: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3443: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3444: unsigned CKP :1;
+[; ;pic12f1822.h: 3445: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3446: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3447: unsigned WCOL :1;
+[; ;pic12f1822.h: 3448: };
+[; ;pic12f1822.h: 3449: struct {
+[; ;pic12f1822.h: 3450: unsigned SSPM :4;
+[; ;pic12f1822.h: 3451: };
+[; ;pic12f1822.h: 3452: } SSPCON1bits_t;
+[; ;pic12f1822.h: 3453: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1822.h: 3500: typedef union {
+[; ;pic12f1822.h: 3501: struct {
+[; ;pic12f1822.h: 3502: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3503: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3504: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3505: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3506: unsigned CKP :1;
+[; ;pic12f1822.h: 3507: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3508: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3509: unsigned WCOL :1;
+[; ;pic12f1822.h: 3510: };
+[; ;pic12f1822.h: 3511: struct {
+[; ;pic12f1822.h: 3512: unsigned SSPM :4;
+[; ;pic12f1822.h: 3513: };
+[; ;pic12f1822.h: 3514: } SSPCONbits_t;
+[; ;pic12f1822.h: 3515: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1822.h: 3564: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3566
+[; ;pic12f1822.h: 3566: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3569: extern volatile unsigned char SSPCON2 @ 0x216;
+"3571
+[; ;pic12f1822.h: 3571: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3574: typedef union {
+[; ;pic12f1822.h: 3575: struct {
+[; ;pic12f1822.h: 3576: unsigned SEN :1;
+[; ;pic12f1822.h: 3577: unsigned RSEN :1;
+[; ;pic12f1822.h: 3578: unsigned PEN :1;
+[; ;pic12f1822.h: 3579: unsigned RCEN :1;
+[; ;pic12f1822.h: 3580: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3581: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3582: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3583: unsigned GCEN :1;
+[; ;pic12f1822.h: 3584: };
+[; ;pic12f1822.h: 3585: } SSP1CON2bits_t;
+[; ;pic12f1822.h: 3586: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1822.h: 3629: typedef union {
+[; ;pic12f1822.h: 3630: struct {
+[; ;pic12f1822.h: 3631: unsigned SEN :1;
+[; ;pic12f1822.h: 3632: unsigned RSEN :1;
+[; ;pic12f1822.h: 3633: unsigned PEN :1;
+[; ;pic12f1822.h: 3634: unsigned RCEN :1;
+[; ;pic12f1822.h: 3635: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3636: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3637: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3638: unsigned GCEN :1;
+[; ;pic12f1822.h: 3639: };
+[; ;pic12f1822.h: 3640: } SSPCON2bits_t;
+[; ;pic12f1822.h: 3641: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1822.h: 3685: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3687
+[; ;pic12f1822.h: 3687: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3690: extern volatile unsigned char SSPCON3 @ 0x217;
+"3692
+[; ;pic12f1822.h: 3692: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3695: typedef union {
+[; ;pic12f1822.h: 3696: struct {
+[; ;pic12f1822.h: 3697: unsigned DHEN :1;
+[; ;pic12f1822.h: 3698: unsigned AHEN :1;
+[; ;pic12f1822.h: 3699: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3700: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3701: unsigned BOEN :1;
+[; ;pic12f1822.h: 3702: unsigned SCIE :1;
+[; ;pic12f1822.h: 3703: unsigned PCIE :1;
+[; ;pic12f1822.h: 3704: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3705: };
+[; ;pic12f1822.h: 3706: } SSP1CON3bits_t;
+[; ;pic12f1822.h: 3707: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1822.h: 3750: typedef union {
+[; ;pic12f1822.h: 3751: struct {
+[; ;pic12f1822.h: 3752: unsigned DHEN :1;
+[; ;pic12f1822.h: 3753: unsigned AHEN :1;
+[; ;pic12f1822.h: 3754: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3755: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3756: unsigned BOEN :1;
+[; ;pic12f1822.h: 3757: unsigned SCIE :1;
+[; ;pic12f1822.h: 3758: unsigned PCIE :1;
+[; ;pic12f1822.h: 3759: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3760: };
+[; ;pic12f1822.h: 3761: } SSPCON3bits_t;
+[; ;pic12f1822.h: 3762: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1822.h: 3806: extern volatile unsigned char CCPR1L @ 0x291;
+"3808
+[; ;pic12f1822.h: 3808: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1822.h: 3811: typedef union {
+[; ;pic12f1822.h: 3812: struct {
+[; ;pic12f1822.h: 3813: unsigned CCPR1L :8;
+[; ;pic12f1822.h: 3814: };
+[; ;pic12f1822.h: 3815: } CCPR1Lbits_t;
+[; ;pic12f1822.h: 3816: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1822.h: 3825: extern volatile unsigned char CCPR1H @ 0x292;
+"3827
+[; ;pic12f1822.h: 3827: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1822.h: 3830: typedef union {
+[; ;pic12f1822.h: 3831: struct {
+[; ;pic12f1822.h: 3832: unsigned CCPR1H :8;
+[; ;pic12f1822.h: 3833: };
+[; ;pic12f1822.h: 3834: } CCPR1Hbits_t;
+[; ;pic12f1822.h: 3835: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1822.h: 3844: extern volatile unsigned char CCP1CON @ 0x293;
+"3846
+[; ;pic12f1822.h: 3846: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1822.h: 3849: typedef union {
+[; ;pic12f1822.h: 3850: struct {
+[; ;pic12f1822.h: 3851: unsigned CCP1M0 :1;
+[; ;pic12f1822.h: 3852: unsigned CCP1M1 :1;
+[; ;pic12f1822.h: 3853: unsigned CCP1M2 :1;
+[; ;pic12f1822.h: 3854: unsigned CCP1M3 :1;
+[; ;pic12f1822.h: 3855: unsigned DC1B0 :1;
+[; ;pic12f1822.h: 3856: unsigned DC1B1 :1;
+[; ;pic12f1822.h: 3857: unsigned P1M0 :1;
+[; ;pic12f1822.h: 3858: unsigned P1M1 :1;
+[; ;pic12f1822.h: 3859: };
+[; ;pic12f1822.h: 3860: struct {
+[; ;pic12f1822.h: 3861: unsigned CCP1M :4;
+[; ;pic12f1822.h: 3862: unsigned DC1B :2;
+[; ;pic12f1822.h: 3863: unsigned P1M :2;
+[; ;pic12f1822.h: 3864: };
+[; ;pic12f1822.h: 3865: } CCP1CONbits_t;
+[; ;pic12f1822.h: 3866: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1822.h: 3925: extern volatile unsigned char PWM1CON @ 0x294;
+"3927
+[; ;pic12f1822.h: 3927: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1822.h: 3930: typedef union {
+[; ;pic12f1822.h: 3931: struct {
+[; ;pic12f1822.h: 3932: unsigned P1DC0 :1;
+[; ;pic12f1822.h: 3933: unsigned P1DC1 :1;
+[; ;pic12f1822.h: 3934: unsigned P1DC2 :1;
+[; ;pic12f1822.h: 3935: unsigned P1DC3 :1;
+[; ;pic12f1822.h: 3936: unsigned P1DC4 :1;
+[; ;pic12f1822.h: 3937: unsigned P1DC5 :1;
+[; ;pic12f1822.h: 3938: unsigned P1DC6 :1;
+[; ;pic12f1822.h: 3939: unsigned P1RSEN :1;
+[; ;pic12f1822.h: 3940: };
+[; ;pic12f1822.h: 3941: struct {
+[; ;pic12f1822.h: 3942: unsigned P1DC :7;
+[; ;pic12f1822.h: 3943: };
+[; ;pic12f1822.h: 3944: } PWM1CONbits_t;
+[; ;pic12f1822.h: 3945: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1822.h: 3994: extern volatile unsigned char CCP1AS @ 0x295;
+"3996
+[; ;pic12f1822.h: 3996: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 3999: extern volatile unsigned char ECCP1AS @ 0x295;
+"4001
+[; ;pic12f1822.h: 4001: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 4004: typedef union {
+[; ;pic12f1822.h: 4005: struct {
+[; ;pic12f1822.h: 4006: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4007: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4008: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4009: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4010: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4011: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4012: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4013: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4014: };
+[; ;pic12f1822.h: 4015: struct {
+[; ;pic12f1822.h: 4016: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4017: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4018: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4019: };
+[; ;pic12f1822.h: 4020: } CCP1ASbits_t;
+[; ;pic12f1822.h: 4021: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4079: typedef union {
+[; ;pic12f1822.h: 4080: struct {
+[; ;pic12f1822.h: 4081: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4082: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4083: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4084: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4085: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4086: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4087: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4088: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4089: };
+[; ;pic12f1822.h: 4090: struct {
+[; ;pic12f1822.h: 4091: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4092: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4093: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4094: };
+[; ;pic12f1822.h: 4095: } ECCP1ASbits_t;
+[; ;pic12f1822.h: 4096: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4155: extern volatile unsigned char PSTR1CON @ 0x296;
+"4157
+[; ;pic12f1822.h: 4157: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1822.h: 4160: typedef union {
+[; ;pic12f1822.h: 4161: struct {
+[; ;pic12f1822.h: 4162: unsigned STR1A :1;
+[; ;pic12f1822.h: 4163: unsigned STR1B :1;
+[; ;pic12f1822.h: 4164: unsigned STR1C :1;
+[; ;pic12f1822.h: 4165: unsigned STR1D :1;
+[; ;pic12f1822.h: 4166: unsigned STR1SYNC :1;
+[; ;pic12f1822.h: 4167: };
+[; ;pic12f1822.h: 4168: } PSTR1CONbits_t;
+[; ;pic12f1822.h: 4169: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1822.h: 4198: extern volatile unsigned char IOCAP @ 0x391;
+"4200
+[; ;pic12f1822.h: 4200: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1822.h: 4203: typedef union {
+[; ;pic12f1822.h: 4204: struct {
+[; ;pic12f1822.h: 4205: unsigned IOCAP0 :1;
+[; ;pic12f1822.h: 4206: unsigned IOCAP1 :1;
+[; ;pic12f1822.h: 4207: unsigned IOCAP2 :1;
+[; ;pic12f1822.h: 4208: unsigned IOCAP3 :1;
+[; ;pic12f1822.h: 4209: unsigned IOCAP4 :1;
+[; ;pic12f1822.h: 4210: unsigned IOCAP5 :1;
+[; ;pic12f1822.h: 4211: };
+[; ;pic12f1822.h: 4212: struct {
+[; ;pic12f1822.h: 4213: unsigned IOCAP :6;
+[; ;pic12f1822.h: 4214: };
+[; ;pic12f1822.h: 4215: } IOCAPbits_t;
+[; ;pic12f1822.h: 4216: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1822.h: 4255: extern volatile unsigned char IOCAN @ 0x392;
+"4257
+[; ;pic12f1822.h: 4257: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1822.h: 4260: typedef union {
+[; ;pic12f1822.h: 4261: struct {
+[; ;pic12f1822.h: 4262: unsigned IOCAN0 :1;
+[; ;pic12f1822.h: 4263: unsigned IOCAN1 :1;
+[; ;pic12f1822.h: 4264: unsigned IOCAN2 :1;
+[; ;pic12f1822.h: 4265: unsigned IOCAN3 :1;
+[; ;pic12f1822.h: 4266: unsigned IOCAN4 :1;
+[; ;pic12f1822.h: 4267: unsigned IOCAN5 :1;
+[; ;pic12f1822.h: 4268: };
+[; ;pic12f1822.h: 4269: struct {
+[; ;pic12f1822.h: 4270: unsigned IOCAN :6;
+[; ;pic12f1822.h: 4271: };
+[; ;pic12f1822.h: 4272: } IOCANbits_t;
+[; ;pic12f1822.h: 4273: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1822.h: 4312: extern volatile unsigned char IOCAF @ 0x393;
+"4314
+[; ;pic12f1822.h: 4314: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1822.h: 4317: typedef union {
+[; ;pic12f1822.h: 4318: struct {
+[; ;pic12f1822.h: 4319: unsigned IOCAF0 :1;
+[; ;pic12f1822.h: 4320: unsigned IOCAF1 :1;
+[; ;pic12f1822.h: 4321: unsigned IOCAF2 :1;
+[; ;pic12f1822.h: 4322: unsigned IOCAF3 :1;
+[; ;pic12f1822.h: 4323: unsigned IOCAF4 :1;
+[; ;pic12f1822.h: 4324: unsigned IOCAF5 :1;
+[; ;pic12f1822.h: 4325: };
+[; ;pic12f1822.h: 4326: struct {
+[; ;pic12f1822.h: 4327: unsigned IOCAF :6;
+[; ;pic12f1822.h: 4328: };
+[; ;pic12f1822.h: 4329: } IOCAFbits_t;
+[; ;pic12f1822.h: 4330: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1822.h: 4369: extern volatile unsigned char CLKRCON @ 0x39A;
+"4371
+[; ;pic12f1822.h: 4371: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1822.h: 4374: typedef union {
+[; ;pic12f1822.h: 4375: struct {
+[; ;pic12f1822.h: 4376: unsigned CLKRDIV0 :1;
+[; ;pic12f1822.h: 4377: unsigned CLKRDIV1 :1;
+[; ;pic12f1822.h: 4378: unsigned CLKRDIV2 :1;
+[; ;pic12f1822.h: 4379: unsigned CLKRDC0 :1;
+[; ;pic12f1822.h: 4380: unsigned CLKRDC1 :1;
+[; ;pic12f1822.h: 4381: unsigned CLKRSLR :1;
+[; ;pic12f1822.h: 4382: unsigned CLKROE :1;
+[; ;pic12f1822.h: 4383: unsigned CLKREN :1;
+[; ;pic12f1822.h: 4384: };
+[; ;pic12f1822.h: 4385: struct {
+[; ;pic12f1822.h: 4386: unsigned CLKRDIV :3;
+[; ;pic12f1822.h: 4387: unsigned CLKRDC :2;
+[; ;pic12f1822.h: 4388: };
+[; ;pic12f1822.h: 4389: } CLKRCONbits_t;
+[; ;pic12f1822.h: 4390: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1822.h: 4444: extern volatile unsigned char MDCON @ 0x39C;
+"4446
+[; ;pic12f1822.h: 4446: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1822.h: 4449: typedef union {
+[; ;pic12f1822.h: 4450: struct {
+[; ;pic12f1822.h: 4451: unsigned MDBIT :1;
+[; ;pic12f1822.h: 4452: unsigned :2;
+[; ;pic12f1822.h: 4453: unsigned MDOUT :1;
+[; ;pic12f1822.h: 4454: unsigned MDOPOL :1;
+[; ;pic12f1822.h: 4455: unsigned MDSLR :1;
+[; ;pic12f1822.h: 4456: unsigned MDOE :1;
+[; ;pic12f1822.h: 4457: unsigned MDEN :1;
+[; ;pic12f1822.h: 4458: };
+[; ;pic12f1822.h: 4459: } MDCONbits_t;
+[; ;pic12f1822.h: 4460: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1822.h: 4494: extern volatile unsigned char MDSRC @ 0x39D;
+"4496
+[; ;pic12f1822.h: 4496: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1822.h: 4499: typedef union {
+[; ;pic12f1822.h: 4500: struct {
+[; ;pic12f1822.h: 4501: unsigned MDMS0 :1;
+[; ;pic12f1822.h: 4502: unsigned MDMS1 :1;
+[; ;pic12f1822.h: 4503: unsigned MDMS2 :1;
+[; ;pic12f1822.h: 4504: unsigned MDMS3 :1;
+[; ;pic12f1822.h: 4505: unsigned :3;
+[; ;pic12f1822.h: 4506: unsigned MDMSODIS :1;
+[; ;pic12f1822.h: 4507: };
+[; ;pic12f1822.h: 4508: struct {
+[; ;pic12f1822.h: 4509: unsigned MDMS :4;
+[; ;pic12f1822.h: 4510: };
+[; ;pic12f1822.h: 4511: } MDSRCbits_t;
+[; ;pic12f1822.h: 4512: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1822.h: 4546: extern volatile unsigned char MDCARL @ 0x39E;
+"4548
+[; ;pic12f1822.h: 4548: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1822.h: 4551: typedef union {
+[; ;pic12f1822.h: 4552: struct {
+[; ;pic12f1822.h: 4553: unsigned MDCL0 :1;
+[; ;pic12f1822.h: 4554: unsigned MDCL1 :1;
+[; ;pic12f1822.h: 4555: unsigned MDCL2 :1;
+[; ;pic12f1822.h: 4556: unsigned MDCL3 :1;
+[; ;pic12f1822.h: 4557: unsigned :1;
+[; ;pic12f1822.h: 4558: unsigned MDCLSYNC :1;
+[; ;pic12f1822.h: 4559: unsigned MDCLPOL :1;
+[; ;pic12f1822.h: 4560: unsigned MDCLODIS :1;
+[; ;pic12f1822.h: 4561: };
+[; ;pic12f1822.h: 4562: struct {
+[; ;pic12f1822.h: 4563: unsigned MDCL :4;
+[; ;pic12f1822.h: 4564: };
+[; ;pic12f1822.h: 4565: } MDCARLbits_t;
+[; ;pic12f1822.h: 4566: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1822.h: 4610: extern volatile unsigned char MDCARH @ 0x39F;
+"4612
+[; ;pic12f1822.h: 4612: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1822.h: 4615: typedef union {
+[; ;pic12f1822.h: 4616: struct {
+[; ;pic12f1822.h: 4617: unsigned MDCH0 :1;
+[; ;pic12f1822.h: 4618: unsigned MDCH1 :1;
+[; ;pic12f1822.h: 4619: unsigned MDCH2 :1;
+[; ;pic12f1822.h: 4620: unsigned MDCH3 :1;
+[; ;pic12f1822.h: 4621: unsigned :1;
+[; ;pic12f1822.h: 4622: unsigned MDCHSYNC :1;
+[; ;pic12f1822.h: 4623: unsigned MDCHPOL :1;
+[; ;pic12f1822.h: 4624: unsigned MDCHODIS :1;
+[; ;pic12f1822.h: 4625: };
+[; ;pic12f1822.h: 4626: struct {
+[; ;pic12f1822.h: 4627: unsigned MDCH :4;
+[; ;pic12f1822.h: 4628: };
+[; ;pic12f1822.h: 4629: } MDCARHbits_t;
+[; ;pic12f1822.h: 4630: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1822.h: 4674: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4676
+[; ;pic12f1822.h: 4676: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1822.h: 4679: typedef union {
+[; ;pic12f1822.h: 4680: struct {
+[; ;pic12f1822.h: 4681: unsigned C_SHAD :1;
+[; ;pic12f1822.h: 4682: unsigned DC_SHAD :1;
+[; ;pic12f1822.h: 4683: unsigned Z_SHAD :1;
+[; ;pic12f1822.h: 4684: };
+[; ;pic12f1822.h: 4685: } STATUS_SHADbits_t;
+[; ;pic12f1822.h: 4686: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1822.h: 4705: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4707
+[; ;pic12f1822.h: 4707: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1822.h: 4710: typedef union {
+[; ;pic12f1822.h: 4711: struct {
+[; ;pic12f1822.h: 4712: unsigned WREG_SHAD :8;
+[; ;pic12f1822.h: 4713: };
+[; ;pic12f1822.h: 4714: } WREG_SHADbits_t;
+[; ;pic12f1822.h: 4715: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1822.h: 4724: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4726
+[; ;pic12f1822.h: 4726: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1822.h: 4729: typedef union {
+[; ;pic12f1822.h: 4730: struct {
+[; ;pic12f1822.h: 4731: unsigned BSR_SHAD :5;
+[; ;pic12f1822.h: 4732: };
+[; ;pic12f1822.h: 4733: } BSR_SHADbits_t;
+[; ;pic12f1822.h: 4734: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1822.h: 4743: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4745
+[; ;pic12f1822.h: 4745: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1822.h: 4748: typedef union {
+[; ;pic12f1822.h: 4749: struct {
+[; ;pic12f1822.h: 4750: unsigned PCLATH_SHAD :7;
+[; ;pic12f1822.h: 4751: };
+[; ;pic12f1822.h: 4752: } PCLATH_SHADbits_t;
+[; ;pic12f1822.h: 4753: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1822.h: 4762: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4764
+[; ;pic12f1822.h: 4764: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1822.h: 4767: typedef union {
+[; ;pic12f1822.h: 4768: struct {
+[; ;pic12f1822.h: 4769: unsigned FSR0L_SHAD :8;
+[; ;pic12f1822.h: 4770: };
+[; ;pic12f1822.h: 4771: } FSR0L_SHADbits_t;
+[; ;pic12f1822.h: 4772: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1822.h: 4781: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4783
+[; ;pic12f1822.h: 4783: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1822.h: 4786: typedef union {
+[; ;pic12f1822.h: 4787: struct {
+[; ;pic12f1822.h: 4788: unsigned FSR0H_SHAD :8;
+[; ;pic12f1822.h: 4789: };
+[; ;pic12f1822.h: 4790: } FSR0H_SHADbits_t;
+[; ;pic12f1822.h: 4791: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1822.h: 4800: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4802
+[; ;pic12f1822.h: 4802: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1822.h: 4805: typedef union {
+[; ;pic12f1822.h: 4806: struct {
+[; ;pic12f1822.h: 4807: unsigned FSR1L_SHAD :8;
+[; ;pic12f1822.h: 4808: };
+[; ;pic12f1822.h: 4809: } FSR1L_SHADbits_t;
+[; ;pic12f1822.h: 4810: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1822.h: 4819: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4821
+[; ;pic12f1822.h: 4821: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1822.h: 4824: typedef union {
+[; ;pic12f1822.h: 4825: struct {
+[; ;pic12f1822.h: 4826: unsigned FSR1H_SHAD :8;
+[; ;pic12f1822.h: 4827: };
+[; ;pic12f1822.h: 4828: } FSR1H_SHADbits_t;
+[; ;pic12f1822.h: 4829: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1822.h: 4838: extern volatile unsigned char STKPTR @ 0xFED;
+"4840
+[; ;pic12f1822.h: 4840: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1822.h: 4843: typedef union {
+[; ;pic12f1822.h: 4844: struct {
+[; ;pic12f1822.h: 4845: unsigned STKPTR :5;
+[; ;pic12f1822.h: 4846: };
+[; ;pic12f1822.h: 4847: } STKPTRbits_t;
+[; ;pic12f1822.h: 4848: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1822.h: 4857: extern volatile unsigned char TOSL @ 0xFEE;
+"4859
+[; ;pic12f1822.h: 4859: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1822.h: 4862: typedef union {
+[; ;pic12f1822.h: 4863: struct {
+[; ;pic12f1822.h: 4864: unsigned TOSL :8;
+[; ;pic12f1822.h: 4865: };
+[; ;pic12f1822.h: 4866: } TOSLbits_t;
+[; ;pic12f1822.h: 4867: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1822.h: 4876: extern volatile unsigned char TOSH @ 0xFEF;
+"4878
+[; ;pic12f1822.h: 4878: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1822.h: 4881: typedef union {
+[; ;pic12f1822.h: 4882: struct {
+[; ;pic12f1822.h: 4883: unsigned TOSH :7;
+[; ;pic12f1822.h: 4884: };
+[; ;pic12f1822.h: 4885: } TOSHbits_t;
+[; ;pic12f1822.h: 4886: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1822.h: 4901: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1822.h: 4903: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1822.h: 4905: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1822.h: 4907: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1822.h: 4909: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1822.h: 4911: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1822.h: 4913: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1822.h: 4915: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1822.h: 4917: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1822.h: 4919: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1822.h: 4921: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1822.h: 4923: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1822.h: 4925: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1822.h: 4927: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 4929: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1822.h: 4931: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1822.h: 4933: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1822.h: 4935: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1822.h: 4937: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1822.h: 4939: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1822.h: 4941: extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4943: extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4945: extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 4947: extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4949: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1822.h: 4951: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1822.h: 4953: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1822.h: 4955: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1822.h: 4957: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1822.h: 4959: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1822.h: 4961: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1822.h: 4963: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1822.h: 4965: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1822.h: 4967: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1822.h: 4969: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1822.h: 4971: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1822.h: 4973: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1822.h: 4975: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1822.h: 4977: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1822.h: 4979: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1822.h: 4981: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1822.h: 4983: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1822.h: 4985: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1822.h: 4987: extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4989: extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4991: extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4993: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1822.h: 4995: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1822.h: 4997: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1822.h: 4999: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1822.h: 5001: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1822.h: 5003: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1822.h: 5005: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1822.h: 5007: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1822.h: 5009: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1822.h: 5011: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1822.h: 5013: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1822.h: 5015: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1822.h: 5017: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1822.h: 5019: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1822.h: 5021: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1822.h: 5023: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1822.h: 5025: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1822.h: 5027: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1822.h: 5029: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1822.h: 5031: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1822.h: 5033: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1822.h: 5035: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1822.h: 5037: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1822.h: 5039: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1822.h: 5041: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1822.h: 5043: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1822.h: 5045: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1822.h: 5047: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1822.h: 5049: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1822.h: 5051: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1822.h: 5053: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1822.h: 5055: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1822.h: 5057: extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5059: extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5061: extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5063: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1822.h: 5065: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1822.h: 5067: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1822.h: 5069: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1822.h: 5071: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1822.h: 5073: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1822.h: 5075: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1822.h: 5077: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1822.h: 5079: extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5081: extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5083: extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5085: extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5087: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1822.h: 5089: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1822.h: 5091: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1822.h: 5093: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1822.h: 5095: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1822.h: 5097: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1822.h: 5099: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1822.h: 5101: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1822.h: 5103: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1822.h: 5105: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1822.h: 5107: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1822.h: 5109: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1822.h: 5111: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1822.h: 5113: extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5115: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1822.h: 5117: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1822.h: 5119: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1822.h: 5121: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1822.h: 5123: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1822.h: 5125: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1822.h: 5127: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1822.h: 5129: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1822.h: 5131: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1822.h: 5133: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1822.h: 5135: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1822.h: 5137: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1822.h: 5139: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1822.h: 5141: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1822.h: 5143: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1822.h: 5145: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1822.h: 5147: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1822.h: 5149: extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5151: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1822.h: 5153: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1822.h: 5155: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1822.h: 5157: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1822.h: 5159: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1822.h: 5161: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5163: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5165: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1822.h: 5167: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1822.h: 5169: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1822.h: 5171: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1822.h: 5173: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1822.h: 5175: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1822.h: 5177: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1822.h: 5179: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1822.h: 5181: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1822.h: 5183: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1822.h: 5185: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1822.h: 5187: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1822.h: 5189: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1822.h: 5191: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1822.h: 5193: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1822.h: 5195: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1822.h: 5197: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1822.h: 5199: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1822.h: 5201: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1822.h: 5203: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1822.h: 5205: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1822.h: 5207: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1822.h: 5209: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1822.h: 5211: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1822.h: 5213: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1822.h: 5215: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1822.h: 5217: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1822.h: 5219: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1822.h: 5221: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1822.h: 5223: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1822.h: 5225: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1822.h: 5227: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1822.h: 5229: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1822.h: 5231: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1822.h: 5233: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1822.h: 5235: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1822.h: 5237: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1822.h: 5239: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1822.h: 5241: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1822.h: 5243: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1822.h: 5245: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1822.h: 5247: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1822.h: 5249: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1822.h: 5251: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1822.h: 5253: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1822.h: 5255: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1822.h: 5257: extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5259: extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5261: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1822.h: 5263: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1822.h: 5265: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1822.h: 5267: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1822.h: 5269: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1822.h: 5271: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1822.h: 5273: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1822.h: 5275: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1822.h: 5277: extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5279: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1822.h: 5281: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1822.h: 5283: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1822.h: 5285: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1822.h: 5287: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1822.h: 5289: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1822.h: 5291: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1822.h: 5293: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1822.h: 5295: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1822.h: 5297: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1822.h: 5299: extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5301: extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5303: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1822.h: 5305: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1822.h: 5307: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1822.h: 5309: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1822.h: 5311: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1822.h: 5313: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1822.h: 5315: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1822.h: 5317: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1822.h: 5319: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1822.h: 5321: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1822.h: 5323: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1822.h: 5325: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1822.h: 5327: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1822.h: 5329: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1822.h: 5331: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1822.h: 5333: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1822.h: 5335: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1822.h: 5337: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1822.h: 5339: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1822.h: 5341: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1822.h: 5343: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1822.h: 5345: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1822.h: 5347: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1822.h: 5349: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1822.h: 5351: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1822.h: 5353: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1822.h: 5355: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5357: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5359: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5361: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5363: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5365: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5367: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1822.h: 5369: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1822.h: 5371: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1822.h: 5373: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1822.h: 5375: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1822.h: 5377: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1822.h: 5379: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1822.h: 5381: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1822.h: 5383: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1822.h: 5385: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1822.h: 5387: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1822.h: 5389: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1822.h: 5391: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1822.h: 5393: extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5395: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1822.h: 5397: extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5399: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1822.h: 5401: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1822.h: 5403: extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5405: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1822.h: 5407: extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5409: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5411: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5413: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1822.h: 5415: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1822.h: 5417: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1822.h: 5419: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1822.h: 5421: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1822.h: 5423: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1822.h: 5425: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1822.h: 5427: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1822.h: 5429: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1822.h: 5431: extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5433: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1822.h: 5435: extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5437: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1822.h: 5439: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1822.h: 5441: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1822.h: 5443: extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5445: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1822.h: 5447: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1822.h: 5449: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1822.h: 5451: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1822.h: 5453: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1822.h: 5455: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1822.h: 5457: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1822.h: 5459: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5461: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1822.h: 5463: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1822.h: 5465: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1822.h: 5467: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1822.h: 5469: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1822.h: 5471: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1822.h: 5473: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1822.h: 5475: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1822.h: 5477: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5479: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1822.h: 5481: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1822.h: 5483: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1822.h: 5485: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1822.h: 5487: extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+[; ;pic12f1822.h: 5489: extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+[; ;pic12f1822.h: 5491: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1822.h: 5493: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1822.h: 5495: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1822.h: 5497: extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5499: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5501: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5503: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5505: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5507: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1822.h: 5509: extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5511: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1822.h: 5513: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1822.h: 5515: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5517: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5519: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1822.h: 5521: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1822.h: 5523: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1822.h: 5525: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1822.h: 5527: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1822.h: 5529: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1822.h: 5531: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1822.h: 5533: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1822.h: 5535: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1822.h: 5537: extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5539: extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5541: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1822.h: 5543: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1822.h: 5545: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1822.h: 5547: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1822.h: 5549: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1822.h: 5551: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1822.h: 5553: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5555: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5557: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5559: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5561: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1822.h: 5563: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1822.h: 5565: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1822.h: 5567: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1822.h: 5569: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1822.h: 5571: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1822.h: 5573: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1822.h: 5575: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1822.h: 5577: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1822.h: 5579: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1822.h: 5581: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1822.h: 5583: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1822.h: 5585: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1822.h: 5587: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1822.h: 5589: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1822.h: 5591: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1822.h: 5593: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1822.h: 5595: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1822.h: 5597: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1822.h: 5599: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1822.h: 5601: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1822.h: 5603: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1822.h: 5605: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1822.h: 5607: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1822.h: 5609: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1822.h: 5611: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1822.h: 5613: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1822.h: 5615: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1822.h: 5617: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1822.h: 5619: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1822.h: 5621: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1822.h: 5623: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1822.h: 5625: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1822.h: 5627: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1822.h: 5629: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1822.h: 5631: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1822.h: 5633: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1822.h: 5635: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1822.h: 5637: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1822.h: 5639: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1822.h: 5641: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1822.h: 5643: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1822.h: 5645: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1822.h: 5647: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1822.h: 5649: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1822.h: 5651: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1822.h: 5653: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1822.h: 5655: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1822.h: 5657: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1822.h: 5659: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1822.h: 5661: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1822.h: 5663: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1822.h: 5665: extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5667: extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5669: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1822.h: 5671: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1822.h: 5673: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1822.h: 5675: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1822.h: 5677: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1822.h: 5679: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1822.h: 5681: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;system.h: 31: void ConfigureOscillator(void);
+"19 system.c
+[v _ConfigureOscillator `(v ~T0 @X0 1 ef ]
+{
+[; ;system.c: 18: void ConfigureOscillator(void)
+[; ;system.c: 19: {
+[e :U _ConfigureOscillator ]
+[f ]
+[; ;system.c: 22: OSCCONbits.SPLLEN = 0;
+"22
+[e = . . _OSCCONbits 0 7 -> -> 0 `i `uc ]
+[; ;system.c: 23: OSCCONbits.IRCF = 0b1101;
+"23
+[e = . . _OSCCONbits 1 2 -> -> 13 `i `uc ]
+[; ;system.c: 24: OSCCONbits.SCS = 0b00;
+"24
+[e = . . _OSCCONbits 1 0 -> -> 0 `i `uc ]
+[; ;system.c: 26: }
+"26
+[e :UE 524 ]
+}

diff --git a/build/XC8_12F1822/production/system.p1.d b/build/XC8_12F1822/production/system.p1.d
new file mode 100644 (file)
index 0000000..75c643f
--- /dev/null
+++ b/build/XC8_12F1822/production/system.p1.d
@@ -0,0 +1,4 @@
+ build/XC8_12F1822/production/system.d  \
+ build/XC8_12F1822/production/system.p1:  \
+ system.c  \
+system.h 
\ No newline at end of file

diff --git a/build/XC8_12F1822/production/system.pre b/build/XC8_12F1822/production/system.pre
new file mode 100644 (file)
index 0000000..a384c99
--- /dev/null
+++ b/build/XC8_12F1822/production/system.pre
@@ -0,0 +1,5636 @@
+
+# 1 "system.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1822.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+struct {
+unsigned AN0 :1;
+unsigned AN1 :1;
+unsigned AN2 :1;
+unsigned :1;
+unsigned AN3 :1;
+};
+struct {
+unsigned CPS0 :1;
+unsigned CPS1 :1;
+unsigned CPS2 :1;
+unsigned :1;
+unsigned CPS3 :1;
+};
+struct {
+unsigned C1INP :1;
+unsigned C1IN0N :1;
+unsigned C1OUT :1;
+unsigned :1;
+unsigned C1IN1N :1;
+};
+struct {
+unsigned DACOUT :1;
+unsigned SRI :1;
+unsigned SRQ :1;
+unsigned :2;
+unsigned SRNQ :1;
+};
+struct {
+unsigned :1;
+unsigned SCK :1;
+unsigned T0CKI :1;
+unsigned :1;
+unsigned T1OSO :1;
+unsigned T1CKI :1;
+};
+struct {
+unsigned :1;
+unsigned SCL :1;
+unsigned SDA :1;
+unsigned nMCLR :1;
+unsigned CLKR :1;
+unsigned T1OSI :1;
+};
+struct {
+unsigned MDOUT :1;
+unsigned MDMIN :1;
+unsigned MDCIN1 :1;
+unsigned :1;
+unsigned MDCIN2 :1;
+};
+struct {
+unsigned :2;
+unsigned SDI :1;
+unsigned :1;
+unsigned OSC2 :1;
+unsigned OSC1 :1;
+};
+struct {
+unsigned :2;
+unsigned FLT0 :1;
+unsigned :1;
+unsigned CLKOUT :1;
+unsigned CLKIN :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 698
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 759
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 798
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 817
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 842
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 861
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 932
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 1008
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 1027
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 1046
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 1116
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 1175
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 1208
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1257
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1318
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1357
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1439
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1489
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1547
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1604
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1675
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1736
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1761
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1780
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+struct {
+unsigned :1;
+unsigned nDONE :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1868
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1933
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1977
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 2033
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned :4;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 2086
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 2105
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :6;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 2131
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 2206
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2260
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2311
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2381
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2432
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2507
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2573
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2619
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2644
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2663
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2692
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2706
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2725
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2786
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2805
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2824
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2843
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2866
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2880
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2899
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2960
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 3021
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 3072
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 3129
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 3152
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 3166
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 3189
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 3203
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3226
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3240
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3305
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3361
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3438
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3500
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3564
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3629
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3685
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3750
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3806
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3825
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3844
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3925
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3994
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 4079
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 4155
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned STR1C :1;
+unsigned STR1D :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 4198
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4255
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4312
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4369
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4444
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4494
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4546
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4610
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4674
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4705
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4724
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4743
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4762
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4781
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4800
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4819
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4838
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4857
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4876
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4901
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+
+extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+# 31 "system.h"
+void ConfigureOscillator(void);
+
+# 18 "system.c"
+void ConfigureOscillator(void)
+{
+
+
+OSCCONbits.SPLLEN = 0;
+OSCCONbits.IRCF = 0b1101;
+OSCCONbits.SCS = 0b00;
+
+}

diff --git a/build/XC8_12F1822/production/user.p1 b/build/XC8_12F1822/production/user.p1
new file mode 100644 (file)
index 0000000..d7192d1
--- /dev/null
+++ b/build/XC8_12F1822/production/user.p1
@@ -0,0 +1,4267 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[s S81 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S81 . SWDTEN WDTPS0 WDTPS1 WDTPS2 WDTPS3 WDTPS4 ]
+[s S82 :1 `uc 1 :5 `uc 1 ]
+[n S82 . . WDTPS ]
+[u S80 `S81 1 `S82 1 ]
+[n S80 . . . ]
+"1508 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[v _WDTCONbits `VS80 ~T0 @X0 0 e@151 ]
+[s S129 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S129 . CCP1SEL P1BSEL TXCKSEL T1GSEL . SSSEL SDOSEL RXDTSEL ]
+[s S130 :5 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S130 . . SS1SEL SDO1SEL ]
+[u S128 `S129 1 `S130 1 ]
+[n S128 . . . ]
+"2459
+[v _APFCONbits `VS128 ~T0 @X0 0 e@285 ]
+[s S70 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S70 . TRISA0 TRISA1 TRISA2 TRISA3 TRISA4 TRISA5 ]
+[u S69 `S70 1 ]
+[n S69 . . ]
+"1223
+[v _TRISAbits `VS69 ~T0 @X0 0 e@140 ]
+"2573
+[v _ANSELA `Vuc ~T0 @X0 0 e@396 ]
+"3072
+[v _WPUA `Vuc ~T0 @X0 0 e@524 ]
+[s S76 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S76 . PS0 PS1 PS2 PSA TMR0SE TMR0CS INTEDG nWPUEN ]
+[s S77 :3 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S77 . PS . T0SE T0CS ]
+[u S75 `S76 1 `S77 1 ]
+[n S75 . . . ]
+"1380
+[v _OPTION_REGbits `VS75 ~T0 @X0 0 e@149 ]
+[s S164 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S164 . TX9D TRMT BRGH SENDB SYNC TXEN TX9 CSRC ]
+[u S163 `S164 1 ]
+[n S163 . . ]
+"2977
+[v _TXSTAbits `VS163 ~T0 @X0 0 e@414 ]
+[s S162 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S162 . RX9D OERR FERR ADDEN CREN SREN RX9 SPEN ]
+[u S161 `S162 1 ]
+[n S161 . . ]
+"2916
+[v _RCSTAbits `VS161 ~T0 @X0 0 e@413 ]
+[s S166 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S166 . ABDEN WUE . BRG16 SCKP . RCIDL ABDOVF ]
+[u S165 `S166 1 ]
+[n S165 . . ]
+"3038
+[v _BAUDCONbits `VS165 ~T0 @X0 0 e@415 ]
+"2848
+[v _SPBRG `Vuc ~T0 @X0 0 e@411 ]
+[s S27 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S27 . IOCIF INTF TMR0IF IOCIE INTE TMR0IE PEIE GIE ]
+[s S28 :2 `uc 1 :1 `uc 1 :2 `uc 1 :1 `uc 1 ]
+[n S28 . . T0IF . T0IE ]
+[u S26 `S27 1 `S28 1 ]
+[n S26 . . . ]
+"355
+[v _INTCONbits `VS26 ~T0 @X0 0 e@11 ]
+[s S72 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S72 . TMR1IE TMR2IE CCP1IE SSP1IE TXIE RCIE ADIE TMR1GIE ]
+[u S71 `S72 1 ]
+[n S71 . . ]
+"1274
+[v _PIE1bits `VS71 ~T0 @X0 0 e@145 ]
+[; ;pic12f1822.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[; ;pic12f1822.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1822.h: 49: typedef union {
+[; ;pic12f1822.h: 50: struct {
+[; ;pic12f1822.h: 51: unsigned INDF0 :8;
+[; ;pic12f1822.h: 52: };
+[; ;pic12f1822.h: 53: } INDF0bits_t;
+[; ;pic12f1822.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1822.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1822.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1822.h: 68: typedef union {
+[; ;pic12f1822.h: 69: struct {
+[; ;pic12f1822.h: 70: unsigned INDF1 :8;
+[; ;pic12f1822.h: 71: };
+[; ;pic12f1822.h: 72: } INDF1bits_t;
+[; ;pic12f1822.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1822.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1822.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1822.h: 87: typedef union {
+[; ;pic12f1822.h: 88: struct {
+[; ;pic12f1822.h: 89: unsigned PCL :8;
+[; ;pic12f1822.h: 90: };
+[; ;pic12f1822.h: 91: } PCLbits_t;
+[; ;pic12f1822.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1822.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1822.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1822.h: 106: typedef union {
+[; ;pic12f1822.h: 107: struct {
+[; ;pic12f1822.h: 108: unsigned C :1;
+[; ;pic12f1822.h: 109: unsigned DC :1;
+[; ;pic12f1822.h: 110: unsigned Z :1;
+[; ;pic12f1822.h: 111: unsigned nPD :1;
+[; ;pic12f1822.h: 112: unsigned nTO :1;
+[; ;pic12f1822.h: 113: };
+[; ;pic12f1822.h: 114: struct {
+[; ;pic12f1822.h: 115: unsigned CARRY :1;
+[; ;pic12f1822.h: 116: };
+[; ;pic12f1822.h: 117: struct {
+[; ;pic12f1822.h: 118: unsigned :2;
+[; ;pic12f1822.h: 119: unsigned ZERO :1;
+[; ;pic12f1822.h: 120: };
+[; ;pic12f1822.h: 121: } STATUSbits_t;
+[; ;pic12f1822.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1822.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1822.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1822.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1822.h: 169: typedef union {
+[; ;pic12f1822.h: 170: struct {
+[; ;pic12f1822.h: 171: unsigned FSR0L :8;
+[; ;pic12f1822.h: 172: };
+[; ;pic12f1822.h: 173: } FSR0Lbits_t;
+[; ;pic12f1822.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1822.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1822.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1822.h: 188: typedef union {
+[; ;pic12f1822.h: 189: struct {
+[; ;pic12f1822.h: 190: unsigned FSR0H :8;
+[; ;pic12f1822.h: 191: };
+[; ;pic12f1822.h: 192: } FSR0Hbits_t;
+[; ;pic12f1822.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1822.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1822.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1822.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1822.h: 210: typedef union {
+[; ;pic12f1822.h: 211: struct {
+[; ;pic12f1822.h: 212: unsigned FSR1L :8;
+[; ;pic12f1822.h: 213: };
+[; ;pic12f1822.h: 214: } FSR1Lbits_t;
+[; ;pic12f1822.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1822.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1822.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1822.h: 229: typedef union {
+[; ;pic12f1822.h: 230: struct {
+[; ;pic12f1822.h: 231: unsigned FSR1H :8;
+[; ;pic12f1822.h: 232: };
+[; ;pic12f1822.h: 233: } FSR1Hbits_t;
+[; ;pic12f1822.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1822.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1822.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1822.h: 248: typedef union {
+[; ;pic12f1822.h: 249: struct {
+[; ;pic12f1822.h: 250: unsigned BSR0 :1;
+[; ;pic12f1822.h: 251: unsigned BSR1 :1;
+[; ;pic12f1822.h: 252: unsigned BSR2 :1;
+[; ;pic12f1822.h: 253: unsigned BSR3 :1;
+[; ;pic12f1822.h: 254: unsigned BSR4 :1;
+[; ;pic12f1822.h: 255: };
+[; ;pic12f1822.h: 256: struct {
+[; ;pic12f1822.h: 257: unsigned BSR :5;
+[; ;pic12f1822.h: 258: };
+[; ;pic12f1822.h: 259: } BSRbits_t;
+[; ;pic12f1822.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1822.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1822.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1822.h: 299: typedef union {
+[; ;pic12f1822.h: 300: struct {
+[; ;pic12f1822.h: 301: unsigned WREG0 :8;
+[; ;pic12f1822.h: 302: };
+[; ;pic12f1822.h: 303: } WREGbits_t;
+[; ;pic12f1822.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1822.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1822.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1822.h: 318: typedef union {
+[; ;pic12f1822.h: 319: struct {
+[; ;pic12f1822.h: 320: unsigned PCLATH :7;
+[; ;pic12f1822.h: 321: };
+[; ;pic12f1822.h: 322: } PCLATHbits_t;
+[; ;pic12f1822.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1822.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1822.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1822.h: 337: typedef union {
+[; ;pic12f1822.h: 338: struct {
+[; ;pic12f1822.h: 339: unsigned IOCIF :1;
+[; ;pic12f1822.h: 340: unsigned INTF :1;
+[; ;pic12f1822.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1822.h: 342: unsigned IOCIE :1;
+[; ;pic12f1822.h: 343: unsigned INTE :1;
+[; ;pic12f1822.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1822.h: 345: unsigned PEIE :1;
+[; ;pic12f1822.h: 346: unsigned GIE :1;
+[; ;pic12f1822.h: 347: };
+[; ;pic12f1822.h: 348: struct {
+[; ;pic12f1822.h: 349: unsigned :2;
+[; ;pic12f1822.h: 350: unsigned T0IF :1;
+[; ;pic12f1822.h: 351: unsigned :2;
+[; ;pic12f1822.h: 352: unsigned T0IE :1;
+[; ;pic12f1822.h: 353: };
+[; ;pic12f1822.h: 354: } INTCONbits_t;
+[; ;pic12f1822.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1822.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1822.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1822.h: 414: typedef union {
+[; ;pic12f1822.h: 415: struct {
+[; ;pic12f1822.h: 416: unsigned RA0 :1;
+[; ;pic12f1822.h: 417: unsigned RA1 :1;
+[; ;pic12f1822.h: 418: unsigned RA2 :1;
+[; ;pic12f1822.h: 419: unsigned RA3 :1;
+[; ;pic12f1822.h: 420: unsigned RA4 :1;
+[; ;pic12f1822.h: 421: unsigned RA5 :1;
+[; ;pic12f1822.h: 422: };
+[; ;pic12f1822.h: 423: struct {
+[; ;pic12f1822.h: 424: unsigned AN0 :1;
+[; ;pic12f1822.h: 425: unsigned AN1 :1;
+[; ;pic12f1822.h: 426: unsigned AN2 :1;
+[; ;pic12f1822.h: 427: unsigned :1;
+[; ;pic12f1822.h: 428: unsigned AN3 :1;
+[; ;pic12f1822.h: 429: };
+[; ;pic12f1822.h: 430: struct {
+[; ;pic12f1822.h: 431: unsigned CPS0 :1;
+[; ;pic12f1822.h: 432: unsigned CPS1 :1;
+[; ;pic12f1822.h: 433: unsigned CPS2 :1;
+[; ;pic12f1822.h: 434: unsigned :1;
+[; ;pic12f1822.h: 435: unsigned CPS3 :1;
+[; ;pic12f1822.h: 436: };
+[; ;pic12f1822.h: 437: struct {
+[; ;pic12f1822.h: 438: unsigned C1INP :1;
+[; ;pic12f1822.h: 439: unsigned C1IN0N :1;
+[; ;pic12f1822.h: 440: unsigned C1OUT :1;
+[; ;pic12f1822.h: 441: unsigned :1;
+[; ;pic12f1822.h: 442: unsigned C1IN1N :1;
+[; ;pic12f1822.h: 443: };
+[; ;pic12f1822.h: 444: struct {
+[; ;pic12f1822.h: 445: unsigned DACOUT :1;
+[; ;pic12f1822.h: 446: unsigned SRI :1;
+[; ;pic12f1822.h: 447: unsigned SRQ :1;
+[; ;pic12f1822.h: 448: unsigned :2;
+[; ;pic12f1822.h: 449: unsigned SRNQ :1;
+[; ;pic12f1822.h: 450: };
+[; ;pic12f1822.h: 451: struct {
+[; ;pic12f1822.h: 452: unsigned :1;
+[; ;pic12f1822.h: 453: unsigned SCK :1;
+[; ;pic12f1822.h: 454: unsigned T0CKI :1;
+[; ;pic12f1822.h: 455: unsigned :1;
+[; ;pic12f1822.h: 456: unsigned T1OSO :1;
+[; ;pic12f1822.h: 457: unsigned T1CKI :1;
+[; ;pic12f1822.h: 458: };
+[; ;pic12f1822.h: 459: struct {
+[; ;pic12f1822.h: 460: unsigned :1;
+[; ;pic12f1822.h: 461: unsigned SCL :1;
+[; ;pic12f1822.h: 462: unsigned SDA :1;
+[; ;pic12f1822.h: 463: unsigned nMCLR :1;
+[; ;pic12f1822.h: 464: unsigned CLKR :1;
+[; ;pic12f1822.h: 465: unsigned T1OSI :1;
+[; ;pic12f1822.h: 466: };
+[; ;pic12f1822.h: 467: struct {
+[; ;pic12f1822.h: 468: unsigned MDOUT :1;
+[; ;pic12f1822.h: 469: unsigned MDMIN :1;
+[; ;pic12f1822.h: 470: unsigned MDCIN1 :1;
+[; ;pic12f1822.h: 471: unsigned :1;
+[; ;pic12f1822.h: 472: unsigned MDCIN2 :1;
+[; ;pic12f1822.h: 473: };
+[; ;pic12f1822.h: 474: struct {
+[; ;pic12f1822.h: 475: unsigned :2;
+[; ;pic12f1822.h: 476: unsigned SDI :1;
+[; ;pic12f1822.h: 477: unsigned :1;
+[; ;pic12f1822.h: 478: unsigned OSC2 :1;
+[; ;pic12f1822.h: 479: unsigned OSC1 :1;
+[; ;pic12f1822.h: 480: };
+[; ;pic12f1822.h: 481: struct {
+[; ;pic12f1822.h: 482: unsigned :2;
+[; ;pic12f1822.h: 483: unsigned FLT0 :1;
+[; ;pic12f1822.h: 484: unsigned :1;
+[; ;pic12f1822.h: 485: unsigned CLKOUT :1;
+[; ;pic12f1822.h: 486: unsigned CLKIN :1;
+[; ;pic12f1822.h: 487: };
+[; ;pic12f1822.h: 488: } PORTAbits_t;
+[; ;pic12f1822.h: 489: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1822.h: 698: extern volatile unsigned char PIR1 @ 0x011;
+"700
+[; ;pic12f1822.h: 700: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1822.h: 703: typedef union {
+[; ;pic12f1822.h: 704: struct {
+[; ;pic12f1822.h: 705: unsigned TMR1IF :1;
+[; ;pic12f1822.h: 706: unsigned TMR2IF :1;
+[; ;pic12f1822.h: 707: unsigned CCP1IF :1;
+[; ;pic12f1822.h: 708: unsigned SSP1IF :1;
+[; ;pic12f1822.h: 709: unsigned TXIF :1;
+[; ;pic12f1822.h: 710: unsigned RCIF :1;
+[; ;pic12f1822.h: 711: unsigned ADIF :1;
+[; ;pic12f1822.h: 712: unsigned TMR1GIF :1;
+[; ;pic12f1822.h: 713: };
+[; ;pic12f1822.h: 714: } PIR1bits_t;
+[; ;pic12f1822.h: 715: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1822.h: 759: extern volatile unsigned char PIR2 @ 0x012;
+"761
+[; ;pic12f1822.h: 761: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1822.h: 764: typedef union {
+[; ;pic12f1822.h: 765: struct {
+[; ;pic12f1822.h: 766: unsigned :3;
+[; ;pic12f1822.h: 767: unsigned BCL1IF :1;
+[; ;pic12f1822.h: 768: unsigned EEIF :1;
+[; ;pic12f1822.h: 769: unsigned C1IF :1;
+[; ;pic12f1822.h: 770: unsigned :1;
+[; ;pic12f1822.h: 771: unsigned OSFIF :1;
+[; ;pic12f1822.h: 772: };
+[; ;pic12f1822.h: 773: } PIR2bits_t;
+[; ;pic12f1822.h: 774: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1822.h: 798: extern volatile unsigned char TMR0 @ 0x015;
+"800
+[; ;pic12f1822.h: 800: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1822.h: 803: typedef union {
+[; ;pic12f1822.h: 804: struct {
+[; ;pic12f1822.h: 805: unsigned TMR0 :8;
+[; ;pic12f1822.h: 806: };
+[; ;pic12f1822.h: 807: } TMR0bits_t;
+[; ;pic12f1822.h: 808: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1822.h: 817: extern volatile unsigned short TMR1 @ 0x016;
+"819
+[; ;pic12f1822.h: 819: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1822.h: 823: extern volatile unsigned char TMR1L @ 0x016;
+"825
+[; ;pic12f1822.h: 825: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1822.h: 828: typedef union {
+[; ;pic12f1822.h: 829: struct {
+[; ;pic12f1822.h: 830: unsigned TMR1L :8;
+[; ;pic12f1822.h: 831: };
+[; ;pic12f1822.h: 832: } TMR1Lbits_t;
+[; ;pic12f1822.h: 833: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1822.h: 842: extern volatile unsigned char TMR1H @ 0x017;
+"844
+[; ;pic12f1822.h: 844: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1822.h: 847: typedef union {
+[; ;pic12f1822.h: 848: struct {
+[; ;pic12f1822.h: 849: unsigned TMR1H :8;
+[; ;pic12f1822.h: 850: };
+[; ;pic12f1822.h: 851: } TMR1Hbits_t;
+[; ;pic12f1822.h: 852: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1822.h: 861: extern volatile unsigned char T1CON @ 0x018;
+"863
+[; ;pic12f1822.h: 863: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1822.h: 866: typedef union {
+[; ;pic12f1822.h: 867: struct {
+[; ;pic12f1822.h: 868: unsigned TMR1ON :1;
+[; ;pic12f1822.h: 869: unsigned :1;
+[; ;pic12f1822.h: 870: unsigned nT1SYNC :1;
+[; ;pic12f1822.h: 871: unsigned T1OSCEN :1;
+[; ;pic12f1822.h: 872: unsigned T1CKPS0 :1;
+[; ;pic12f1822.h: 873: unsigned T1CKPS1 :1;
+[; ;pic12f1822.h: 874: unsigned TMR1CS0 :1;
+[; ;pic12f1822.h: 875: unsigned TMR1CS1 :1;
+[; ;pic12f1822.h: 876: };
+[; ;pic12f1822.h: 877: struct {
+[; ;pic12f1822.h: 878: unsigned :4;
+[; ;pic12f1822.h: 879: unsigned T1CKPS :2;
+[; ;pic12f1822.h: 880: unsigned TMR1CS :2;
+[; ;pic12f1822.h: 881: };
+[; ;pic12f1822.h: 882: } T1CONbits_t;
+[; ;pic12f1822.h: 883: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1822.h: 932: extern volatile unsigned char T1GCON @ 0x019;
+"934
+[; ;pic12f1822.h: 934: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1822.h: 937: typedef union {
+[; ;pic12f1822.h: 938: struct {
+[; ;pic12f1822.h: 939: unsigned T1GSS0 :1;
+[; ;pic12f1822.h: 940: unsigned T1GSS1 :1;
+[; ;pic12f1822.h: 941: unsigned T1GVAL :1;
+[; ;pic12f1822.h: 942: unsigned T1GGO_nDONE :1;
+[; ;pic12f1822.h: 943: unsigned T1GSPM :1;
+[; ;pic12f1822.h: 944: unsigned T1GTM :1;
+[; ;pic12f1822.h: 945: unsigned T1GPOL :1;
+[; ;pic12f1822.h: 946: unsigned TMR1GE :1;
+[; ;pic12f1822.h: 947: };
+[; ;pic12f1822.h: 948: struct {
+[; ;pic12f1822.h: 949: unsigned T1GSS :2;
+[; ;pic12f1822.h: 950: unsigned :1;
+[; ;pic12f1822.h: 951: unsigned T1GGO :1;
+[; ;pic12f1822.h: 952: };
+[; ;pic12f1822.h: 953: } T1GCONbits_t;
+[; ;pic12f1822.h: 954: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1822.h: 1008: extern volatile unsigned char TMR2 @ 0x01A;
+"1010
+[; ;pic12f1822.h: 1010: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1822.h: 1013: typedef union {
+[; ;pic12f1822.h: 1014: struct {
+[; ;pic12f1822.h: 1015: unsigned TMR2 :8;
+[; ;pic12f1822.h: 1016: };
+[; ;pic12f1822.h: 1017: } TMR2bits_t;
+[; ;pic12f1822.h: 1018: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1822.h: 1027: extern volatile unsigned char PR2 @ 0x01B;
+"1029
+[; ;pic12f1822.h: 1029: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1822.h: 1032: typedef union {
+[; ;pic12f1822.h: 1033: struct {
+[; ;pic12f1822.h: 1034: unsigned PR2 :8;
+[; ;pic12f1822.h: 1035: };
+[; ;pic12f1822.h: 1036: } PR2bits_t;
+[; ;pic12f1822.h: 1037: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1822.h: 1046: extern volatile unsigned char T2CON @ 0x01C;
+"1048
+[; ;pic12f1822.h: 1048: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1822.h: 1051: typedef union {
+[; ;pic12f1822.h: 1052: struct {
+[; ;pic12f1822.h: 1053: unsigned T2CKPS0 :1;
+[; ;pic12f1822.h: 1054: unsigned T2CKPS1 :1;
+[; ;pic12f1822.h: 1055: unsigned TMR2ON :1;
+[; ;pic12f1822.h: 1056: unsigned T2OUTPS0 :1;
+[; ;pic12f1822.h: 1057: unsigned T2OUTPS1 :1;
+[; ;pic12f1822.h: 1058: unsigned T2OUTPS2 :1;
+[; ;pic12f1822.h: 1059: unsigned T2OUTPS3 :1;
+[; ;pic12f1822.h: 1060: };
+[; ;pic12f1822.h: 1061: struct {
+[; ;pic12f1822.h: 1062: unsigned T2CKPS :2;
+[; ;pic12f1822.h: 1063: unsigned :1;
+[; ;pic12f1822.h: 1064: unsigned T2OUTPS :4;
+[; ;pic12f1822.h: 1065: };
+[; ;pic12f1822.h: 1066: } T2CONbits_t;
+[; ;pic12f1822.h: 1067: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1822.h: 1116: extern volatile unsigned char CPSCON0 @ 0x01E;
+"1118
+[; ;pic12f1822.h: 1118: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1822.h: 1121: typedef union {
+[; ;pic12f1822.h: 1122: struct {
+[; ;pic12f1822.h: 1123: unsigned T0XCS :1;
+[; ;pic12f1822.h: 1124: unsigned CPSOUT :1;
+[; ;pic12f1822.h: 1125: unsigned CPSRNG0 :1;
+[; ;pic12f1822.h: 1126: unsigned CPSRNG1 :1;
+[; ;pic12f1822.h: 1127: unsigned :2;
+[; ;pic12f1822.h: 1128: unsigned CPSRM :1;
+[; ;pic12f1822.h: 1129: unsigned CPSON :1;
+[; ;pic12f1822.h: 1130: };
+[; ;pic12f1822.h: 1131: struct {
+[; ;pic12f1822.h: 1132: unsigned :2;
+[; ;pic12f1822.h: 1133: unsigned CPSRNG :2;
+[; ;pic12f1822.h: 1134: };
+[; ;pic12f1822.h: 1135: } CPSCON0bits_t;
+[; ;pic12f1822.h: 1136: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1822.h: 1175: extern volatile unsigned char CPSCON1 @ 0x01F;
+"1177
+[; ;pic12f1822.h: 1177: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1822.h: 1180: typedef union {
+[; ;pic12f1822.h: 1181: struct {
+[; ;pic12f1822.h: 1182: unsigned CPSCH0 :1;
+[; ;pic12f1822.h: 1183: unsigned CPSCH1 :1;
+[; ;pic12f1822.h: 1184: };
+[; ;pic12f1822.h: 1185: struct {
+[; ;pic12f1822.h: 1186: unsigned CPSCH :2;
+[; ;pic12f1822.h: 1187: };
+[; ;pic12f1822.h: 1188: } CPSCON1bits_t;
+[; ;pic12f1822.h: 1189: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1822.h: 1208: extern volatile unsigned char TRISA @ 0x08C;
+"1210
+[; ;pic12f1822.h: 1210: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1822.h: 1213: typedef union {
+[; ;pic12f1822.h: 1214: struct {
+[; ;pic12f1822.h: 1215: unsigned TRISA0 :1;
+[; ;pic12f1822.h: 1216: unsigned TRISA1 :1;
+[; ;pic12f1822.h: 1217: unsigned TRISA2 :1;
+[; ;pic12f1822.h: 1218: unsigned TRISA3 :1;
+[; ;pic12f1822.h: 1219: unsigned TRISA4 :1;
+[; ;pic12f1822.h: 1220: unsigned TRISA5 :1;
+[; ;pic12f1822.h: 1221: };
+[; ;pic12f1822.h: 1222: } TRISAbits_t;
+[; ;pic12f1822.h: 1223: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1822.h: 1257: extern volatile unsigned char PIE1 @ 0x091;
+"1259
+[; ;pic12f1822.h: 1259: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1822.h: 1262: typedef union {
+[; ;pic12f1822.h: 1263: struct {
+[; ;pic12f1822.h: 1264: unsigned TMR1IE :1;
+[; ;pic12f1822.h: 1265: unsigned TMR2IE :1;
+[; ;pic12f1822.h: 1266: unsigned CCP1IE :1;
+[; ;pic12f1822.h: 1267: unsigned SSP1IE :1;
+[; ;pic12f1822.h: 1268: unsigned TXIE :1;
+[; ;pic12f1822.h: 1269: unsigned RCIE :1;
+[; ;pic12f1822.h: 1270: unsigned ADIE :1;
+[; ;pic12f1822.h: 1271: unsigned TMR1GIE :1;
+[; ;pic12f1822.h: 1272: };
+[; ;pic12f1822.h: 1273: } PIE1bits_t;
+[; ;pic12f1822.h: 1274: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1822.h: 1318: extern volatile unsigned char PIE2 @ 0x092;
+"1320
+[; ;pic12f1822.h: 1320: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1822.h: 1323: typedef union {
+[; ;pic12f1822.h: 1324: struct {
+[; ;pic12f1822.h: 1325: unsigned :3;
+[; ;pic12f1822.h: 1326: unsigned BCL1IE :1;
+[; ;pic12f1822.h: 1327: unsigned EEIE :1;
+[; ;pic12f1822.h: 1328: unsigned C1IE :1;
+[; ;pic12f1822.h: 1329: unsigned :1;
+[; ;pic12f1822.h: 1330: unsigned OSFIE :1;
+[; ;pic12f1822.h: 1331: };
+[; ;pic12f1822.h: 1332: } PIE2bits_t;
+[; ;pic12f1822.h: 1333: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1822.h: 1357: extern volatile unsigned char OPTION_REG @ 0x095;
+"1359
+[; ;pic12f1822.h: 1359: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1822.h: 1362: typedef union {
+[; ;pic12f1822.h: 1363: struct {
+[; ;pic12f1822.h: 1364: unsigned PS0 :1;
+[; ;pic12f1822.h: 1365: unsigned PS1 :1;
+[; ;pic12f1822.h: 1366: unsigned PS2 :1;
+[; ;pic12f1822.h: 1367: unsigned PSA :1;
+[; ;pic12f1822.h: 1368: unsigned TMR0SE :1;
+[; ;pic12f1822.h: 1369: unsigned TMR0CS :1;
+[; ;pic12f1822.h: 1370: unsigned INTEDG :1;
+[; ;pic12f1822.h: 1371: unsigned nWPUEN :1;
+[; ;pic12f1822.h: 1372: };
+[; ;pic12f1822.h: 1373: struct {
+[; ;pic12f1822.h: 1374: unsigned PS :3;
+[; ;pic12f1822.h: 1375: unsigned :1;
+[; ;pic12f1822.h: 1376: unsigned T0SE :1;
+[; ;pic12f1822.h: 1377: unsigned T0CS :1;
+[; ;pic12f1822.h: 1378: };
+[; ;pic12f1822.h: 1379: } OPTION_REGbits_t;
+[; ;pic12f1822.h: 1380: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1822.h: 1439: extern volatile unsigned char PCON @ 0x096;
+"1441
+[; ;pic12f1822.h: 1441: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1822.h: 1444: typedef union {
+[; ;pic12f1822.h: 1445: struct {
+[; ;pic12f1822.h: 1446: unsigned nBOR :1;
+[; ;pic12f1822.h: 1447: unsigned nPOR :1;
+[; ;pic12f1822.h: 1448: unsigned nRI :1;
+[; ;pic12f1822.h: 1449: unsigned nRMCLR :1;
+[; ;pic12f1822.h: 1450: unsigned :2;
+[; ;pic12f1822.h: 1451: unsigned STKUNF :1;
+[; ;pic12f1822.h: 1452: unsigned STKOVF :1;
+[; ;pic12f1822.h: 1453: };
+[; ;pic12f1822.h: 1454: } PCONbits_t;
+[; ;pic12f1822.h: 1455: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1822.h: 1489: extern volatile unsigned char WDTCON @ 0x097;
+"1491
+[; ;pic12f1822.h: 1491: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1822.h: 1494: typedef union {
+[; ;pic12f1822.h: 1495: struct {
+[; ;pic12f1822.h: 1496: unsigned SWDTEN :1;
+[; ;pic12f1822.h: 1497: unsigned WDTPS0 :1;
+[; ;pic12f1822.h: 1498: unsigned WDTPS1 :1;
+[; ;pic12f1822.h: 1499: unsigned WDTPS2 :1;
+[; ;pic12f1822.h: 1500: unsigned WDTPS3 :1;
+[; ;pic12f1822.h: 1501: unsigned WDTPS4 :1;
+[; ;pic12f1822.h: 1502: };
+[; ;pic12f1822.h: 1503: struct {
+[; ;pic12f1822.h: 1504: unsigned :1;
+[; ;pic12f1822.h: 1505: unsigned WDTPS :5;
+[; ;pic12f1822.h: 1506: };
+[; ;pic12f1822.h: 1507: } WDTCONbits_t;
+[; ;pic12f1822.h: 1508: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1822.h: 1547: extern volatile unsigned char OSCTUNE @ 0x098;
+"1549
+[; ;pic12f1822.h: 1549: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1822.h: 1552: typedef union {
+[; ;pic12f1822.h: 1553: struct {
+[; ;pic12f1822.h: 1554: unsigned TUN0 :1;
+[; ;pic12f1822.h: 1555: unsigned TUN1 :1;
+[; ;pic12f1822.h: 1556: unsigned TUN2 :1;
+[; ;pic12f1822.h: 1557: unsigned TUN3 :1;
+[; ;pic12f1822.h: 1558: unsigned TUN4 :1;
+[; ;pic12f1822.h: 1559: unsigned TUN5 :1;
+[; ;pic12f1822.h: 1560: };
+[; ;pic12f1822.h: 1561: struct {
+[; ;pic12f1822.h: 1562: unsigned TUN :6;
+[; ;pic12f1822.h: 1563: };
+[; ;pic12f1822.h: 1564: } OSCTUNEbits_t;
+[; ;pic12f1822.h: 1565: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1822.h: 1604: extern volatile unsigned char OSCCON @ 0x099;
+"1606
+[; ;pic12f1822.h: 1606: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1822.h: 1609: typedef union {
+[; ;pic12f1822.h: 1610: struct {
+[; ;pic12f1822.h: 1611: unsigned SCS0 :1;
+[; ;pic12f1822.h: 1612: unsigned SCS1 :1;
+[; ;pic12f1822.h: 1613: unsigned :1;
+[; ;pic12f1822.h: 1614: unsigned IRCF0 :1;
+[; ;pic12f1822.h: 1615: unsigned IRCF1 :1;
+[; ;pic12f1822.h: 1616: unsigned IRCF2 :1;
+[; ;pic12f1822.h: 1617: unsigned IRCF3 :1;
+[; ;pic12f1822.h: 1618: unsigned SPLLEN :1;
+[; ;pic12f1822.h: 1619: };
+[; ;pic12f1822.h: 1620: struct {
+[; ;pic12f1822.h: 1621: unsigned SCS :2;
+[; ;pic12f1822.h: 1622: unsigned :1;
+[; ;pic12f1822.h: 1623: unsigned IRCF :4;
+[; ;pic12f1822.h: 1624: };
+[; ;pic12f1822.h: 1625: } OSCCONbits_t;
+[; ;pic12f1822.h: 1626: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1822.h: 1675: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1677
+[; ;pic12f1822.h: 1677: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1822.h: 1680: typedef union {
+[; ;pic12f1822.h: 1681: struct {
+[; ;pic12f1822.h: 1682: unsigned HFIOFS :1;
+[; ;pic12f1822.h: 1683: unsigned LFIOFR :1;
+[; ;pic12f1822.h: 1684: unsigned MFIOFR :1;
+[; ;pic12f1822.h: 1685: unsigned HFIOFL :1;
+[; ;pic12f1822.h: 1686: unsigned HFIOFR :1;
+[; ;pic12f1822.h: 1687: unsigned OSTS :1;
+[; ;pic12f1822.h: 1688: unsigned PLLR :1;
+[; ;pic12f1822.h: 1689: unsigned T1OSCR :1;
+[; ;pic12f1822.h: 1690: };
+[; ;pic12f1822.h: 1691: } OSCSTATbits_t;
+[; ;pic12f1822.h: 1692: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1822.h: 1736: extern volatile unsigned short ADRES @ 0x09B;
+"1738
+[; ;pic12f1822.h: 1738: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1822.h: 1742: extern volatile unsigned char ADRESL @ 0x09B;
+"1744
+[; ;pic12f1822.h: 1744: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1822.h: 1747: typedef union {
+[; ;pic12f1822.h: 1748: struct {
+[; ;pic12f1822.h: 1749: unsigned ADRESL :8;
+[; ;pic12f1822.h: 1750: };
+[; ;pic12f1822.h: 1751: } ADRESLbits_t;
+[; ;pic12f1822.h: 1752: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1822.h: 1761: extern volatile unsigned char ADRESH @ 0x09C;
+"1763
+[; ;pic12f1822.h: 1763: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1822.h: 1766: typedef union {
+[; ;pic12f1822.h: 1767: struct {
+[; ;pic12f1822.h: 1768: unsigned ADRESH :8;
+[; ;pic12f1822.h: 1769: };
+[; ;pic12f1822.h: 1770: } ADRESHbits_t;
+[; ;pic12f1822.h: 1771: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1822.h: 1780: extern volatile unsigned char ADCON0 @ 0x09D;
+"1782
+[; ;pic12f1822.h: 1782: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1822.h: 1785: typedef union {
+[; ;pic12f1822.h: 1786: struct {
+[; ;pic12f1822.h: 1787: unsigned ADON :1;
+[; ;pic12f1822.h: 1788: unsigned GO_nDONE :1;
+[; ;pic12f1822.h: 1789: unsigned CHS0 :1;
+[; ;pic12f1822.h: 1790: unsigned CHS1 :1;
+[; ;pic12f1822.h: 1791: unsigned CHS2 :1;
+[; ;pic12f1822.h: 1792: unsigned CHS3 :1;
+[; ;pic12f1822.h: 1793: unsigned CHS4 :1;
+[; ;pic12f1822.h: 1794: };
+[; ;pic12f1822.h: 1795: struct {
+[; ;pic12f1822.h: 1796: unsigned :1;
+[; ;pic12f1822.h: 1797: unsigned ADGO :1;
+[; ;pic12f1822.h: 1798: unsigned CHS :5;
+[; ;pic12f1822.h: 1799: };
+[; ;pic12f1822.h: 1800: struct {
+[; ;pic12f1822.h: 1801: unsigned :1;
+[; ;pic12f1822.h: 1802: unsigned GO :1;
+[; ;pic12f1822.h: 1803: };
+[; ;pic12f1822.h: 1804: struct {
+[; ;pic12f1822.h: 1805: unsigned :1;
+[; ;pic12f1822.h: 1806: unsigned nDONE :1;
+[; ;pic12f1822.h: 1807: };
+[; ;pic12f1822.h: 1808: } ADCON0bits_t;
+[; ;pic12f1822.h: 1809: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1822.h: 1868: extern volatile unsigned char ADCON1 @ 0x09E;
+"1870
+[; ;pic12f1822.h: 1870: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1822.h: 1873: typedef union {
+[; ;pic12f1822.h: 1874: struct {
+[; ;pic12f1822.h: 1875: unsigned ADPREF0 :1;
+[; ;pic12f1822.h: 1876: unsigned ADPREF1 :1;
+[; ;pic12f1822.h: 1877: unsigned :2;
+[; ;pic12f1822.h: 1878: unsigned ADCS0 :1;
+[; ;pic12f1822.h: 1879: unsigned ADCS1 :1;
+[; ;pic12f1822.h: 1880: unsigned ADCS2 :1;
+[; ;pic12f1822.h: 1881: unsigned ADFM :1;
+[; ;pic12f1822.h: 1882: };
+[; ;pic12f1822.h: 1883: struct {
+[; ;pic12f1822.h: 1884: unsigned ADPREF :2;
+[; ;pic12f1822.h: 1885: unsigned :2;
+[; ;pic12f1822.h: 1886: unsigned ADCS :3;
+[; ;pic12f1822.h: 1887: };
+[; ;pic12f1822.h: 1888: } ADCON1bits_t;
+[; ;pic12f1822.h: 1889: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1822.h: 1933: extern volatile unsigned char LATA @ 0x10C;
+"1935
+[; ;pic12f1822.h: 1935: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1822.h: 1938: typedef union {
+[; ;pic12f1822.h: 1939: struct {
+[; ;pic12f1822.h: 1940: unsigned LATA0 :1;
+[; ;pic12f1822.h: 1941: unsigned LATA1 :1;
+[; ;pic12f1822.h: 1942: unsigned LATA2 :1;
+[; ;pic12f1822.h: 1943: unsigned :1;
+[; ;pic12f1822.h: 1944: unsigned LATA4 :1;
+[; ;pic12f1822.h: 1945: unsigned LATA5 :1;
+[; ;pic12f1822.h: 1946: };
+[; ;pic12f1822.h: 1947: } LATAbits_t;
+[; ;pic12f1822.h: 1948: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1822.h: 1977: extern volatile unsigned char CM1CON0 @ 0x111;
+"1979
+[; ;pic12f1822.h: 1979: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1822.h: 1982: typedef union {
+[; ;pic12f1822.h: 1983: struct {
+[; ;pic12f1822.h: 1984: unsigned C1SYNC :1;
+[; ;pic12f1822.h: 1985: unsigned C1HYS :1;
+[; ;pic12f1822.h: 1986: unsigned C1SP :1;
+[; ;pic12f1822.h: 1987: unsigned :1;
+[; ;pic12f1822.h: 1988: unsigned C1POL :1;
+[; ;pic12f1822.h: 1989: unsigned C1OE :1;
+[; ;pic12f1822.h: 1990: unsigned C1OUT :1;
+[; ;pic12f1822.h: 1991: unsigned C1ON :1;
+[; ;pic12f1822.h: 1992: };
+[; ;pic12f1822.h: 1993: } CM1CON0bits_t;
+[; ;pic12f1822.h: 1994: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1822.h: 2033: extern volatile unsigned char CM1CON1 @ 0x112;
+"2035
+[; ;pic12f1822.h: 2035: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1822.h: 2038: typedef union {
+[; ;pic12f1822.h: 2039: struct {
+[; ;pic12f1822.h: 2040: unsigned C1NCH0 :1;
+[; ;pic12f1822.h: 2041: unsigned :3;
+[; ;pic12f1822.h: 2042: unsigned C1PCH0 :1;
+[; ;pic12f1822.h: 2043: unsigned C1PCH1 :1;
+[; ;pic12f1822.h: 2044: unsigned C1INTN :1;
+[; ;pic12f1822.h: 2045: unsigned C1INTP :1;
+[; ;pic12f1822.h: 2046: };
+[; ;pic12f1822.h: 2047: struct {
+[; ;pic12f1822.h: 2048: unsigned :4;
+[; ;pic12f1822.h: 2049: unsigned C1PCH :2;
+[; ;pic12f1822.h: 2050: };
+[; ;pic12f1822.h: 2051: } CM1CON1bits_t;
+[; ;pic12f1822.h: 2052: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1822.h: 2086: extern volatile unsigned char CMOUT @ 0x115;
+"2088
+[; ;pic12f1822.h: 2088: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1822.h: 2091: typedef union {
+[; ;pic12f1822.h: 2092: struct {
+[; ;pic12f1822.h: 2093: unsigned MC1OUT :1;
+[; ;pic12f1822.h: 2094: };
+[; ;pic12f1822.h: 2095: } CMOUTbits_t;
+[; ;pic12f1822.h: 2096: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1822.h: 2105: extern volatile unsigned char BORCON @ 0x116;
+"2107
+[; ;pic12f1822.h: 2107: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1822.h: 2110: typedef union {
+[; ;pic12f1822.h: 2111: struct {
+[; ;pic12f1822.h: 2112: unsigned BORRDY :1;
+[; ;pic12f1822.h: 2113: unsigned :6;
+[; ;pic12f1822.h: 2114: unsigned SBOREN :1;
+[; ;pic12f1822.h: 2115: };
+[; ;pic12f1822.h: 2116: } BORCONbits_t;
+[; ;pic12f1822.h: 2117: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1822.h: 2131: extern volatile unsigned char FVRCON @ 0x117;
+"2133
+[; ;pic12f1822.h: 2133: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1822.h: 2136: typedef union {
+[; ;pic12f1822.h: 2137: struct {
+[; ;pic12f1822.h: 2138: unsigned ADFVR0 :1;
+[; ;pic12f1822.h: 2139: unsigned ADFVR1 :1;
+[; ;pic12f1822.h: 2140: unsigned CDAFVR0 :1;
+[; ;pic12f1822.h: 2141: unsigned CDAFVR1 :1;
+[; ;pic12f1822.h: 2142: unsigned TSRNG :1;
+[; ;pic12f1822.h: 2143: unsigned TSEN :1;
+[; ;pic12f1822.h: 2144: unsigned FVRRDY :1;
+[; ;pic12f1822.h: 2145: unsigned FVREN :1;
+[; ;pic12f1822.h: 2146: };
+[; ;pic12f1822.h: 2147: struct {
+[; ;pic12f1822.h: 2148: unsigned ADFVR :2;
+[; ;pic12f1822.h: 2149: unsigned CDAFVR :2;
+[; ;pic12f1822.h: 2150: };
+[; ;pic12f1822.h: 2151: } FVRCONbits_t;
+[; ;pic12f1822.h: 2152: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1822.h: 2206: extern volatile unsigned char DACCON0 @ 0x118;
+"2208
+[; ;pic12f1822.h: 2208: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1822.h: 2211: typedef union {
+[; ;pic12f1822.h: 2212: struct {
+[; ;pic12f1822.h: 2213: unsigned :2;
+[; ;pic12f1822.h: 2214: unsigned DACPSS0 :1;
+[; ;pic12f1822.h: 2215: unsigned DACPSS1 :1;
+[; ;pic12f1822.h: 2216: unsigned :1;
+[; ;pic12f1822.h: 2217: unsigned DACOE :1;
+[; ;pic12f1822.h: 2218: unsigned DACLPS :1;
+[; ;pic12f1822.h: 2219: unsigned DACEN :1;
+[; ;pic12f1822.h: 2220: };
+[; ;pic12f1822.h: 2221: struct {
+[; ;pic12f1822.h: 2222: unsigned :2;
+[; ;pic12f1822.h: 2223: unsigned DACPSS :2;
+[; ;pic12f1822.h: 2224: };
+[; ;pic12f1822.h: 2225: } DACCON0bits_t;
+[; ;pic12f1822.h: 2226: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1822.h: 2260: extern volatile unsigned char DACCON1 @ 0x119;
+"2262
+[; ;pic12f1822.h: 2262: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1822.h: 2265: typedef union {
+[; ;pic12f1822.h: 2266: struct {
+[; ;pic12f1822.h: 2267: unsigned DACR0 :1;
+[; ;pic12f1822.h: 2268: unsigned DACR1 :1;
+[; ;pic12f1822.h: 2269: unsigned DACR2 :1;
+[; ;pic12f1822.h: 2270: unsigned DACR3 :1;
+[; ;pic12f1822.h: 2271: unsigned DACR4 :1;
+[; ;pic12f1822.h: 2272: };
+[; ;pic12f1822.h: 2273: struct {
+[; ;pic12f1822.h: 2274: unsigned DACR :5;
+[; ;pic12f1822.h: 2275: };
+[; ;pic12f1822.h: 2276: } DACCON1bits_t;
+[; ;pic12f1822.h: 2277: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1822.h: 2311: extern volatile unsigned char SRCON0 @ 0x11A;
+"2313
+[; ;pic12f1822.h: 2313: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1822.h: 2316: typedef union {
+[; ;pic12f1822.h: 2317: struct {
+[; ;pic12f1822.h: 2318: unsigned SRPR :1;
+[; ;pic12f1822.h: 2319: unsigned SRPS :1;
+[; ;pic12f1822.h: 2320: unsigned SRNQEN :1;
+[; ;pic12f1822.h: 2321: unsigned SRQEN :1;
+[; ;pic12f1822.h: 2322: unsigned SRCLK0 :1;
+[; ;pic12f1822.h: 2323: unsigned SRCLK1 :1;
+[; ;pic12f1822.h: 2324: unsigned SRCLK2 :1;
+[; ;pic12f1822.h: 2325: unsigned SRLEN :1;
+[; ;pic12f1822.h: 2326: };
+[; ;pic12f1822.h: 2327: struct {
+[; ;pic12f1822.h: 2328: unsigned :4;
+[; ;pic12f1822.h: 2329: unsigned SRCLK :3;
+[; ;pic12f1822.h: 2330: };
+[; ;pic12f1822.h: 2331: } SRCON0bits_t;
+[; ;pic12f1822.h: 2332: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1822.h: 2381: extern volatile unsigned char SRCON1 @ 0x11B;
+"2383
+[; ;pic12f1822.h: 2383: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1822.h: 2386: typedef union {
+[; ;pic12f1822.h: 2387: struct {
+[; ;pic12f1822.h: 2388: unsigned SRRC1E :1;
+[; ;pic12f1822.h: 2389: unsigned :1;
+[; ;pic12f1822.h: 2390: unsigned SRRCKE :1;
+[; ;pic12f1822.h: 2391: unsigned SRRPE :1;
+[; ;pic12f1822.h: 2392: unsigned SRSC1E :1;
+[; ;pic12f1822.h: 2393: unsigned :1;
+[; ;pic12f1822.h: 2394: unsigned SRSCKE :1;
+[; ;pic12f1822.h: 2395: unsigned SRSPE :1;
+[; ;pic12f1822.h: 2396: };
+[; ;pic12f1822.h: 2397: } SRCON1bits_t;
+[; ;pic12f1822.h: 2398: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1822.h: 2432: extern volatile unsigned char APFCON @ 0x11D;
+"2434
+[; ;pic12f1822.h: 2434: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1822.h: 2437: extern volatile unsigned char APFCON0 @ 0x11D;
+"2439
+[; ;pic12f1822.h: 2439: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1822.h: 2442: typedef union {
+[; ;pic12f1822.h: 2443: struct {
+[; ;pic12f1822.h: 2444: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2445: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2446: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2447: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2448: unsigned :1;
+[; ;pic12f1822.h: 2449: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2450: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2451: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2452: };
+[; ;pic12f1822.h: 2453: struct {
+[; ;pic12f1822.h: 2454: unsigned :5;
+[; ;pic12f1822.h: 2455: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2456: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2457: };
+[; ;pic12f1822.h: 2458: } APFCONbits_t;
+[; ;pic12f1822.h: 2459: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1822.h: 2507: typedef union {
+[; ;pic12f1822.h: 2508: struct {
+[; ;pic12f1822.h: 2509: unsigned CCP1SEL :1;
+[; ;pic12f1822.h: 2510: unsigned P1BSEL :1;
+[; ;pic12f1822.h: 2511: unsigned TXCKSEL :1;
+[; ;pic12f1822.h: 2512: unsigned T1GSEL :1;
+[; ;pic12f1822.h: 2513: unsigned :1;
+[; ;pic12f1822.h: 2514: unsigned SSSEL :1;
+[; ;pic12f1822.h: 2515: unsigned SDOSEL :1;
+[; ;pic12f1822.h: 2516: unsigned RXDTSEL :1;
+[; ;pic12f1822.h: 2517: };
+[; ;pic12f1822.h: 2518: struct {
+[; ;pic12f1822.h: 2519: unsigned :5;
+[; ;pic12f1822.h: 2520: unsigned SS1SEL :1;
+[; ;pic12f1822.h: 2521: unsigned SDO1SEL :1;
+[; ;pic12f1822.h: 2522: };
+[; ;pic12f1822.h: 2523: } APFCON0bits_t;
+[; ;pic12f1822.h: 2524: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1822.h: 2573: extern volatile unsigned char ANSELA @ 0x18C;
+"2575
+[; ;pic12f1822.h: 2575: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1822.h: 2578: typedef union {
+[; ;pic12f1822.h: 2579: struct {
+[; ;pic12f1822.h: 2580: unsigned ANSA0 :1;
+[; ;pic12f1822.h: 2581: unsigned ANSA1 :1;
+[; ;pic12f1822.h: 2582: unsigned ANSA2 :1;
+[; ;pic12f1822.h: 2583: unsigned :1;
+[; ;pic12f1822.h: 2584: unsigned ANSA4 :1;
+[; ;pic12f1822.h: 2585: };
+[; ;pic12f1822.h: 2586: struct {
+[; ;pic12f1822.h: 2587: unsigned ANSELA :5;
+[; ;pic12f1822.h: 2588: };
+[; ;pic12f1822.h: 2589: } ANSELAbits_t;
+[; ;pic12f1822.h: 2590: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1822.h: 2619: extern volatile unsigned short EEADR @ 0x191;
+"2621
+[; ;pic12f1822.h: 2621: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1822.h: 2625: extern volatile unsigned char EEADRL @ 0x191;
+"2627
+[; ;pic12f1822.h: 2627: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1822.h: 2630: typedef union {
+[; ;pic12f1822.h: 2631: struct {
+[; ;pic12f1822.h: 2632: unsigned EEADRL :8;
+[; ;pic12f1822.h: 2633: };
+[; ;pic12f1822.h: 2634: } EEADRLbits_t;
+[; ;pic12f1822.h: 2635: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1822.h: 2644: extern volatile unsigned char EEADRH @ 0x192;
+"2646
+[; ;pic12f1822.h: 2646: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1822.h: 2649: typedef union {
+[; ;pic12f1822.h: 2650: struct {
+[; ;pic12f1822.h: 2651: unsigned EEADRH :7;
+[; ;pic12f1822.h: 2652: };
+[; ;pic12f1822.h: 2653: } EEADRHbits_t;
+[; ;pic12f1822.h: 2654: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1822.h: 2663: extern volatile unsigned short EEDAT @ 0x193;
+"2665
+[; ;pic12f1822.h: 2665: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1822.h: 2669: extern volatile unsigned char EEDATL @ 0x193;
+"2671
+[; ;pic12f1822.h: 2671: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1822.h: 2674: extern volatile unsigned char EEDATA @ 0x193;
+"2676
+[; ;pic12f1822.h: 2676: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1822.h: 2679: typedef union {
+[; ;pic12f1822.h: 2680: struct {
+[; ;pic12f1822.h: 2681: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2682: };
+[; ;pic12f1822.h: 2683: } EEDATLbits_t;
+[; ;pic12f1822.h: 2684: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1822.h: 2692: typedef union {
+[; ;pic12f1822.h: 2693: struct {
+[; ;pic12f1822.h: 2694: unsigned EEDATL :8;
+[; ;pic12f1822.h: 2695: };
+[; ;pic12f1822.h: 2696: } EEDATAbits_t;
+[; ;pic12f1822.h: 2697: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1822.h: 2706: extern volatile unsigned char EEDATH @ 0x194;
+"2708
+[; ;pic12f1822.h: 2708: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1822.h: 2711: typedef union {
+[; ;pic12f1822.h: 2712: struct {
+[; ;pic12f1822.h: 2713: unsigned EEDATH :6;
+[; ;pic12f1822.h: 2714: };
+[; ;pic12f1822.h: 2715: } EEDATHbits_t;
+[; ;pic12f1822.h: 2716: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1822.h: 2725: extern volatile unsigned char EECON1 @ 0x195;
+"2727
+[; ;pic12f1822.h: 2727: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1822.h: 2730: typedef union {
+[; ;pic12f1822.h: 2731: struct {
+[; ;pic12f1822.h: 2732: unsigned RD :1;
+[; ;pic12f1822.h: 2733: unsigned WR :1;
+[; ;pic12f1822.h: 2734: unsigned WREN :1;
+[; ;pic12f1822.h: 2735: unsigned WRERR :1;
+[; ;pic12f1822.h: 2736: unsigned FREE :1;
+[; ;pic12f1822.h: 2737: unsigned LWLO :1;
+[; ;pic12f1822.h: 2738: unsigned CFGS :1;
+[; ;pic12f1822.h: 2739: unsigned EEPGD :1;
+[; ;pic12f1822.h: 2740: };
+[; ;pic12f1822.h: 2741: } EECON1bits_t;
+[; ;pic12f1822.h: 2742: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1822.h: 2786: extern volatile unsigned char EECON2 @ 0x196;
+"2788
+[; ;pic12f1822.h: 2788: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1822.h: 2791: typedef union {
+[; ;pic12f1822.h: 2792: struct {
+[; ;pic12f1822.h: 2793: unsigned EECON2 :8;
+[; ;pic12f1822.h: 2794: };
+[; ;pic12f1822.h: 2795: } EECON2bits_t;
+[; ;pic12f1822.h: 2796: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1822.h: 2805: extern volatile unsigned char RCREG @ 0x199;
+"2807
+[; ;pic12f1822.h: 2807: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1822.h: 2810: typedef union {
+[; ;pic12f1822.h: 2811: struct {
+[; ;pic12f1822.h: 2812: unsigned RCREG :8;
+[; ;pic12f1822.h: 2813: };
+[; ;pic12f1822.h: 2814: } RCREGbits_t;
+[; ;pic12f1822.h: 2815: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1822.h: 2824: extern volatile unsigned char TXREG @ 0x19A;
+"2826
+[; ;pic12f1822.h: 2826: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1822.h: 2829: typedef union {
+[; ;pic12f1822.h: 2830: struct {
+[; ;pic12f1822.h: 2831: unsigned TXREG :8;
+[; ;pic12f1822.h: 2832: };
+[; ;pic12f1822.h: 2833: } TXREGbits_t;
+[; ;pic12f1822.h: 2834: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1822.h: 2843: extern volatile unsigned char SPBRGL @ 0x19B;
+"2845
+[; ;pic12f1822.h: 2845: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1822.h: 2848: extern volatile unsigned char SPBRG @ 0x19B;
+"2850
+[; ;pic12f1822.h: 2850: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1822.h: 2853: typedef union {
+[; ;pic12f1822.h: 2854: struct {
+[; ;pic12f1822.h: 2855: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2856: };
+[; ;pic12f1822.h: 2857: } SPBRGLbits_t;
+[; ;pic12f1822.h: 2858: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1822.h: 2866: typedef union {
+[; ;pic12f1822.h: 2867: struct {
+[; ;pic12f1822.h: 2868: unsigned SPBRGL :8;
+[; ;pic12f1822.h: 2869: };
+[; ;pic12f1822.h: 2870: } SPBRGbits_t;
+[; ;pic12f1822.h: 2871: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1822.h: 2880: extern volatile unsigned char SPBRGH @ 0x19C;
+"2882
+[; ;pic12f1822.h: 2882: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1822.h: 2885: typedef union {
+[; ;pic12f1822.h: 2886: struct {
+[; ;pic12f1822.h: 2887: unsigned SPBRGH :8;
+[; ;pic12f1822.h: 2888: };
+[; ;pic12f1822.h: 2889: } SPBRGHbits_t;
+[; ;pic12f1822.h: 2890: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1822.h: 2899: extern volatile unsigned char RCSTA @ 0x19D;
+"2901
+[; ;pic12f1822.h: 2901: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1822.h: 2904: typedef union {
+[; ;pic12f1822.h: 2905: struct {
+[; ;pic12f1822.h: 2906: unsigned RX9D :1;
+[; ;pic12f1822.h: 2907: unsigned OERR :1;
+[; ;pic12f1822.h: 2908: unsigned FERR :1;
+[; ;pic12f1822.h: 2909: unsigned ADDEN :1;
+[; ;pic12f1822.h: 2910: unsigned CREN :1;
+[; ;pic12f1822.h: 2911: unsigned SREN :1;
+[; ;pic12f1822.h: 2912: unsigned RX9 :1;
+[; ;pic12f1822.h: 2913: unsigned SPEN :1;
+[; ;pic12f1822.h: 2914: };
+[; ;pic12f1822.h: 2915: } RCSTAbits_t;
+[; ;pic12f1822.h: 2916: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1822.h: 2960: extern volatile unsigned char TXSTA @ 0x19E;
+"2962
+[; ;pic12f1822.h: 2962: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1822.h: 2965: typedef union {
+[; ;pic12f1822.h: 2966: struct {
+[; ;pic12f1822.h: 2967: unsigned TX9D :1;
+[; ;pic12f1822.h: 2968: unsigned TRMT :1;
+[; ;pic12f1822.h: 2969: unsigned BRGH :1;
+[; ;pic12f1822.h: 2970: unsigned SENDB :1;
+[; ;pic12f1822.h: 2971: unsigned SYNC :1;
+[; ;pic12f1822.h: 2972: unsigned TXEN :1;
+[; ;pic12f1822.h: 2973: unsigned TX9 :1;
+[; ;pic12f1822.h: 2974: unsigned CSRC :1;
+[; ;pic12f1822.h: 2975: };
+[; ;pic12f1822.h: 2976: } TXSTAbits_t;
+[; ;pic12f1822.h: 2977: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1822.h: 3021: extern volatile unsigned char BAUDCON @ 0x19F;
+"3023
+[; ;pic12f1822.h: 3023: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1822.h: 3026: typedef union {
+[; ;pic12f1822.h: 3027: struct {
+[; ;pic12f1822.h: 3028: unsigned ABDEN :1;
+[; ;pic12f1822.h: 3029: unsigned WUE :1;
+[; ;pic12f1822.h: 3030: unsigned :1;
+[; ;pic12f1822.h: 3031: unsigned BRG16 :1;
+[; ;pic12f1822.h: 3032: unsigned SCKP :1;
+[; ;pic12f1822.h: 3033: unsigned :1;
+[; ;pic12f1822.h: 3034: unsigned RCIDL :1;
+[; ;pic12f1822.h: 3035: unsigned ABDOVF :1;
+[; ;pic12f1822.h: 3036: };
+[; ;pic12f1822.h: 3037: } BAUDCONbits_t;
+[; ;pic12f1822.h: 3038: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1822.h: 3072: extern volatile unsigned char WPUA @ 0x20C;
+"3074
+[; ;pic12f1822.h: 3074: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1822.h: 3077: typedef union {
+[; ;pic12f1822.h: 3078: struct {
+[; ;pic12f1822.h: 3079: unsigned WPUA0 :1;
+[; ;pic12f1822.h: 3080: unsigned WPUA1 :1;
+[; ;pic12f1822.h: 3081: unsigned WPUA2 :1;
+[; ;pic12f1822.h: 3082: unsigned WPUA3 :1;
+[; ;pic12f1822.h: 3083: unsigned WPUA4 :1;
+[; ;pic12f1822.h: 3084: unsigned WPUA5 :1;
+[; ;pic12f1822.h: 3085: };
+[; ;pic12f1822.h: 3086: struct {
+[; ;pic12f1822.h: 3087: unsigned WPUA :6;
+[; ;pic12f1822.h: 3088: };
+[; ;pic12f1822.h: 3089: } WPUAbits_t;
+[; ;pic12f1822.h: 3090: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1822.h: 3129: extern volatile unsigned char SSP1BUF @ 0x211;
+"3131
+[; ;pic12f1822.h: 3131: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3134: extern volatile unsigned char SSPBUF @ 0x211;
+"3136
+[; ;pic12f1822.h: 3136: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1822.h: 3139: typedef union {
+[; ;pic12f1822.h: 3140: struct {
+[; ;pic12f1822.h: 3141: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3142: };
+[; ;pic12f1822.h: 3143: } SSP1BUFbits_t;
+[; ;pic12f1822.h: 3144: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1822.h: 3152: typedef union {
+[; ;pic12f1822.h: 3153: struct {
+[; ;pic12f1822.h: 3154: unsigned SSPBUF :8;
+[; ;pic12f1822.h: 3155: };
+[; ;pic12f1822.h: 3156: } SSPBUFbits_t;
+[; ;pic12f1822.h: 3157: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1822.h: 3166: extern volatile unsigned char SSP1ADD @ 0x212;
+"3168
+[; ;pic12f1822.h: 3168: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3171: extern volatile unsigned char SSPADD @ 0x212;
+"3173
+[; ;pic12f1822.h: 3173: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1822.h: 3176: typedef union {
+[; ;pic12f1822.h: 3177: struct {
+[; ;pic12f1822.h: 3178: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3179: };
+[; ;pic12f1822.h: 3180: } SSP1ADDbits_t;
+[; ;pic12f1822.h: 3181: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1822.h: 3189: typedef union {
+[; ;pic12f1822.h: 3190: struct {
+[; ;pic12f1822.h: 3191: unsigned SSPADD :8;
+[; ;pic12f1822.h: 3192: };
+[; ;pic12f1822.h: 3193: } SSPADDbits_t;
+[; ;pic12f1822.h: 3194: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1822.h: 3203: extern volatile unsigned char SSP1MSK @ 0x213;
+"3205
+[; ;pic12f1822.h: 3205: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3208: extern volatile unsigned char SSPMSK @ 0x213;
+"3210
+[; ;pic12f1822.h: 3210: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1822.h: 3213: typedef union {
+[; ;pic12f1822.h: 3214: struct {
+[; ;pic12f1822.h: 3215: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3216: };
+[; ;pic12f1822.h: 3217: } SSP1MSKbits_t;
+[; ;pic12f1822.h: 3218: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1822.h: 3226: typedef union {
+[; ;pic12f1822.h: 3227: struct {
+[; ;pic12f1822.h: 3228: unsigned SSPMSK :8;
+[; ;pic12f1822.h: 3229: };
+[; ;pic12f1822.h: 3230: } SSPMSKbits_t;
+[; ;pic12f1822.h: 3231: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1822.h: 3240: extern volatile unsigned char SSP1STAT @ 0x214;
+"3242
+[; ;pic12f1822.h: 3242: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3245: extern volatile unsigned char SSPSTAT @ 0x214;
+"3247
+[; ;pic12f1822.h: 3247: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1822.h: 3250: typedef union {
+[; ;pic12f1822.h: 3251: struct {
+[; ;pic12f1822.h: 3252: unsigned BF :1;
+[; ;pic12f1822.h: 3253: unsigned UA :1;
+[; ;pic12f1822.h: 3254: unsigned R_nW :1;
+[; ;pic12f1822.h: 3255: unsigned S :1;
+[; ;pic12f1822.h: 3256: unsigned P :1;
+[; ;pic12f1822.h: 3257: unsigned D_nA :1;
+[; ;pic12f1822.h: 3258: unsigned CKE :1;
+[; ;pic12f1822.h: 3259: unsigned SMP :1;
+[; ;pic12f1822.h: 3260: };
+[; ;pic12f1822.h: 3261: } SSP1STATbits_t;
+[; ;pic12f1822.h: 3262: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1822.h: 3305: typedef union {
+[; ;pic12f1822.h: 3306: struct {
+[; ;pic12f1822.h: 3307: unsigned BF :1;
+[; ;pic12f1822.h: 3308: unsigned UA :1;
+[; ;pic12f1822.h: 3309: unsigned R_nW :1;
+[; ;pic12f1822.h: 3310: unsigned S :1;
+[; ;pic12f1822.h: 3311: unsigned P :1;
+[; ;pic12f1822.h: 3312: unsigned D_nA :1;
+[; ;pic12f1822.h: 3313: unsigned CKE :1;
+[; ;pic12f1822.h: 3314: unsigned SMP :1;
+[; ;pic12f1822.h: 3315: };
+[; ;pic12f1822.h: 3316: } SSPSTATbits_t;
+[; ;pic12f1822.h: 3317: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1822.h: 3361: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3363
+[; ;pic12f1822.h: 3363: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3366: extern volatile unsigned char SSPCON1 @ 0x215;
+"3368
+[; ;pic12f1822.h: 3368: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1822.h: 3370: extern volatile unsigned char SSPCON @ 0x215;
+"3372
+[; ;pic12f1822.h: 3372: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1822.h: 3375: typedef union {
+[; ;pic12f1822.h: 3376: struct {
+[; ;pic12f1822.h: 3377: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3378: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3379: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3380: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3381: unsigned CKP :1;
+[; ;pic12f1822.h: 3382: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3383: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3384: unsigned WCOL :1;
+[; ;pic12f1822.h: 3385: };
+[; ;pic12f1822.h: 3386: struct {
+[; ;pic12f1822.h: 3387: unsigned SSPM :4;
+[; ;pic12f1822.h: 3388: };
+[; ;pic12f1822.h: 3389: } SSP1CON1bits_t;
+[; ;pic12f1822.h: 3390: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1822.h: 3438: typedef union {
+[; ;pic12f1822.h: 3439: struct {
+[; ;pic12f1822.h: 3440: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3441: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3442: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3443: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3444: unsigned CKP :1;
+[; ;pic12f1822.h: 3445: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3446: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3447: unsigned WCOL :1;
+[; ;pic12f1822.h: 3448: };
+[; ;pic12f1822.h: 3449: struct {
+[; ;pic12f1822.h: 3450: unsigned SSPM :4;
+[; ;pic12f1822.h: 3451: };
+[; ;pic12f1822.h: 3452: } SSPCON1bits_t;
+[; ;pic12f1822.h: 3453: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1822.h: 3500: typedef union {
+[; ;pic12f1822.h: 3501: struct {
+[; ;pic12f1822.h: 3502: unsigned SSPM0 :1;
+[; ;pic12f1822.h: 3503: unsigned SSPM1 :1;
+[; ;pic12f1822.h: 3504: unsigned SSPM2 :1;
+[; ;pic12f1822.h: 3505: unsigned SSPM3 :1;
+[; ;pic12f1822.h: 3506: unsigned CKP :1;
+[; ;pic12f1822.h: 3507: unsigned SSPEN :1;
+[; ;pic12f1822.h: 3508: unsigned SSPOV :1;
+[; ;pic12f1822.h: 3509: unsigned WCOL :1;
+[; ;pic12f1822.h: 3510: };
+[; ;pic12f1822.h: 3511: struct {
+[; ;pic12f1822.h: 3512: unsigned SSPM :4;
+[; ;pic12f1822.h: 3513: };
+[; ;pic12f1822.h: 3514: } SSPCONbits_t;
+[; ;pic12f1822.h: 3515: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1822.h: 3564: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3566
+[; ;pic12f1822.h: 3566: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3569: extern volatile unsigned char SSPCON2 @ 0x216;
+"3571
+[; ;pic12f1822.h: 3571: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1822.h: 3574: typedef union {
+[; ;pic12f1822.h: 3575: struct {
+[; ;pic12f1822.h: 3576: unsigned SEN :1;
+[; ;pic12f1822.h: 3577: unsigned RSEN :1;
+[; ;pic12f1822.h: 3578: unsigned PEN :1;
+[; ;pic12f1822.h: 3579: unsigned RCEN :1;
+[; ;pic12f1822.h: 3580: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3581: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3582: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3583: unsigned GCEN :1;
+[; ;pic12f1822.h: 3584: };
+[; ;pic12f1822.h: 3585: } SSP1CON2bits_t;
+[; ;pic12f1822.h: 3586: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1822.h: 3629: typedef union {
+[; ;pic12f1822.h: 3630: struct {
+[; ;pic12f1822.h: 3631: unsigned SEN :1;
+[; ;pic12f1822.h: 3632: unsigned RSEN :1;
+[; ;pic12f1822.h: 3633: unsigned PEN :1;
+[; ;pic12f1822.h: 3634: unsigned RCEN :1;
+[; ;pic12f1822.h: 3635: unsigned ACKEN :1;
+[; ;pic12f1822.h: 3636: unsigned ACKDT :1;
+[; ;pic12f1822.h: 3637: unsigned ACKSTAT :1;
+[; ;pic12f1822.h: 3638: unsigned GCEN :1;
+[; ;pic12f1822.h: 3639: };
+[; ;pic12f1822.h: 3640: } SSPCON2bits_t;
+[; ;pic12f1822.h: 3641: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1822.h: 3685: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3687
+[; ;pic12f1822.h: 3687: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3690: extern volatile unsigned char SSPCON3 @ 0x217;
+"3692
+[; ;pic12f1822.h: 3692: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1822.h: 3695: typedef union {
+[; ;pic12f1822.h: 3696: struct {
+[; ;pic12f1822.h: 3697: unsigned DHEN :1;
+[; ;pic12f1822.h: 3698: unsigned AHEN :1;
+[; ;pic12f1822.h: 3699: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3700: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3701: unsigned BOEN :1;
+[; ;pic12f1822.h: 3702: unsigned SCIE :1;
+[; ;pic12f1822.h: 3703: unsigned PCIE :1;
+[; ;pic12f1822.h: 3704: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3705: };
+[; ;pic12f1822.h: 3706: } SSP1CON3bits_t;
+[; ;pic12f1822.h: 3707: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1822.h: 3750: typedef union {
+[; ;pic12f1822.h: 3751: struct {
+[; ;pic12f1822.h: 3752: unsigned DHEN :1;
+[; ;pic12f1822.h: 3753: unsigned AHEN :1;
+[; ;pic12f1822.h: 3754: unsigned SBCDE :1;
+[; ;pic12f1822.h: 3755: unsigned SDAHT :1;
+[; ;pic12f1822.h: 3756: unsigned BOEN :1;
+[; ;pic12f1822.h: 3757: unsigned SCIE :1;
+[; ;pic12f1822.h: 3758: unsigned PCIE :1;
+[; ;pic12f1822.h: 3759: unsigned ACKTIM :1;
+[; ;pic12f1822.h: 3760: };
+[; ;pic12f1822.h: 3761: } SSPCON3bits_t;
+[; ;pic12f1822.h: 3762: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1822.h: 3806: extern volatile unsigned char CCPR1L @ 0x291;
+"3808
+[; ;pic12f1822.h: 3808: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1822.h: 3811: typedef union {
+[; ;pic12f1822.h: 3812: struct {
+[; ;pic12f1822.h: 3813: unsigned CCPR1L :8;
+[; ;pic12f1822.h: 3814: };
+[; ;pic12f1822.h: 3815: } CCPR1Lbits_t;
+[; ;pic12f1822.h: 3816: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1822.h: 3825: extern volatile unsigned char CCPR1H @ 0x292;
+"3827
+[; ;pic12f1822.h: 3827: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1822.h: 3830: typedef union {
+[; ;pic12f1822.h: 3831: struct {
+[; ;pic12f1822.h: 3832: unsigned CCPR1H :8;
+[; ;pic12f1822.h: 3833: };
+[; ;pic12f1822.h: 3834: } CCPR1Hbits_t;
+[; ;pic12f1822.h: 3835: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1822.h: 3844: extern volatile unsigned char CCP1CON @ 0x293;
+"3846
+[; ;pic12f1822.h: 3846: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1822.h: 3849: typedef union {
+[; ;pic12f1822.h: 3850: struct {
+[; ;pic12f1822.h: 3851: unsigned CCP1M0 :1;
+[; ;pic12f1822.h: 3852: unsigned CCP1M1 :1;
+[; ;pic12f1822.h: 3853: unsigned CCP1M2 :1;
+[; ;pic12f1822.h: 3854: unsigned CCP1M3 :1;
+[; ;pic12f1822.h: 3855: unsigned DC1B0 :1;
+[; ;pic12f1822.h: 3856: unsigned DC1B1 :1;
+[; ;pic12f1822.h: 3857: unsigned P1M0 :1;
+[; ;pic12f1822.h: 3858: unsigned P1M1 :1;
+[; ;pic12f1822.h: 3859: };
+[; ;pic12f1822.h: 3860: struct {
+[; ;pic12f1822.h: 3861: unsigned CCP1M :4;
+[; ;pic12f1822.h: 3862: unsigned DC1B :2;
+[; ;pic12f1822.h: 3863: unsigned P1M :2;
+[; ;pic12f1822.h: 3864: };
+[; ;pic12f1822.h: 3865: } CCP1CONbits_t;
+[; ;pic12f1822.h: 3866: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1822.h: 3925: extern volatile unsigned char PWM1CON @ 0x294;
+"3927
+[; ;pic12f1822.h: 3927: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1822.h: 3930: typedef union {
+[; ;pic12f1822.h: 3931: struct {
+[; ;pic12f1822.h: 3932: unsigned P1DC0 :1;
+[; ;pic12f1822.h: 3933: unsigned P1DC1 :1;
+[; ;pic12f1822.h: 3934: unsigned P1DC2 :1;
+[; ;pic12f1822.h: 3935: unsigned P1DC3 :1;
+[; ;pic12f1822.h: 3936: unsigned P1DC4 :1;
+[; ;pic12f1822.h: 3937: unsigned P1DC5 :1;
+[; ;pic12f1822.h: 3938: unsigned P1DC6 :1;
+[; ;pic12f1822.h: 3939: unsigned P1RSEN :1;
+[; ;pic12f1822.h: 3940: };
+[; ;pic12f1822.h: 3941: struct {
+[; ;pic12f1822.h: 3942: unsigned P1DC :7;
+[; ;pic12f1822.h: 3943: };
+[; ;pic12f1822.h: 3944: } PWM1CONbits_t;
+[; ;pic12f1822.h: 3945: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1822.h: 3994: extern volatile unsigned char CCP1AS @ 0x295;
+"3996
+[; ;pic12f1822.h: 3996: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 3999: extern volatile unsigned char ECCP1AS @ 0x295;
+"4001
+[; ;pic12f1822.h: 4001: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1822.h: 4004: typedef union {
+[; ;pic12f1822.h: 4005: struct {
+[; ;pic12f1822.h: 4006: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4007: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4008: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4009: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4010: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4011: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4012: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4013: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4014: };
+[; ;pic12f1822.h: 4015: struct {
+[; ;pic12f1822.h: 4016: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4017: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4018: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4019: };
+[; ;pic12f1822.h: 4020: } CCP1ASbits_t;
+[; ;pic12f1822.h: 4021: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4079: typedef union {
+[; ;pic12f1822.h: 4080: struct {
+[; ;pic12f1822.h: 4081: unsigned PSS1BD0 :1;
+[; ;pic12f1822.h: 4082: unsigned PSS1BD1 :1;
+[; ;pic12f1822.h: 4083: unsigned PSS1AC0 :1;
+[; ;pic12f1822.h: 4084: unsigned PSS1AC1 :1;
+[; ;pic12f1822.h: 4085: unsigned CCP1AS0 :1;
+[; ;pic12f1822.h: 4086: unsigned CCP1AS1 :1;
+[; ;pic12f1822.h: 4087: unsigned CCP1AS2 :1;
+[; ;pic12f1822.h: 4088: unsigned CCP1ASE :1;
+[; ;pic12f1822.h: 4089: };
+[; ;pic12f1822.h: 4090: struct {
+[; ;pic12f1822.h: 4091: unsigned PSS1BD :2;
+[; ;pic12f1822.h: 4092: unsigned PSS1AC :2;
+[; ;pic12f1822.h: 4093: unsigned CCP1AS :3;
+[; ;pic12f1822.h: 4094: };
+[; ;pic12f1822.h: 4095: } ECCP1ASbits_t;
+[; ;pic12f1822.h: 4096: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1822.h: 4155: extern volatile unsigned char PSTR1CON @ 0x296;
+"4157
+[; ;pic12f1822.h: 4157: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1822.h: 4160: typedef union {
+[; ;pic12f1822.h: 4161: struct {
+[; ;pic12f1822.h: 4162: unsigned STR1A :1;
+[; ;pic12f1822.h: 4163: unsigned STR1B :1;
+[; ;pic12f1822.h: 4164: unsigned STR1C :1;
+[; ;pic12f1822.h: 4165: unsigned STR1D :1;
+[; ;pic12f1822.h: 4166: unsigned STR1SYNC :1;
+[; ;pic12f1822.h: 4167: };
+[; ;pic12f1822.h: 4168: } PSTR1CONbits_t;
+[; ;pic12f1822.h: 4169: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1822.h: 4198: extern volatile unsigned char IOCAP @ 0x391;
+"4200
+[; ;pic12f1822.h: 4200: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1822.h: 4203: typedef union {
+[; ;pic12f1822.h: 4204: struct {
+[; ;pic12f1822.h: 4205: unsigned IOCAP0 :1;
+[; ;pic12f1822.h: 4206: unsigned IOCAP1 :1;
+[; ;pic12f1822.h: 4207: unsigned IOCAP2 :1;
+[; ;pic12f1822.h: 4208: unsigned IOCAP3 :1;
+[; ;pic12f1822.h: 4209: unsigned IOCAP4 :1;
+[; ;pic12f1822.h: 4210: unsigned IOCAP5 :1;
+[; ;pic12f1822.h: 4211: };
+[; ;pic12f1822.h: 4212: struct {
+[; ;pic12f1822.h: 4213: unsigned IOCAP :6;
+[; ;pic12f1822.h: 4214: };
+[; ;pic12f1822.h: 4215: } IOCAPbits_t;
+[; ;pic12f1822.h: 4216: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1822.h: 4255: extern volatile unsigned char IOCAN @ 0x392;
+"4257
+[; ;pic12f1822.h: 4257: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1822.h: 4260: typedef union {
+[; ;pic12f1822.h: 4261: struct {
+[; ;pic12f1822.h: 4262: unsigned IOCAN0 :1;
+[; ;pic12f1822.h: 4263: unsigned IOCAN1 :1;
+[; ;pic12f1822.h: 4264: unsigned IOCAN2 :1;
+[; ;pic12f1822.h: 4265: unsigned IOCAN3 :1;
+[; ;pic12f1822.h: 4266: unsigned IOCAN4 :1;
+[; ;pic12f1822.h: 4267: unsigned IOCAN5 :1;
+[; ;pic12f1822.h: 4268: };
+[; ;pic12f1822.h: 4269: struct {
+[; ;pic12f1822.h: 4270: unsigned IOCAN :6;
+[; ;pic12f1822.h: 4271: };
+[; ;pic12f1822.h: 4272: } IOCANbits_t;
+[; ;pic12f1822.h: 4273: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1822.h: 4312: extern volatile unsigned char IOCAF @ 0x393;
+"4314
+[; ;pic12f1822.h: 4314: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1822.h: 4317: typedef union {
+[; ;pic12f1822.h: 4318: struct {
+[; ;pic12f1822.h: 4319: unsigned IOCAF0 :1;
+[; ;pic12f1822.h: 4320: unsigned IOCAF1 :1;
+[; ;pic12f1822.h: 4321: unsigned IOCAF2 :1;
+[; ;pic12f1822.h: 4322: unsigned IOCAF3 :1;
+[; ;pic12f1822.h: 4323: unsigned IOCAF4 :1;
+[; ;pic12f1822.h: 4324: unsigned IOCAF5 :1;
+[; ;pic12f1822.h: 4325: };
+[; ;pic12f1822.h: 4326: struct {
+[; ;pic12f1822.h: 4327: unsigned IOCAF :6;
+[; ;pic12f1822.h: 4328: };
+[; ;pic12f1822.h: 4329: } IOCAFbits_t;
+[; ;pic12f1822.h: 4330: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1822.h: 4369: extern volatile unsigned char CLKRCON @ 0x39A;
+"4371
+[; ;pic12f1822.h: 4371: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1822.h: 4374: typedef union {
+[; ;pic12f1822.h: 4375: struct {
+[; ;pic12f1822.h: 4376: unsigned CLKRDIV0 :1;
+[; ;pic12f1822.h: 4377: unsigned CLKRDIV1 :1;
+[; ;pic12f1822.h: 4378: unsigned CLKRDIV2 :1;
+[; ;pic12f1822.h: 4379: unsigned CLKRDC0 :1;
+[; ;pic12f1822.h: 4380: unsigned CLKRDC1 :1;
+[; ;pic12f1822.h: 4381: unsigned CLKRSLR :1;
+[; ;pic12f1822.h: 4382: unsigned CLKROE :1;
+[; ;pic12f1822.h: 4383: unsigned CLKREN :1;
+[; ;pic12f1822.h: 4384: };
+[; ;pic12f1822.h: 4385: struct {
+[; ;pic12f1822.h: 4386: unsigned CLKRDIV :3;
+[; ;pic12f1822.h: 4387: unsigned CLKRDC :2;
+[; ;pic12f1822.h: 4388: };
+[; ;pic12f1822.h: 4389: } CLKRCONbits_t;
+[; ;pic12f1822.h: 4390: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1822.h: 4444: extern volatile unsigned char MDCON @ 0x39C;
+"4446
+[; ;pic12f1822.h: 4446: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1822.h: 4449: typedef union {
+[; ;pic12f1822.h: 4450: struct {
+[; ;pic12f1822.h: 4451: unsigned MDBIT :1;
+[; ;pic12f1822.h: 4452: unsigned :2;
+[; ;pic12f1822.h: 4453: unsigned MDOUT :1;
+[; ;pic12f1822.h: 4454: unsigned MDOPOL :1;
+[; ;pic12f1822.h: 4455: unsigned MDSLR :1;
+[; ;pic12f1822.h: 4456: unsigned MDOE :1;
+[; ;pic12f1822.h: 4457: unsigned MDEN :1;
+[; ;pic12f1822.h: 4458: };
+[; ;pic12f1822.h: 4459: } MDCONbits_t;
+[; ;pic12f1822.h: 4460: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1822.h: 4494: extern volatile unsigned char MDSRC @ 0x39D;
+"4496
+[; ;pic12f1822.h: 4496: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1822.h: 4499: typedef union {
+[; ;pic12f1822.h: 4500: struct {
+[; ;pic12f1822.h: 4501: unsigned MDMS0 :1;
+[; ;pic12f1822.h: 4502: unsigned MDMS1 :1;
+[; ;pic12f1822.h: 4503: unsigned MDMS2 :1;
+[; ;pic12f1822.h: 4504: unsigned MDMS3 :1;
+[; ;pic12f1822.h: 4505: unsigned :3;
+[; ;pic12f1822.h: 4506: unsigned MDMSODIS :1;
+[; ;pic12f1822.h: 4507: };
+[; ;pic12f1822.h: 4508: struct {
+[; ;pic12f1822.h: 4509: unsigned MDMS :4;
+[; ;pic12f1822.h: 4510: };
+[; ;pic12f1822.h: 4511: } MDSRCbits_t;
+[; ;pic12f1822.h: 4512: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1822.h: 4546: extern volatile unsigned char MDCARL @ 0x39E;
+"4548
+[; ;pic12f1822.h: 4548: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1822.h: 4551: typedef union {
+[; ;pic12f1822.h: 4552: struct {
+[; ;pic12f1822.h: 4553: unsigned MDCL0 :1;
+[; ;pic12f1822.h: 4554: unsigned MDCL1 :1;
+[; ;pic12f1822.h: 4555: unsigned MDCL2 :1;
+[; ;pic12f1822.h: 4556: unsigned MDCL3 :1;
+[; ;pic12f1822.h: 4557: unsigned :1;
+[; ;pic12f1822.h: 4558: unsigned MDCLSYNC :1;
+[; ;pic12f1822.h: 4559: unsigned MDCLPOL :1;
+[; ;pic12f1822.h: 4560: unsigned MDCLODIS :1;
+[; ;pic12f1822.h: 4561: };
+[; ;pic12f1822.h: 4562: struct {
+[; ;pic12f1822.h: 4563: unsigned MDCL :4;
+[; ;pic12f1822.h: 4564: };
+[; ;pic12f1822.h: 4565: } MDCARLbits_t;
+[; ;pic12f1822.h: 4566: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1822.h: 4610: extern volatile unsigned char MDCARH @ 0x39F;
+"4612
+[; ;pic12f1822.h: 4612: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1822.h: 4615: typedef union {
+[; ;pic12f1822.h: 4616: struct {
+[; ;pic12f1822.h: 4617: unsigned MDCH0 :1;
+[; ;pic12f1822.h: 4618: unsigned MDCH1 :1;
+[; ;pic12f1822.h: 4619: unsigned MDCH2 :1;
+[; ;pic12f1822.h: 4620: unsigned MDCH3 :1;
+[; ;pic12f1822.h: 4621: unsigned :1;
+[; ;pic12f1822.h: 4622: unsigned MDCHSYNC :1;
+[; ;pic12f1822.h: 4623: unsigned MDCHPOL :1;
+[; ;pic12f1822.h: 4624: unsigned MDCHODIS :1;
+[; ;pic12f1822.h: 4625: };
+[; ;pic12f1822.h: 4626: struct {
+[; ;pic12f1822.h: 4627: unsigned MDCH :4;
+[; ;pic12f1822.h: 4628: };
+[; ;pic12f1822.h: 4629: } MDCARHbits_t;
+[; ;pic12f1822.h: 4630: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1822.h: 4674: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4676
+[; ;pic12f1822.h: 4676: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1822.h: 4679: typedef union {
+[; ;pic12f1822.h: 4680: struct {
+[; ;pic12f1822.h: 4681: unsigned C_SHAD :1;
+[; ;pic12f1822.h: 4682: unsigned DC_SHAD :1;
+[; ;pic12f1822.h: 4683: unsigned Z_SHAD :1;
+[; ;pic12f1822.h: 4684: };
+[; ;pic12f1822.h: 4685: } STATUS_SHADbits_t;
+[; ;pic12f1822.h: 4686: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1822.h: 4705: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4707
+[; ;pic12f1822.h: 4707: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1822.h: 4710: typedef union {
+[; ;pic12f1822.h: 4711: struct {
+[; ;pic12f1822.h: 4712: unsigned WREG_SHAD :8;
+[; ;pic12f1822.h: 4713: };
+[; ;pic12f1822.h: 4714: } WREG_SHADbits_t;
+[; ;pic12f1822.h: 4715: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1822.h: 4724: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4726
+[; ;pic12f1822.h: 4726: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1822.h: 4729: typedef union {
+[; ;pic12f1822.h: 4730: struct {
+[; ;pic12f1822.h: 4731: unsigned BSR_SHAD :5;
+[; ;pic12f1822.h: 4732: };
+[; ;pic12f1822.h: 4733: } BSR_SHADbits_t;
+[; ;pic12f1822.h: 4734: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1822.h: 4743: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4745
+[; ;pic12f1822.h: 4745: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1822.h: 4748: typedef union {
+[; ;pic12f1822.h: 4749: struct {
+[; ;pic12f1822.h: 4750: unsigned PCLATH_SHAD :7;
+[; ;pic12f1822.h: 4751: };
+[; ;pic12f1822.h: 4752: } PCLATH_SHADbits_t;
+[; ;pic12f1822.h: 4753: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1822.h: 4762: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4764
+[; ;pic12f1822.h: 4764: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1822.h: 4767: typedef union {
+[; ;pic12f1822.h: 4768: struct {
+[; ;pic12f1822.h: 4769: unsigned FSR0L_SHAD :8;
+[; ;pic12f1822.h: 4770: };
+[; ;pic12f1822.h: 4771: } FSR0L_SHADbits_t;
+[; ;pic12f1822.h: 4772: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1822.h: 4781: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4783
+[; ;pic12f1822.h: 4783: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1822.h: 4786: typedef union {
+[; ;pic12f1822.h: 4787: struct {
+[; ;pic12f1822.h: 4788: unsigned FSR0H_SHAD :8;
+[; ;pic12f1822.h: 4789: };
+[; ;pic12f1822.h: 4790: } FSR0H_SHADbits_t;
+[; ;pic12f1822.h: 4791: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1822.h: 4800: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4802
+[; ;pic12f1822.h: 4802: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1822.h: 4805: typedef union {
+[; ;pic12f1822.h: 4806: struct {
+[; ;pic12f1822.h: 4807: unsigned FSR1L_SHAD :8;
+[; ;pic12f1822.h: 4808: };
+[; ;pic12f1822.h: 4809: } FSR1L_SHADbits_t;
+[; ;pic12f1822.h: 4810: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1822.h: 4819: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4821
+[; ;pic12f1822.h: 4821: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1822.h: 4824: typedef union {
+[; ;pic12f1822.h: 4825: struct {
+[; ;pic12f1822.h: 4826: unsigned FSR1H_SHAD :8;
+[; ;pic12f1822.h: 4827: };
+[; ;pic12f1822.h: 4828: } FSR1H_SHADbits_t;
+[; ;pic12f1822.h: 4829: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1822.h: 4838: extern volatile unsigned char STKPTR @ 0xFED;
+"4840
+[; ;pic12f1822.h: 4840: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1822.h: 4843: typedef union {
+[; ;pic12f1822.h: 4844: struct {
+[; ;pic12f1822.h: 4845: unsigned STKPTR :5;
+[; ;pic12f1822.h: 4846: };
+[; ;pic12f1822.h: 4847: } STKPTRbits_t;
+[; ;pic12f1822.h: 4848: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1822.h: 4857: extern volatile unsigned char TOSL @ 0xFEE;
+"4859
+[; ;pic12f1822.h: 4859: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1822.h: 4862: typedef union {
+[; ;pic12f1822.h: 4863: struct {
+[; ;pic12f1822.h: 4864: unsigned TOSL :8;
+[; ;pic12f1822.h: 4865: };
+[; ;pic12f1822.h: 4866: } TOSLbits_t;
+[; ;pic12f1822.h: 4867: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1822.h: 4876: extern volatile unsigned char TOSH @ 0xFEF;
+"4878
+[; ;pic12f1822.h: 4878: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1822.h: 4881: typedef union {
+[; ;pic12f1822.h: 4882: struct {
+[; ;pic12f1822.h: 4883: unsigned TOSH :7;
+[; ;pic12f1822.h: 4884: };
+[; ;pic12f1822.h: 4885: } TOSHbits_t;
+[; ;pic12f1822.h: 4886: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1822.h: 4901: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1822.h: 4903: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1822.h: 4905: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1822.h: 4907: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1822.h: 4909: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1822.h: 4911: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1822.h: 4913: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1822.h: 4915: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1822.h: 4917: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1822.h: 4919: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1822.h: 4921: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1822.h: 4923: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1822.h: 4925: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1822.h: 4927: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 4929: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1822.h: 4931: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1822.h: 4933: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1822.h: 4935: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1822.h: 4937: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1822.h: 4939: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1822.h: 4941: extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4943: extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4945: extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 4947: extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4949: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1822.h: 4951: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1822.h: 4953: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1822.h: 4955: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1822.h: 4957: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1822.h: 4959: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1822.h: 4961: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1822.h: 4963: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1822.h: 4965: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1822.h: 4967: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1822.h: 4969: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1822.h: 4971: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1822.h: 4973: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1822.h: 4975: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1822.h: 4977: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1822.h: 4979: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1822.h: 4981: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1822.h: 4983: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1822.h: 4985: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1822.h: 4987: extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 4989: extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 4991: extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 4993: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1822.h: 4995: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1822.h: 4997: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1822.h: 4999: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1822.h: 5001: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1822.h: 5003: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1822.h: 5005: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1822.h: 5007: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1822.h: 5009: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1822.h: 5011: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1822.h: 5013: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1822.h: 5015: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1822.h: 5017: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1822.h: 5019: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1822.h: 5021: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1822.h: 5023: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1822.h: 5025: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1822.h: 5027: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1822.h: 5029: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1822.h: 5031: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1822.h: 5033: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1822.h: 5035: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1822.h: 5037: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1822.h: 5039: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1822.h: 5041: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1822.h: 5043: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1822.h: 5045: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1822.h: 5047: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1822.h: 5049: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1822.h: 5051: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1822.h: 5053: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1822.h: 5055: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1822.h: 5057: extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5059: extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5061: extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5063: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1822.h: 5065: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1822.h: 5067: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1822.h: 5069: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1822.h: 5071: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1822.h: 5073: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1822.h: 5075: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1822.h: 5077: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1822.h: 5079: extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5081: extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5083: extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5085: extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5087: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1822.h: 5089: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1822.h: 5091: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1822.h: 5093: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1822.h: 5095: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1822.h: 5097: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1822.h: 5099: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1822.h: 5101: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1822.h: 5103: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1822.h: 5105: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1822.h: 5107: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1822.h: 5109: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1822.h: 5111: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1822.h: 5113: extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5115: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1822.h: 5117: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1822.h: 5119: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1822.h: 5121: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1822.h: 5123: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1822.h: 5125: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1822.h: 5127: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1822.h: 5129: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1822.h: 5131: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1822.h: 5133: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1822.h: 5135: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1822.h: 5137: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1822.h: 5139: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1822.h: 5141: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1822.h: 5143: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1822.h: 5145: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1822.h: 5147: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1822.h: 5149: extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5151: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1822.h: 5153: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1822.h: 5155: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1822.h: 5157: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1822.h: 5159: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1822.h: 5161: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5163: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5165: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1822.h: 5167: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1822.h: 5169: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1822.h: 5171: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1822.h: 5173: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1822.h: 5175: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1822.h: 5177: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1822.h: 5179: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1822.h: 5181: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1822.h: 5183: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1822.h: 5185: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1822.h: 5187: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1822.h: 5189: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1822.h: 5191: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1822.h: 5193: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1822.h: 5195: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1822.h: 5197: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1822.h: 5199: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1822.h: 5201: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1822.h: 5203: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1822.h: 5205: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1822.h: 5207: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1822.h: 5209: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1822.h: 5211: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1822.h: 5213: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1822.h: 5215: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1822.h: 5217: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1822.h: 5219: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1822.h: 5221: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1822.h: 5223: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1822.h: 5225: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1822.h: 5227: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1822.h: 5229: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1822.h: 5231: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1822.h: 5233: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1822.h: 5235: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1822.h: 5237: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1822.h: 5239: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1822.h: 5241: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1822.h: 5243: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1822.h: 5245: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1822.h: 5247: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1822.h: 5249: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1822.h: 5251: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1822.h: 5253: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1822.h: 5255: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1822.h: 5257: extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5259: extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5261: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1822.h: 5263: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1822.h: 5265: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1822.h: 5267: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1822.h: 5269: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1822.h: 5271: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1822.h: 5273: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1822.h: 5275: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1822.h: 5277: extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5279: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1822.h: 5281: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1822.h: 5283: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1822.h: 5285: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1822.h: 5287: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1822.h: 5289: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1822.h: 5291: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1822.h: 5293: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1822.h: 5295: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1822.h: 5297: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1822.h: 5299: extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5301: extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5303: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1822.h: 5305: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1822.h: 5307: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1822.h: 5309: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1822.h: 5311: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1822.h: 5313: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1822.h: 5315: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1822.h: 5317: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1822.h: 5319: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1822.h: 5321: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1822.h: 5323: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1822.h: 5325: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1822.h: 5327: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1822.h: 5329: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1822.h: 5331: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1822.h: 5333: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1822.h: 5335: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1822.h: 5337: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1822.h: 5339: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1822.h: 5341: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1822.h: 5343: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1822.h: 5345: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1822.h: 5347: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1822.h: 5349: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1822.h: 5351: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1822.h: 5353: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1822.h: 5355: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1822.h: 5357: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5359: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5361: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5363: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5365: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5367: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1822.h: 5369: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1822.h: 5371: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1822.h: 5373: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1822.h: 5375: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1822.h: 5377: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1822.h: 5379: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1822.h: 5381: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1822.h: 5383: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1822.h: 5385: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1822.h: 5387: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1822.h: 5389: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1822.h: 5391: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1822.h: 5393: extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5395: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1822.h: 5397: extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5399: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1822.h: 5401: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1822.h: 5403: extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5405: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1822.h: 5407: extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5409: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5411: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1822.h: 5413: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1822.h: 5415: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1822.h: 5417: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1822.h: 5419: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1822.h: 5421: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1822.h: 5423: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1822.h: 5425: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1822.h: 5427: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1822.h: 5429: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1822.h: 5431: extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1822.h: 5433: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1822.h: 5435: extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5437: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1822.h: 5439: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1822.h: 5441: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1822.h: 5443: extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5445: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1822.h: 5447: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1822.h: 5449: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1822.h: 5451: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1822.h: 5453: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1822.h: 5455: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1822.h: 5457: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1822.h: 5459: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5461: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1822.h: 5463: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1822.h: 5465: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1822.h: 5467: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1822.h: 5469: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1822.h: 5471: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1822.h: 5473: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1822.h: 5475: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1822.h: 5477: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1822.h: 5479: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1822.h: 5481: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1822.h: 5483: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1822.h: 5485: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1822.h: 5487: extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+[; ;pic12f1822.h: 5489: extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+[; ;pic12f1822.h: 5491: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1822.h: 5493: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1822.h: 5495: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1822.h: 5497: extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1822.h: 5499: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5501: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5503: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5505: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5507: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1822.h: 5509: extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5511: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1822.h: 5513: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1822.h: 5515: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5517: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1822.h: 5519: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1822.h: 5521: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1822.h: 5523: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1822.h: 5525: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1822.h: 5527: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1822.h: 5529: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1822.h: 5531: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1822.h: 5533: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1822.h: 5535: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1822.h: 5537: extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1822.h: 5539: extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1822.h: 5541: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1822.h: 5543: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1822.h: 5545: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1822.h: 5547: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1822.h: 5549: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1822.h: 5551: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1822.h: 5553: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1822.h: 5555: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1822.h: 5557: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1822.h: 5559: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1822.h: 5561: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1822.h: 5563: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1822.h: 5565: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1822.h: 5567: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1822.h: 5569: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1822.h: 5571: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1822.h: 5573: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1822.h: 5575: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1822.h: 5577: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1822.h: 5579: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1822.h: 5581: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1822.h: 5583: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1822.h: 5585: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1822.h: 5587: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1822.h: 5589: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1822.h: 5591: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1822.h: 5593: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1822.h: 5595: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1822.h: 5597: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1822.h: 5599: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1822.h: 5601: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1822.h: 5603: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1822.h: 5605: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1822.h: 5607: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1822.h: 5609: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1822.h: 5611: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1822.h: 5613: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1822.h: 5615: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1822.h: 5617: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1822.h: 5619: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1822.h: 5621: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1822.h: 5623: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1822.h: 5625: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1822.h: 5627: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1822.h: 5629: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1822.h: 5631: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1822.h: 5633: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1822.h: 5635: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1822.h: 5637: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1822.h: 5639: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1822.h: 5641: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1822.h: 5643: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1822.h: 5645: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1822.h: 5647: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1822.h: 5649: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1822.h: 5651: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1822.h: 5653: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1822.h: 5655: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1822.h: 5657: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1822.h: 5659: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1822.h: 5661: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1822.h: 5663: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1822.h: 5665: extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1822.h: 5667: extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1822.h: 5669: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1822.h: 5671: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1822.h: 5673: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1822.h: 5675: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1822.h: 5677: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1822.h: 5679: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1822.h: 5681: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;system.h: 31: void ConfigureOscillator(void);
+[; ;user.h: 13: void InitApp(void);
+[; ;user.h: 14: bool msg_empty(void);
+[; ;user.h: 15: void msg_write(const char *msg);
+[; ;user.h: 16: void msg_writebyte(const char msg);
+[; ;user.h: 17: void msg_sendnext(void);
+[; ;user.h: 18: void tohex(char val[3], char i);
+[; ;user.h: 19: void msg_recvnext(void);
+[; ;user.h: 20: bool msg_recvready(void);
+[; ;user.h: 21: char msg_recv(void);
+[; ;user.h: 22: void putch(char);
+[; ;user.h: 24: void int_disable(void);
+[; ;user.h: 25: void int_enable(void);
+"24 user.c
+[v _InitApp `(v ~T0 @X0 1 ef ]
+{
+[; ;user.c: 23: void InitApp(void)
+[; ;user.c: 24: {
+[e :U _InitApp ]
+[f ]
+[; ;user.c: 26: WDTCONbits.WDTPS = 0b01100;
+"26
+[e = . . _WDTCONbits 1 1 -> -> 12 `i `uc ]
+[; ;user.c: 27: WDTCONbits.SWDTEN = 1;
+"27
+[e = . . _WDTCONbits 0 0 -> -> 1 `i `uc ]
+[; ;user.c: 30: APFCONbits.RXDTSEL = 0;
+"30
+[e = . . _APFCONbits 0 7 -> -> 0 `i `uc ]
+[; ;user.c: 31: APFCONbits.TXCKSEL = 0;
+"31
+[e = . . _APFCONbits 0 2 -> -> 0 `i `uc ]
+[; ;user.c: 32: TRISAbits.TRISA1 = 1;
+"32
+[e = . . _TRISAbits 0 1 -> -> 1 `i `uc ]
+[; ;user.c: 33: TRISAbits.TRISA0 = 0;
+"33
+[e = . . _TRISAbits 0 0 -> -> 0 `i `uc ]
+[; ;user.c: 35: ANSELA = 0;
+"35
+[e = _ANSELA -> -> 0 `i `uc ]
+[; ;user.c: 39: WPUA = 0;
+"39
+[e = _WPUA -> -> 0 `i `uc ]
+[; ;user.c: 41: OPTION_REGbits.nWPUEN = 1;
+"41
+[e = . . _OPTION_REGbits 0 7 -> -> 1 `i `uc ]
+[; ;user.c: 44: TXSTAbits.TXEN = 1;
+"44
+[e = . . _TXSTAbits 0 5 -> -> 1 `i `uc ]
+[; ;user.c: 45: TXSTAbits.SYNC = 0;
+"45
+[e = . . _TXSTAbits 0 4 -> -> 0 `i `uc ]
+[; ;user.c: 46: RCSTAbits.SPEN = 1;
+"46
+[e = . . _RCSTAbits 0 7 -> -> 1 `i `uc ]
+[; ;user.c: 48: RCSTAbits.CREN = 1;
+"48
+[e = . . _RCSTAbits 0 4 -> -> 1 `i `uc ]
+[; ;user.c: 51: TXSTAbits.BRGH = 1;
+"51
+[e = . . _TXSTAbits 0 2 -> -> 1 `i `uc ]
+[; ;user.c: 52: BAUDCONbits.BRG16 = 1;
+"52
+[e = . . _BAUDCONbits 0 3 -> -> 1 `i `uc ]
+[; ;user.c: 54: SPBRG = 51;
+"54
+[e = _SPBRG -> -> 51 `i `uc ]
+[; ;user.c: 58: INTCONbits.GIE = 1;
+"58
+[e = . . _INTCONbits 0 7 -> -> 1 `i `uc ]
+[; ;user.c: 59: INTCONbits.PEIE = 1;
+"59
+[e = . . _INTCONbits 0 6 -> -> 1 `i `uc ]
+[; ;user.c: 62: PIE1bits.RCIE = 1;
+"62
+[e = . . _PIE1bits 0 5 -> -> 1 `i `uc ]
+[; ;user.c: 63: }
+"63
+[e :UE 524 ]
+}

diff --git a/build/XC8_12F1822/production/user.p1.d b/build/XC8_12F1822/production/user.p1.d
new file mode 100644 (file)
index 0000000..93d8cf6
--- /dev/null
+++ b/build/XC8_12F1822/production/user.p1.d
@@ -0,0 +1,5 @@
+ build/XC8_12F1822/production/user.d  \
+ build/XC8_12F1822/production/user.p1:  \
+ user.c  \
+user.h  \
+system.h 
\ No newline at end of file

diff --git a/build/XC8_12F1822/production/user.pre b/build/XC8_12F1822/production/user.pre
new file mode 100644 (file)
index 0000000..4b892c0
--- /dev/null
+++ b/build/XC8_12F1822/production/user.pre
@@ -0,0 +1,5684 @@
+
+# 1 "user.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1822.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+struct {
+unsigned AN0 :1;
+unsigned AN1 :1;
+unsigned AN2 :1;
+unsigned :1;
+unsigned AN3 :1;
+};
+struct {
+unsigned CPS0 :1;
+unsigned CPS1 :1;
+unsigned CPS2 :1;
+unsigned :1;
+unsigned CPS3 :1;
+};
+struct {
+unsigned C1INP :1;
+unsigned C1IN0N :1;
+unsigned C1OUT :1;
+unsigned :1;
+unsigned C1IN1N :1;
+};
+struct {
+unsigned DACOUT :1;
+unsigned SRI :1;
+unsigned SRQ :1;
+unsigned :2;
+unsigned SRNQ :1;
+};
+struct {
+unsigned :1;
+unsigned SCK :1;
+unsigned T0CKI :1;
+unsigned :1;
+unsigned T1OSO :1;
+unsigned T1CKI :1;
+};
+struct {
+unsigned :1;
+unsigned SCL :1;
+unsigned SDA :1;
+unsigned nMCLR :1;
+unsigned CLKR :1;
+unsigned T1OSI :1;
+};
+struct {
+unsigned MDOUT :1;
+unsigned MDMIN :1;
+unsigned MDCIN1 :1;
+unsigned :1;
+unsigned MDCIN2 :1;
+};
+struct {
+unsigned :2;
+unsigned SDI :1;
+unsigned :1;
+unsigned OSC2 :1;
+unsigned OSC1 :1;
+};
+struct {
+unsigned :2;
+unsigned FLT0 :1;
+unsigned :1;
+unsigned CLKOUT :1;
+unsigned CLKIN :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 698
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 759
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 798
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 817
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 842
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 861
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 932
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 1008
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 1027
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 1046
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 1116
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 1175
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 1208
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1257
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1318
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1357
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1439
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1489
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1547
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1604
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1675
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1736
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1761
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1780
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+struct {
+unsigned :1;
+unsigned nDONE :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1868
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1933
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1977
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 2033
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned :4;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 2086
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 2105
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :6;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 2131
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 2206
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2260
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2311
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2381
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2432
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2507
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2573
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2619
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2644
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2663
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2692
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2706
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2725
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2786
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2805
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2824
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2843
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2866
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2880
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2899
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2960
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 3021
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 3072
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 3129
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 3152
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 3166
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 3189
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 3203
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3226
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3240
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3305
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3361
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3438
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3500
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3564
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3629
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3685
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3750
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3806
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3825
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3844
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3925
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3994
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 4079
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 4155
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned STR1C :1;
+unsigned STR1D :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 4198
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4255
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4312
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4369
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4444
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4494
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4546
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4610
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4674
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4705
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4724
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4743
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4762
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4781
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4800
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4819
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4838
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4857
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4876
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4901
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit AN0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit AN1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit AN2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit AN3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1IN0N @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit C1IN1N @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit C1INP @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKIN @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit CLKOUT @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKR @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPS0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit CPS1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit CPS2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit CPS3 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACOUT @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FLT0 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCIN1 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit MDCIN2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMIN @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSC1 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit OSC2 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCK @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCL @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDA @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRI @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQ @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQ @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1C @ (((unsigned) &PSTR1CON)*8) + 2;
+
+extern volatile __bit STR1D @ (((unsigned) &PSTR1CON)*8) + 3;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CKI @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T1OSI @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit T1OSO @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit nMCLR @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+# 31 "system.h"
+void ConfigureOscillator(void);
+
+# 13 "user.h"
+void InitApp(void);
+bool msg_empty(void);
+void msg_write(const char *msg);
+void msg_writebyte(const char msg);
+void msg_sendnext(void);
+void tohex(char val[3], char i);
+void msg_recvnext(void);
+bool msg_recvready(void);
+char msg_recv(void);
+void putch(char);
+
+void int_disable(void);
+void int_enable(void);
+
+# 23 "user.c"
+void InitApp(void)
+{
+
+WDTCONbits.WDTPS = 0b01100;
+WDTCONbits.SWDTEN = 1;
+
+
+APFCONbits.RXDTSEL = 0;
+APFCONbits.TXCKSEL = 0;
+TRISAbits.TRISA1 = 1;
+TRISAbits.TRISA0 = 0;
+
+ANSELA = 0;
+
+
+
+WPUA = 0;
+
+OPTION_REGbits.nWPUEN = 1;
+
+
+TXSTAbits.TXEN = 1;
+TXSTAbits.SYNC = 0;
+RCSTAbits.SPEN = 1;
+
+RCSTAbits.CREN = 1;
+
+
+TXSTAbits.BRGH = 1;
+BAUDCONbits.BRG16 = 1;
+
+SPBRG = 51;
+
+
+
+INTCONbits.GIE = 1;
+INTCONbits.PEIE = 1;
+
+
+PIE1bits.RCIE = 1;
+}
+

diff --git a/build/XC8_PIC12F609/production/configuration_bits.p1 b/build/XC8_PIC12F609/production/configuration_bits.p1
new file mode 100644 (file)
index 0000000..d86ce7d
--- /dev/null
+++ b/build/XC8_PIC12F609/production/configuration_bits.p1
@@ -0,0 +1,2037 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+"37 configuration_bits.c
+[p x FOSC=INTOSC ]
+"38
+[p x WDTE=OFF ]
+"39
+[p x PWRTE=OFF ]
+"40
+[p x MCLRE=OFF ]
+"41
+[p x CP=OFF ]
+"42
+[p x CPD=OFF ]
+"43
+[p x BOREN=ON ]
+"44
+[p x CLKOUTEN=OFF ]
+"45
+[p x IESO=OFF ]
+"46
+[p x FCMEN=ON ]
+"49
+[p x WRT=OFF ]
+"50
+[p x PLLEN=ON ]
+"51
+[p x STVREN=ON ]
+"52
+[p x BORV=LO ]
+"53
+[p x LVP=ON ]

diff --git a/build/XC8_PIC12F609/production/configuration_bits.p1.d b/build/XC8_PIC12F609/production/configuration_bits.p1.d
new file mode 100644 (file)
index 0000000..5fc45c7
--- /dev/null
+++ b/build/XC8_PIC12F609/production/configuration_bits.p1.d
@@ -0,0 +1,3 @@
+ build/XC8_PIC12F609/production/configuration_bits.d  \
+ build/XC8_PIC12F609/production/configuration_bits.p1:  \
+ configuration_bits.c 
\ No newline at end of file

diff --git a/build/XC8_PIC12F609/production/configuration_bits.pre b/build/XC8_PIC12F609/production/configuration_bits.pre
new file mode 100644 (file)
index 0000000..59913a5
--- /dev/null
+++ b/build/XC8_PIC12F609/production/configuration_bits.pre
@@ -0,0 +1,2741 @@
+
+# 1 "configuration_bits.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+
+# 37 "configuration_bits.c"
+#pragma config FOSC = INTOSC
+#pragma config WDTE = OFF
+#pragma config PWRTE = OFF
+#pragma config MCLRE = OFF
+#pragma config CP = OFF
+#pragma config CPD = OFF
+#pragma config BOREN = ON
+#pragma config CLKOUTEN = OFF
+#pragma config IESO = OFF
+#pragma config FCMEN = ON
+
+
+#pragma config WRT = OFF
+#pragma config PLLEN = ON
+#pragma config STVREN = ON
+#pragma config BORV = LO
+#pragma config LVP = ON
+

diff --git a/build/XC8_PIC12F609/production/interrupts.p1 b/build/XC8_PIC12F609/production/interrupts.p1
new file mode 100644 (file)
index 0000000..a5d4cd9
--- /dev/null
+++ b/build/XC8_PIC12F609/production/interrupts.p1
@@ -0,0 +1,2048 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+"24 interrupts.c
+[v F2072 `(v ~T0 @X0 1 tf ]
+[v _isr `IF2072 ~T0 @X0 1 e ]
+{
+[; ;interrupts.c: 23: void interrupt isr(void)
+[; ;interrupts.c: 24: {
+[e :U _isr ]
+[f ]
+[; ;interrupts.c: 50: }
+"50
+[e :UE 259 ]
+}

diff --git a/build/XC8_PIC12F609/production/interrupts.p1.d b/build/XC8_PIC12F609/production/interrupts.p1.d
new file mode 100644 (file)
index 0000000..b250f3a
--- /dev/null
+++ b/build/XC8_PIC12F609/production/interrupts.p1.d
@@ -0,0 +1,3 @@
+ build/XC8_PIC12F609/production/interrupts.d  \
+ build/XC8_PIC12F609/production/interrupts.p1:  \
+ interrupts.c 
\ No newline at end of file

diff --git a/build/XC8_PIC12F609/production/interrupts.pre b/build/XC8_PIC12F609/production/interrupts.pre
new file mode 100644 (file)
index 0000000..9665315
--- /dev/null
+++ b/build/XC8_PIC12F609/production/interrupts.pre
@@ -0,0 +1,2821 @@
+
+# 1 "interrupts.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 23 "interrupts.c"
+void interrupt isr(void)
+{
+
+# 50
+}
+

diff --git a/build/XC8_PIC12F609/production/main.p1 b/build/XC8_PIC12F609/production/main.p1
new file mode 100644 (file)
index 0000000..e046845
--- /dev/null
+++ b/build/XC8_PIC12F609/production/main.p1
@@ -0,0 +1,2104 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[p mainexit ]
+"21 system.h
+[v _ConfigureOscillator `(v ~T0 @X0 0 ef ]
+"13 user.h
+[v _InitApp `(v ~T0 @X0 0 ef ]
+[s S32 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S32 . TMR1IF TMR2IF CCP1IF SSP1IF TXIF RCIF ADIF TMR1GIF ]
+[u S31 `S32 1 ]
+[n S31 . . ]
+"475 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[v _PIR1bits `VS31 ~T0 @X0 0 e@17 ]
+"2620
+[v _TXREG `Vuc ~T0 @X0 0 e@410 ]
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+[; ;system.h: 21: void ConfigureOscillator(void);
+[; ;user.h: 13: void InitApp(void);
+"28 main.c
+[v _main `(v ~T0 @X0 1 ef ]
+{
+[; ;main.c: 27: void main(void)
+[; ;main.c: 28: {
+[e :U _main ]
+[f ]
+[; ;main.c: 30: ConfigureOscillator();
+"30
+[e ( _ConfigureOscillator ..  ]
+[; ;main.c: 33: InitApp();
+"33
+[e ( _InitApp ..  ]
+"35
+[v _i `uc ~T0 @X0 1 a ]
+[; ;main.c: 35: char i = 'A';
+[e = _i -> -> 65 `ui `uc ]
+[; ;main.c: 37: while(1)
+"37
+[e :U 261 ]
+[; ;main.c: 38: {
+"38
+{
+[; ;main.c: 39: if (PIR1bits.TXIF) {
+"39
+[e $ ! != -> . . _PIR1bits 0 4 `i -> -> -> 0 `i `Vuc `i 263  ]
+{
+[; ;main.c: 40: TXREG = i;
+"40
+[e = _TXREG _i ]
+[; ;main.c: 41: i++;
+"41
+[e ++ _i -> -> 1 `i `uc ]
+[; ;main.c: 42: if (i > 'Z') i='A';
+"42
+[e $ ! > -> _i `ui -> 90 `ui 264  ]
+[e = _i -> -> 65 `ui `uc ]
+[e :U 264 ]
+"43
+}
+[e :U 263 ]
+"44
+}
+[e :U 260 ]
+"37
+[e $U 261  ]
+[e :U 262 ]
+[; ;main.c: 43: }
+[; ;main.c: 44: }
+[; ;main.c: 45: }
+"45
+[e :UE 259 ]
+}

diff --git a/build/XC8_PIC12F609/production/main.p1.d b/build/XC8_PIC12F609/production/main.p1.d
new file mode 100644 (file)
index 0000000..260ca9a
--- /dev/null
+++ b/build/XC8_PIC12F609/production/main.p1.d
@@ -0,0 +1,5 @@
+ build/XC8_PIC12F609/production/main.d  \
+ build/XC8_PIC12F609/production/main.p1:  \
+ main.c  \
+user.h  \
+system.h 
\ No newline at end of file

diff --git a/build/XC8_PIC12F609/production/main.pre b/build/XC8_PIC12F609/production/main.pre
new file mode 100644 (file)
index 0000000..2ccd93d
--- /dev/null
+++ b/build/XC8_PIC12F609/production/main.pre
@@ -0,0 +1,2841 @@
+
+# 1 "main.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 21 "system.h"
+void ConfigureOscillator(void);
+
+# 13 "user.h"
+void InitApp(void);
+
+# 27 "main.c"
+void main(void)
+{
+
+ConfigureOscillator();
+
+
+InitApp();
+
+char i = 'A';
+
+while(1)
+{
+if (PIR1bits.TXIF) {
+TXREG = i;
+i++;
+if (i > 'Z') i='A';
+}
+}
+}
+

diff --git a/build/XC8_PIC12F609/production/system.p1 b/build/XC8_PIC12F609/production/system.p1
new file mode 100644 (file)
index 0000000..50e65f0
--- /dev/null
+++ b/build/XC8_PIC12F609/production/system.p1
@@ -0,0 +1,2048 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+[; ;system.h: 21: void ConfigureOscillator(void);
+"19 system.c
+[v _ConfigureOscillator `(v ~T0 @X0 1 ef ]
+{
+[; ;system.c: 18: void ConfigureOscillator(void)
+[; ;system.c: 19: {
+[e :U _ConfigureOscillator ]
+[f ]
+[; ;system.c: 40: }
+"40
+[e :UE 259 ]
+}

diff --git a/build/XC8_PIC12F609/production/system.p1.d b/build/XC8_PIC12F609/production/system.p1.d
new file mode 100644 (file)
index 0000000..11dc5f5
--- /dev/null
+++ b/build/XC8_PIC12F609/production/system.p1.d
@@ -0,0 +1,4 @@
+ build/XC8_PIC12F609/production/system.d  \
+ build/XC8_PIC12F609/production/system.p1:  \
+ system.c  \
+system.h 
\ No newline at end of file

diff --git a/build/XC8_PIC12F609/production/system.pre b/build/XC8_PIC12F609/production/system.pre
new file mode 100644 (file)
index 0000000..23a76c8
--- /dev/null
+++ b/build/XC8_PIC12F609/production/system.pre
@@ -0,0 +1,2823 @@
+
+# 1 "system.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 21 "system.h"
+void ConfigureOscillator(void);
+
+# 18 "system.c"
+void ConfigureOscillator(void)
+{
+
+# 40
+}

diff --git a/build/XC8_PIC12F609/production/user.p1 b/build/XC8_PIC12F609/production/user.p1
new file mode 100644 (file)
index 0000000..09e044d
--- /dev/null
+++ b/build/XC8_PIC12F609/production/user.p1
@@ -0,0 +1,2153 @@
+Version 3.2 HI-TECH Software Intermediate Code
+[s S78 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S78 . SCS0 SCS1 . IRCF0 IRCF1 IRCF2 IRCF3 SPLLEN ]
+[s S79 :2 `uc 1 :1 `uc 1 :4 `uc 1 ]
+[n S79 . SCS . IRCF ]
+[u S77 `S78 1 `S79 1 ]
+[n S77 . . . ]
+"1386 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[v _OSCCONbits `VS77 ~T0 @X0 0 e@153 ]
+[s S157 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S157 . TX9D TRMT BRGH SENDB SYNC TXEN TX9 CSRC ]
+[u S156 `S157 1 ]
+[n S156 . . ]
+"2773
+[v _TXSTAbits `VS156 ~T0 @X0 0 e@414 ]
+[s S155 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S155 . RX9D OERR FERR ADDEN CREN SREN RX9 SPEN ]
+[u S154 `S155 1 ]
+[n S154 . . ]
+"2712
+[v _RCSTAbits `VS154 ~T0 @X0 0 e@413 ]
+[s S159 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S159 . ABDEN WUE . BRG16 SCKP . RCIDL ABDOVF ]
+[u S158 `S159 1 ]
+[n S158 . . ]
+"2834
+[v _BAUDCONbits `VS158 ~T0 @X0 0 e@415 ]
+"2644
+[v _SPBRG `Vuc ~T0 @X0 0 e@411 ]
+[s S119 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S119 . CCP1SEL P1BSEL TXCKSEL T1GSEL . SSSEL SDOSEL RXDTSEL ]
+[s S120 :5 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S120 . . SS1SEL SDO1SEL ]
+[u S118 `S119 1 `S120 1 ]
+[n S118 . . . ]
+"2222
+[v _APFCONbits `VS118 ~T0 @X0 0 e@285 ]
+[s S61 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S61 . TRISA0 TRISA1 TRISA2 TRISA3 TRISA4 TRISA5 ]
+[u S60 `S61 1 ]
+[n S60 . . ]
+"983
+[v _TRISAbits `VS60 ~T0 @X0 0 e@140 ]
+"2336
+[v _ANSELA `Vuc ~T0 @X0 0 e@396 ]
+"2868
+[v _WPUA `Vuc ~T0 @X0 0 e@524 ]
+[s S67 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S67 . PS0 PS1 PS2 PSA TMR0SE TMR0CS INTEDG nWPUEN ]
+[s S68 :3 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ]
+[n S68 . PS . T0SE T0CS ]
+[u S66 `S67 1 `S68 1 ]
+[n S66 . . . ]
+"1140
+[v _OPTION_REGbits `VS66 ~T0 @X0 0 e@149 ]
+[; ;pic12f1840.h: 44: extern volatile unsigned char INDF0 @ 0x000;
+"46 /opt/microchip/xc8/v1.12/include/pic12f1840.h
+[; ;pic12f1840.h: 46: asm("INDF0 equ 00h");
+[; <" INDF0 equ 00h ;# ">
+[; ;pic12f1840.h: 49: typedef union {
+[; ;pic12f1840.h: 50: struct {
+[; ;pic12f1840.h: 51: unsigned INDF0 :8;
+[; ;pic12f1840.h: 52: };
+[; ;pic12f1840.h: 53: } INDF0bits_t;
+[; ;pic12f1840.h: 54: extern volatile INDF0bits_t INDF0bits @ 0x000;
+[; ;pic12f1840.h: 63: extern volatile unsigned char INDF1 @ 0x001;
+"65
+[; ;pic12f1840.h: 65: asm("INDF1 equ 01h");
+[; <" INDF1 equ 01h ;# ">
+[; ;pic12f1840.h: 68: typedef union {
+[; ;pic12f1840.h: 69: struct {
+[; ;pic12f1840.h: 70: unsigned INDF1 :8;
+[; ;pic12f1840.h: 71: };
+[; ;pic12f1840.h: 72: } INDF1bits_t;
+[; ;pic12f1840.h: 73: extern volatile INDF1bits_t INDF1bits @ 0x001;
+[; ;pic12f1840.h: 82: extern volatile unsigned char PCL @ 0x002;
+"84
+[; ;pic12f1840.h: 84: asm("PCL equ 02h");
+[; <" PCL equ 02h ;# ">
+[; ;pic12f1840.h: 87: typedef union {
+[; ;pic12f1840.h: 88: struct {
+[; ;pic12f1840.h: 89: unsigned PCL :8;
+[; ;pic12f1840.h: 90: };
+[; ;pic12f1840.h: 91: } PCLbits_t;
+[; ;pic12f1840.h: 92: extern volatile PCLbits_t PCLbits @ 0x002;
+[; ;pic12f1840.h: 101: extern volatile unsigned char STATUS @ 0x003;
+"103
+[; ;pic12f1840.h: 103: asm("STATUS equ 03h");
+[; <" STATUS equ 03h ;# ">
+[; ;pic12f1840.h: 106: typedef union {
+[; ;pic12f1840.h: 107: struct {
+[; ;pic12f1840.h: 108: unsigned C :1;
+[; ;pic12f1840.h: 109: unsigned DC :1;
+[; ;pic12f1840.h: 110: unsigned Z :1;
+[; ;pic12f1840.h: 111: unsigned nPD :1;
+[; ;pic12f1840.h: 112: unsigned nTO :1;
+[; ;pic12f1840.h: 113: };
+[; ;pic12f1840.h: 114: struct {
+[; ;pic12f1840.h: 115: unsigned CARRY :1;
+[; ;pic12f1840.h: 116: };
+[; ;pic12f1840.h: 117: struct {
+[; ;pic12f1840.h: 118: unsigned :2;
+[; ;pic12f1840.h: 119: unsigned ZERO :1;
+[; ;pic12f1840.h: 120: };
+[; ;pic12f1840.h: 121: } STATUSbits_t;
+[; ;pic12f1840.h: 122: extern volatile STATUSbits_t STATUSbits @ 0x003;
+[; ;pic12f1840.h: 161: extern volatile unsigned short FSR0 @ 0x004;
+[; ;pic12f1840.h: 164: extern volatile unsigned char FSR0L @ 0x004;
+"166
+[; ;pic12f1840.h: 166: asm("FSR0L equ 04h");
+[; <" FSR0L equ 04h ;# ">
+[; ;pic12f1840.h: 169: typedef union {
+[; ;pic12f1840.h: 170: struct {
+[; ;pic12f1840.h: 171: unsigned FSR0L :8;
+[; ;pic12f1840.h: 172: };
+[; ;pic12f1840.h: 173: } FSR0Lbits_t;
+[; ;pic12f1840.h: 174: extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+[; ;pic12f1840.h: 183: extern volatile unsigned char FSR0H @ 0x005;
+"185
+[; ;pic12f1840.h: 185: asm("FSR0H equ 05h");
+[; <" FSR0H equ 05h ;# ">
+[; ;pic12f1840.h: 188: typedef union {
+[; ;pic12f1840.h: 189: struct {
+[; ;pic12f1840.h: 190: unsigned FSR0H :8;
+[; ;pic12f1840.h: 191: };
+[; ;pic12f1840.h: 192: } FSR0Hbits_t;
+[; ;pic12f1840.h: 193: extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+[; ;pic12f1840.h: 202: extern volatile unsigned short FSR1 @ 0x006;
+[; ;pic12f1840.h: 205: extern volatile unsigned char FSR1L @ 0x006;
+"207
+[; ;pic12f1840.h: 207: asm("FSR1L equ 06h");
+[; <" FSR1L equ 06h ;# ">
+[; ;pic12f1840.h: 210: typedef union {
+[; ;pic12f1840.h: 211: struct {
+[; ;pic12f1840.h: 212: unsigned FSR1L :8;
+[; ;pic12f1840.h: 213: };
+[; ;pic12f1840.h: 214: } FSR1Lbits_t;
+[; ;pic12f1840.h: 215: extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+[; ;pic12f1840.h: 224: extern volatile unsigned char FSR1H @ 0x007;
+"226
+[; ;pic12f1840.h: 226: asm("FSR1H equ 07h");
+[; <" FSR1H equ 07h ;# ">
+[; ;pic12f1840.h: 229: typedef union {
+[; ;pic12f1840.h: 230: struct {
+[; ;pic12f1840.h: 231: unsigned FSR1H :8;
+[; ;pic12f1840.h: 232: };
+[; ;pic12f1840.h: 233: } FSR1Hbits_t;
+[; ;pic12f1840.h: 234: extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+[; ;pic12f1840.h: 243: extern volatile unsigned char BSR @ 0x008;
+"245
+[; ;pic12f1840.h: 245: asm("BSR equ 08h");
+[; <" BSR equ 08h ;# ">
+[; ;pic12f1840.h: 248: typedef union {
+[; ;pic12f1840.h: 249: struct {
+[; ;pic12f1840.h: 250: unsigned BSR0 :1;
+[; ;pic12f1840.h: 251: unsigned BSR1 :1;
+[; ;pic12f1840.h: 252: unsigned BSR2 :1;
+[; ;pic12f1840.h: 253: unsigned BSR3 :1;
+[; ;pic12f1840.h: 254: unsigned BSR4 :1;
+[; ;pic12f1840.h: 255: };
+[; ;pic12f1840.h: 256: struct {
+[; ;pic12f1840.h: 257: unsigned BSR :5;
+[; ;pic12f1840.h: 258: };
+[; ;pic12f1840.h: 259: } BSRbits_t;
+[; ;pic12f1840.h: 260: extern volatile BSRbits_t BSRbits @ 0x008;
+[; ;pic12f1840.h: 294: extern volatile unsigned char WREG @ 0x009;
+"296
+[; ;pic12f1840.h: 296: asm("WREG equ 09h");
+[; <" WREG equ 09h ;# ">
+[; ;pic12f1840.h: 299: typedef union {
+[; ;pic12f1840.h: 300: struct {
+[; ;pic12f1840.h: 301: unsigned WREG0 :8;
+[; ;pic12f1840.h: 302: };
+[; ;pic12f1840.h: 303: } WREGbits_t;
+[; ;pic12f1840.h: 304: extern volatile WREGbits_t WREGbits @ 0x009;
+[; ;pic12f1840.h: 313: extern volatile unsigned char PCLATH @ 0x00A;
+"315
+[; ;pic12f1840.h: 315: asm("PCLATH equ 0Ah");
+[; <" PCLATH equ 0Ah ;# ">
+[; ;pic12f1840.h: 318: typedef union {
+[; ;pic12f1840.h: 319: struct {
+[; ;pic12f1840.h: 320: unsigned PCLATH :7;
+[; ;pic12f1840.h: 321: };
+[; ;pic12f1840.h: 322: } PCLATHbits_t;
+[; ;pic12f1840.h: 323: extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+[; ;pic12f1840.h: 332: extern volatile unsigned char INTCON @ 0x00B;
+"334
+[; ;pic12f1840.h: 334: asm("INTCON equ 0Bh");
+[; <" INTCON equ 0Bh ;# ">
+[; ;pic12f1840.h: 337: typedef union {
+[; ;pic12f1840.h: 338: struct {
+[; ;pic12f1840.h: 339: unsigned IOCIF :1;
+[; ;pic12f1840.h: 340: unsigned INTF :1;
+[; ;pic12f1840.h: 341: unsigned TMR0IF :1;
+[; ;pic12f1840.h: 342: unsigned IOCIE :1;
+[; ;pic12f1840.h: 343: unsigned INTE :1;
+[; ;pic12f1840.h: 344: unsigned TMR0IE :1;
+[; ;pic12f1840.h: 345: unsigned PEIE :1;
+[; ;pic12f1840.h: 346: unsigned GIE :1;
+[; ;pic12f1840.h: 347: };
+[; ;pic12f1840.h: 348: struct {
+[; ;pic12f1840.h: 349: unsigned :2;
+[; ;pic12f1840.h: 350: unsigned T0IF :1;
+[; ;pic12f1840.h: 351: unsigned :2;
+[; ;pic12f1840.h: 352: unsigned T0IE :1;
+[; ;pic12f1840.h: 353: };
+[; ;pic12f1840.h: 354: } INTCONbits_t;
+[; ;pic12f1840.h: 355: extern volatile INTCONbits_t INTCONbits @ 0x00B;
+[; ;pic12f1840.h: 409: extern volatile unsigned char PORTA @ 0x00C;
+"411
+[; ;pic12f1840.h: 411: asm("PORTA equ 0Ch");
+[; <" PORTA equ 0Ch ;# ">
+[; ;pic12f1840.h: 414: typedef union {
+[; ;pic12f1840.h: 415: struct {
+[; ;pic12f1840.h: 416: unsigned RA0 :1;
+[; ;pic12f1840.h: 417: unsigned RA1 :1;
+[; ;pic12f1840.h: 418: unsigned RA2 :1;
+[; ;pic12f1840.h: 419: unsigned RA3 :1;
+[; ;pic12f1840.h: 420: unsigned RA4 :1;
+[; ;pic12f1840.h: 421: unsigned RA5 :1;
+[; ;pic12f1840.h: 422: };
+[; ;pic12f1840.h: 423: } PORTAbits_t;
+[; ;pic12f1840.h: 424: extern volatile PORTAbits_t PORTAbits @ 0x00C;
+[; ;pic12f1840.h: 458: extern volatile unsigned char PIR1 @ 0x011;
+"460
+[; ;pic12f1840.h: 460: asm("PIR1 equ 011h");
+[; <" PIR1 equ 011h ;# ">
+[; ;pic12f1840.h: 463: typedef union {
+[; ;pic12f1840.h: 464: struct {
+[; ;pic12f1840.h: 465: unsigned TMR1IF :1;
+[; ;pic12f1840.h: 466: unsigned TMR2IF :1;
+[; ;pic12f1840.h: 467: unsigned CCP1IF :1;
+[; ;pic12f1840.h: 468: unsigned SSP1IF :1;
+[; ;pic12f1840.h: 469: unsigned TXIF :1;
+[; ;pic12f1840.h: 470: unsigned RCIF :1;
+[; ;pic12f1840.h: 471: unsigned ADIF :1;
+[; ;pic12f1840.h: 472: unsigned TMR1GIF :1;
+[; ;pic12f1840.h: 473: };
+[; ;pic12f1840.h: 474: } PIR1bits_t;
+[; ;pic12f1840.h: 475: extern volatile PIR1bits_t PIR1bits @ 0x011;
+[; ;pic12f1840.h: 519: extern volatile unsigned char PIR2 @ 0x012;
+"521
+[; ;pic12f1840.h: 521: asm("PIR2 equ 012h");
+[; <" PIR2 equ 012h ;# ">
+[; ;pic12f1840.h: 524: typedef union {
+[; ;pic12f1840.h: 525: struct {
+[; ;pic12f1840.h: 526: unsigned :3;
+[; ;pic12f1840.h: 527: unsigned BCL1IF :1;
+[; ;pic12f1840.h: 528: unsigned EEIF :1;
+[; ;pic12f1840.h: 529: unsigned C1IF :1;
+[; ;pic12f1840.h: 530: unsigned :1;
+[; ;pic12f1840.h: 531: unsigned OSFIF :1;
+[; ;pic12f1840.h: 532: };
+[; ;pic12f1840.h: 533: } PIR2bits_t;
+[; ;pic12f1840.h: 534: extern volatile PIR2bits_t PIR2bits @ 0x012;
+[; ;pic12f1840.h: 558: extern volatile unsigned char TMR0 @ 0x015;
+"560
+[; ;pic12f1840.h: 560: asm("TMR0 equ 015h");
+[; <" TMR0 equ 015h ;# ">
+[; ;pic12f1840.h: 563: typedef union {
+[; ;pic12f1840.h: 564: struct {
+[; ;pic12f1840.h: 565: unsigned TMR0 :8;
+[; ;pic12f1840.h: 566: };
+[; ;pic12f1840.h: 567: } TMR0bits_t;
+[; ;pic12f1840.h: 568: extern volatile TMR0bits_t TMR0bits @ 0x015;
+[; ;pic12f1840.h: 577: extern volatile unsigned short TMR1 @ 0x016;
+"579
+[; ;pic12f1840.h: 579: asm("TMR1 equ 016h");
+[; <" TMR1 equ 016h ;# ">
+[; ;pic12f1840.h: 583: extern volatile unsigned char TMR1L @ 0x016;
+"585
+[; ;pic12f1840.h: 585: asm("TMR1L equ 016h");
+[; <" TMR1L equ 016h ;# ">
+[; ;pic12f1840.h: 588: typedef union {
+[; ;pic12f1840.h: 589: struct {
+[; ;pic12f1840.h: 590: unsigned TMR1L :8;
+[; ;pic12f1840.h: 591: };
+[; ;pic12f1840.h: 592: } TMR1Lbits_t;
+[; ;pic12f1840.h: 593: extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+[; ;pic12f1840.h: 602: extern volatile unsigned char TMR1H @ 0x017;
+"604
+[; ;pic12f1840.h: 604: asm("TMR1H equ 017h");
+[; <" TMR1H equ 017h ;# ">
+[; ;pic12f1840.h: 607: typedef union {
+[; ;pic12f1840.h: 608: struct {
+[; ;pic12f1840.h: 609: unsigned TMR1H :8;
+[; ;pic12f1840.h: 610: };
+[; ;pic12f1840.h: 611: } TMR1Hbits_t;
+[; ;pic12f1840.h: 612: extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+[; ;pic12f1840.h: 621: extern volatile unsigned char T1CON @ 0x018;
+"623
+[; ;pic12f1840.h: 623: asm("T1CON equ 018h");
+[; <" T1CON equ 018h ;# ">
+[; ;pic12f1840.h: 626: typedef union {
+[; ;pic12f1840.h: 627: struct {
+[; ;pic12f1840.h: 628: unsigned TMR1ON :1;
+[; ;pic12f1840.h: 629: unsigned :1;
+[; ;pic12f1840.h: 630: unsigned nT1SYNC :1;
+[; ;pic12f1840.h: 631: unsigned T1OSCEN :1;
+[; ;pic12f1840.h: 632: unsigned T1CKPS0 :1;
+[; ;pic12f1840.h: 633: unsigned T1CKPS1 :1;
+[; ;pic12f1840.h: 634: unsigned TMR1CS0 :1;
+[; ;pic12f1840.h: 635: unsigned TMR1CS1 :1;
+[; ;pic12f1840.h: 636: };
+[; ;pic12f1840.h: 637: struct {
+[; ;pic12f1840.h: 638: unsigned :4;
+[; ;pic12f1840.h: 639: unsigned T1CKPS :2;
+[; ;pic12f1840.h: 640: unsigned TMR1CS :2;
+[; ;pic12f1840.h: 641: };
+[; ;pic12f1840.h: 642: } T1CONbits_t;
+[; ;pic12f1840.h: 643: extern volatile T1CONbits_t T1CONbits @ 0x018;
+[; ;pic12f1840.h: 692: extern volatile unsigned char T1GCON @ 0x019;
+"694
+[; ;pic12f1840.h: 694: asm("T1GCON equ 019h");
+[; <" T1GCON equ 019h ;# ">
+[; ;pic12f1840.h: 697: typedef union {
+[; ;pic12f1840.h: 698: struct {
+[; ;pic12f1840.h: 699: unsigned T1GSS0 :1;
+[; ;pic12f1840.h: 700: unsigned T1GSS1 :1;
+[; ;pic12f1840.h: 701: unsigned T1GVAL :1;
+[; ;pic12f1840.h: 702: unsigned T1GGO_nDONE :1;
+[; ;pic12f1840.h: 703: unsigned T1GSPM :1;
+[; ;pic12f1840.h: 704: unsigned T1GTM :1;
+[; ;pic12f1840.h: 705: unsigned T1GPOL :1;
+[; ;pic12f1840.h: 706: unsigned TMR1GE :1;
+[; ;pic12f1840.h: 707: };
+[; ;pic12f1840.h: 708: struct {
+[; ;pic12f1840.h: 709: unsigned T1GSS :2;
+[; ;pic12f1840.h: 710: unsigned :1;
+[; ;pic12f1840.h: 711: unsigned T1GGO :1;
+[; ;pic12f1840.h: 712: };
+[; ;pic12f1840.h: 713: } T1GCONbits_t;
+[; ;pic12f1840.h: 714: extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+[; ;pic12f1840.h: 768: extern volatile unsigned char TMR2 @ 0x01A;
+"770
+[; ;pic12f1840.h: 770: asm("TMR2 equ 01Ah");
+[; <" TMR2 equ 01Ah ;# ">
+[; ;pic12f1840.h: 773: typedef union {
+[; ;pic12f1840.h: 774: struct {
+[; ;pic12f1840.h: 775: unsigned TMR2 :8;
+[; ;pic12f1840.h: 776: };
+[; ;pic12f1840.h: 777: } TMR2bits_t;
+[; ;pic12f1840.h: 778: extern volatile TMR2bits_t TMR2bits @ 0x01A;
+[; ;pic12f1840.h: 787: extern volatile unsigned char PR2 @ 0x01B;
+"789
+[; ;pic12f1840.h: 789: asm("PR2 equ 01Bh");
+[; <" PR2 equ 01Bh ;# ">
+[; ;pic12f1840.h: 792: typedef union {
+[; ;pic12f1840.h: 793: struct {
+[; ;pic12f1840.h: 794: unsigned PR2 :8;
+[; ;pic12f1840.h: 795: };
+[; ;pic12f1840.h: 796: } PR2bits_t;
+[; ;pic12f1840.h: 797: extern volatile PR2bits_t PR2bits @ 0x01B;
+[; ;pic12f1840.h: 806: extern volatile unsigned char T2CON @ 0x01C;
+"808
+[; ;pic12f1840.h: 808: asm("T2CON equ 01Ch");
+[; <" T2CON equ 01Ch ;# ">
+[; ;pic12f1840.h: 811: typedef union {
+[; ;pic12f1840.h: 812: struct {
+[; ;pic12f1840.h: 813: unsigned T2CKPS0 :1;
+[; ;pic12f1840.h: 814: unsigned T2CKPS1 :1;
+[; ;pic12f1840.h: 815: unsigned TMR2ON :1;
+[; ;pic12f1840.h: 816: unsigned T2OUTPS0 :1;
+[; ;pic12f1840.h: 817: unsigned T2OUTPS1 :1;
+[; ;pic12f1840.h: 818: unsigned T2OUTPS2 :1;
+[; ;pic12f1840.h: 819: unsigned T2OUTPS3 :1;
+[; ;pic12f1840.h: 820: };
+[; ;pic12f1840.h: 821: struct {
+[; ;pic12f1840.h: 822: unsigned T2CKPS :2;
+[; ;pic12f1840.h: 823: unsigned :1;
+[; ;pic12f1840.h: 824: unsigned T2OUTPS :4;
+[; ;pic12f1840.h: 825: };
+[; ;pic12f1840.h: 826: } T2CONbits_t;
+[; ;pic12f1840.h: 827: extern volatile T2CONbits_t T2CONbits @ 0x01C;
+[; ;pic12f1840.h: 876: extern volatile unsigned char CPSCON0 @ 0x01E;
+"878
+[; ;pic12f1840.h: 878: asm("CPSCON0 equ 01Eh");
+[; <" CPSCON0 equ 01Eh ;# ">
+[; ;pic12f1840.h: 881: typedef union {
+[; ;pic12f1840.h: 882: struct {
+[; ;pic12f1840.h: 883: unsigned T0XCS :1;
+[; ;pic12f1840.h: 884: unsigned CPSOUT :1;
+[; ;pic12f1840.h: 885: unsigned CPSRNG0 :1;
+[; ;pic12f1840.h: 886: unsigned CPSRNG1 :1;
+[; ;pic12f1840.h: 887: unsigned :2;
+[; ;pic12f1840.h: 888: unsigned CPSRM :1;
+[; ;pic12f1840.h: 889: unsigned CPSON :1;
+[; ;pic12f1840.h: 890: };
+[; ;pic12f1840.h: 891: struct {
+[; ;pic12f1840.h: 892: unsigned :2;
+[; ;pic12f1840.h: 893: unsigned CPSRNG :2;
+[; ;pic12f1840.h: 894: };
+[; ;pic12f1840.h: 895: } CPSCON0bits_t;
+[; ;pic12f1840.h: 896: extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+[; ;pic12f1840.h: 935: extern volatile unsigned char CPSCON1 @ 0x01F;
+"937
+[; ;pic12f1840.h: 937: asm("CPSCON1 equ 01Fh");
+[; <" CPSCON1 equ 01Fh ;# ">
+[; ;pic12f1840.h: 940: typedef union {
+[; ;pic12f1840.h: 941: struct {
+[; ;pic12f1840.h: 942: unsigned CPSCH0 :1;
+[; ;pic12f1840.h: 943: unsigned CPSCH1 :1;
+[; ;pic12f1840.h: 944: };
+[; ;pic12f1840.h: 945: struct {
+[; ;pic12f1840.h: 946: unsigned CPSCH :2;
+[; ;pic12f1840.h: 947: };
+[; ;pic12f1840.h: 948: } CPSCON1bits_t;
+[; ;pic12f1840.h: 949: extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+[; ;pic12f1840.h: 968: extern volatile unsigned char TRISA @ 0x08C;
+"970
+[; ;pic12f1840.h: 970: asm("TRISA equ 08Ch");
+[; <" TRISA equ 08Ch ;# ">
+[; ;pic12f1840.h: 973: typedef union {
+[; ;pic12f1840.h: 974: struct {
+[; ;pic12f1840.h: 975: unsigned TRISA0 :1;
+[; ;pic12f1840.h: 976: unsigned TRISA1 :1;
+[; ;pic12f1840.h: 977: unsigned TRISA2 :1;
+[; ;pic12f1840.h: 978: unsigned TRISA3 :1;
+[; ;pic12f1840.h: 979: unsigned TRISA4 :1;
+[; ;pic12f1840.h: 980: unsigned TRISA5 :1;
+[; ;pic12f1840.h: 981: };
+[; ;pic12f1840.h: 982: } TRISAbits_t;
+[; ;pic12f1840.h: 983: extern volatile TRISAbits_t TRISAbits @ 0x08C;
+[; ;pic12f1840.h: 1017: extern volatile unsigned char PIE1 @ 0x091;
+"1019
+[; ;pic12f1840.h: 1019: asm("PIE1 equ 091h");
+[; <" PIE1 equ 091h ;# ">
+[; ;pic12f1840.h: 1022: typedef union {
+[; ;pic12f1840.h: 1023: struct {
+[; ;pic12f1840.h: 1024: unsigned TMR1IE :1;
+[; ;pic12f1840.h: 1025: unsigned TMR2IE :1;
+[; ;pic12f1840.h: 1026: unsigned CCP1IE :1;
+[; ;pic12f1840.h: 1027: unsigned SSP1IE :1;
+[; ;pic12f1840.h: 1028: unsigned TXIE :1;
+[; ;pic12f1840.h: 1029: unsigned RCIE :1;
+[; ;pic12f1840.h: 1030: unsigned ADIE :1;
+[; ;pic12f1840.h: 1031: unsigned TMR1GIE :1;
+[; ;pic12f1840.h: 1032: };
+[; ;pic12f1840.h: 1033: } PIE1bits_t;
+[; ;pic12f1840.h: 1034: extern volatile PIE1bits_t PIE1bits @ 0x091;
+[; ;pic12f1840.h: 1078: extern volatile unsigned char PIE2 @ 0x092;
+"1080
+[; ;pic12f1840.h: 1080: asm("PIE2 equ 092h");
+[; <" PIE2 equ 092h ;# ">
+[; ;pic12f1840.h: 1083: typedef union {
+[; ;pic12f1840.h: 1084: struct {
+[; ;pic12f1840.h: 1085: unsigned :3;
+[; ;pic12f1840.h: 1086: unsigned BCL1IE :1;
+[; ;pic12f1840.h: 1087: unsigned EEIE :1;
+[; ;pic12f1840.h: 1088: unsigned C1IE :1;
+[; ;pic12f1840.h: 1089: unsigned :1;
+[; ;pic12f1840.h: 1090: unsigned OSFIE :1;
+[; ;pic12f1840.h: 1091: };
+[; ;pic12f1840.h: 1092: } PIE2bits_t;
+[; ;pic12f1840.h: 1093: extern volatile PIE2bits_t PIE2bits @ 0x092;
+[; ;pic12f1840.h: 1117: extern volatile unsigned char OPTION_REG @ 0x095;
+"1119
+[; ;pic12f1840.h: 1119: asm("OPTION_REG equ 095h");
+[; <" OPTION_REG equ 095h ;# ">
+[; ;pic12f1840.h: 1122: typedef union {
+[; ;pic12f1840.h: 1123: struct {
+[; ;pic12f1840.h: 1124: unsigned PS0 :1;
+[; ;pic12f1840.h: 1125: unsigned PS1 :1;
+[; ;pic12f1840.h: 1126: unsigned PS2 :1;
+[; ;pic12f1840.h: 1127: unsigned PSA :1;
+[; ;pic12f1840.h: 1128: unsigned TMR0SE :1;
+[; ;pic12f1840.h: 1129: unsigned TMR0CS :1;
+[; ;pic12f1840.h: 1130: unsigned INTEDG :1;
+[; ;pic12f1840.h: 1131: unsigned nWPUEN :1;
+[; ;pic12f1840.h: 1132: };
+[; ;pic12f1840.h: 1133: struct {
+[; ;pic12f1840.h: 1134: unsigned PS :3;
+[; ;pic12f1840.h: 1135: unsigned :1;
+[; ;pic12f1840.h: 1136: unsigned T0SE :1;
+[; ;pic12f1840.h: 1137: unsigned T0CS :1;
+[; ;pic12f1840.h: 1138: };
+[; ;pic12f1840.h: 1139: } OPTION_REGbits_t;
+[; ;pic12f1840.h: 1140: extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+[; ;pic12f1840.h: 1199: extern volatile unsigned char PCON @ 0x096;
+"1201
+[; ;pic12f1840.h: 1201: asm("PCON equ 096h");
+[; <" PCON equ 096h ;# ">
+[; ;pic12f1840.h: 1204: typedef union {
+[; ;pic12f1840.h: 1205: struct {
+[; ;pic12f1840.h: 1206: unsigned nBOR :1;
+[; ;pic12f1840.h: 1207: unsigned nPOR :1;
+[; ;pic12f1840.h: 1208: unsigned nRI :1;
+[; ;pic12f1840.h: 1209: unsigned nRMCLR :1;
+[; ;pic12f1840.h: 1210: unsigned :2;
+[; ;pic12f1840.h: 1211: unsigned STKUNF :1;
+[; ;pic12f1840.h: 1212: unsigned STKOVF :1;
+[; ;pic12f1840.h: 1213: };
+[; ;pic12f1840.h: 1214: } PCONbits_t;
+[; ;pic12f1840.h: 1215: extern volatile PCONbits_t PCONbits @ 0x096;
+[; ;pic12f1840.h: 1249: extern volatile unsigned char WDTCON @ 0x097;
+"1251
+[; ;pic12f1840.h: 1251: asm("WDTCON equ 097h");
+[; <" WDTCON equ 097h ;# ">
+[; ;pic12f1840.h: 1254: typedef union {
+[; ;pic12f1840.h: 1255: struct {
+[; ;pic12f1840.h: 1256: unsigned SWDTEN :1;
+[; ;pic12f1840.h: 1257: unsigned WDTPS0 :1;
+[; ;pic12f1840.h: 1258: unsigned WDTPS1 :1;
+[; ;pic12f1840.h: 1259: unsigned WDTPS2 :1;
+[; ;pic12f1840.h: 1260: unsigned WDTPS3 :1;
+[; ;pic12f1840.h: 1261: unsigned WDTPS4 :1;
+[; ;pic12f1840.h: 1262: };
+[; ;pic12f1840.h: 1263: struct {
+[; ;pic12f1840.h: 1264: unsigned :1;
+[; ;pic12f1840.h: 1265: unsigned WDTPS :5;
+[; ;pic12f1840.h: 1266: };
+[; ;pic12f1840.h: 1267: } WDTCONbits_t;
+[; ;pic12f1840.h: 1268: extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+[; ;pic12f1840.h: 1307: extern volatile unsigned char OSCTUNE @ 0x098;
+"1309
+[; ;pic12f1840.h: 1309: asm("OSCTUNE equ 098h");
+[; <" OSCTUNE equ 098h ;# ">
+[; ;pic12f1840.h: 1312: typedef union {
+[; ;pic12f1840.h: 1313: struct {
+[; ;pic12f1840.h: 1314: unsigned TUN0 :1;
+[; ;pic12f1840.h: 1315: unsigned TUN1 :1;
+[; ;pic12f1840.h: 1316: unsigned TUN2 :1;
+[; ;pic12f1840.h: 1317: unsigned TUN3 :1;
+[; ;pic12f1840.h: 1318: unsigned TUN4 :1;
+[; ;pic12f1840.h: 1319: unsigned TUN5 :1;
+[; ;pic12f1840.h: 1320: };
+[; ;pic12f1840.h: 1321: struct {
+[; ;pic12f1840.h: 1322: unsigned TUN :6;
+[; ;pic12f1840.h: 1323: };
+[; ;pic12f1840.h: 1324: } OSCTUNEbits_t;
+[; ;pic12f1840.h: 1325: extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+[; ;pic12f1840.h: 1364: extern volatile unsigned char OSCCON @ 0x099;
+"1366
+[; ;pic12f1840.h: 1366: asm("OSCCON equ 099h");
+[; <" OSCCON equ 099h ;# ">
+[; ;pic12f1840.h: 1369: typedef union {
+[; ;pic12f1840.h: 1370: struct {
+[; ;pic12f1840.h: 1371: unsigned SCS0 :1;
+[; ;pic12f1840.h: 1372: unsigned SCS1 :1;
+[; ;pic12f1840.h: 1373: unsigned :1;
+[; ;pic12f1840.h: 1374: unsigned IRCF0 :1;
+[; ;pic12f1840.h: 1375: unsigned IRCF1 :1;
+[; ;pic12f1840.h: 1376: unsigned IRCF2 :1;
+[; ;pic12f1840.h: 1377: unsigned IRCF3 :1;
+[; ;pic12f1840.h: 1378: unsigned SPLLEN :1;
+[; ;pic12f1840.h: 1379: };
+[; ;pic12f1840.h: 1380: struct {
+[; ;pic12f1840.h: 1381: unsigned SCS :2;
+[; ;pic12f1840.h: 1382: unsigned :1;
+[; ;pic12f1840.h: 1383: unsigned IRCF :4;
+[; ;pic12f1840.h: 1384: };
+[; ;pic12f1840.h: 1385: } OSCCONbits_t;
+[; ;pic12f1840.h: 1386: extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+[; ;pic12f1840.h: 1435: extern volatile unsigned char OSCSTAT @ 0x09A;
+"1437
+[; ;pic12f1840.h: 1437: asm("OSCSTAT equ 09Ah");
+[; <" OSCSTAT equ 09Ah ;# ">
+[; ;pic12f1840.h: 1440: typedef union {
+[; ;pic12f1840.h: 1441: struct {
+[; ;pic12f1840.h: 1442: unsigned HFIOFS :1;
+[; ;pic12f1840.h: 1443: unsigned LFIOFR :1;
+[; ;pic12f1840.h: 1444: unsigned MFIOFR :1;
+[; ;pic12f1840.h: 1445: unsigned HFIOFL :1;
+[; ;pic12f1840.h: 1446: unsigned HFIOFR :1;
+[; ;pic12f1840.h: 1447: unsigned OSTS :1;
+[; ;pic12f1840.h: 1448: unsigned PLLR :1;
+[; ;pic12f1840.h: 1449: unsigned T1OSCR :1;
+[; ;pic12f1840.h: 1450: };
+[; ;pic12f1840.h: 1451: } OSCSTATbits_t;
+[; ;pic12f1840.h: 1452: extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+[; ;pic12f1840.h: 1496: extern volatile unsigned short ADRES @ 0x09B;
+"1498
+[; ;pic12f1840.h: 1498: asm("ADRES equ 09Bh");
+[; <" ADRES equ 09Bh ;# ">
+[; ;pic12f1840.h: 1502: extern volatile unsigned char ADRESL @ 0x09B;
+"1504
+[; ;pic12f1840.h: 1504: asm("ADRESL equ 09Bh");
+[; <" ADRESL equ 09Bh ;# ">
+[; ;pic12f1840.h: 1507: typedef union {
+[; ;pic12f1840.h: 1508: struct {
+[; ;pic12f1840.h: 1509: unsigned ADRESL :8;
+[; ;pic12f1840.h: 1510: };
+[; ;pic12f1840.h: 1511: } ADRESLbits_t;
+[; ;pic12f1840.h: 1512: extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+[; ;pic12f1840.h: 1521: extern volatile unsigned char ADRESH @ 0x09C;
+"1523
+[; ;pic12f1840.h: 1523: asm("ADRESH equ 09Ch");
+[; <" ADRESH equ 09Ch ;# ">
+[; ;pic12f1840.h: 1526: typedef union {
+[; ;pic12f1840.h: 1527: struct {
+[; ;pic12f1840.h: 1528: unsigned ADRESH :8;
+[; ;pic12f1840.h: 1529: };
+[; ;pic12f1840.h: 1530: } ADRESHbits_t;
+[; ;pic12f1840.h: 1531: extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+[; ;pic12f1840.h: 1540: extern volatile unsigned char ADCON0 @ 0x09D;
+"1542
+[; ;pic12f1840.h: 1542: asm("ADCON0 equ 09Dh");
+[; <" ADCON0 equ 09Dh ;# ">
+[; ;pic12f1840.h: 1545: typedef union {
+[; ;pic12f1840.h: 1546: struct {
+[; ;pic12f1840.h: 1547: unsigned ADON :1;
+[; ;pic12f1840.h: 1548: unsigned GO_nDONE :1;
+[; ;pic12f1840.h: 1549: unsigned CHS0 :1;
+[; ;pic12f1840.h: 1550: unsigned CHS1 :1;
+[; ;pic12f1840.h: 1551: unsigned CHS2 :1;
+[; ;pic12f1840.h: 1552: unsigned CHS3 :1;
+[; ;pic12f1840.h: 1553: unsigned CHS4 :1;
+[; ;pic12f1840.h: 1554: };
+[; ;pic12f1840.h: 1555: struct {
+[; ;pic12f1840.h: 1556: unsigned :1;
+[; ;pic12f1840.h: 1557: unsigned ADGO :1;
+[; ;pic12f1840.h: 1558: unsigned CHS :5;
+[; ;pic12f1840.h: 1559: };
+[; ;pic12f1840.h: 1560: struct {
+[; ;pic12f1840.h: 1561: unsigned :1;
+[; ;pic12f1840.h: 1562: unsigned GO :1;
+[; ;pic12f1840.h: 1563: };
+[; ;pic12f1840.h: 1564: } ADCON0bits_t;
+[; ;pic12f1840.h: 1565: extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+[; ;pic12f1840.h: 1619: extern volatile unsigned char ADCON1 @ 0x09E;
+"1621
+[; ;pic12f1840.h: 1621: asm("ADCON1 equ 09Eh");
+[; <" ADCON1 equ 09Eh ;# ">
+[; ;pic12f1840.h: 1624: typedef union {
+[; ;pic12f1840.h: 1625: struct {
+[; ;pic12f1840.h: 1626: unsigned ADPREF0 :1;
+[; ;pic12f1840.h: 1627: unsigned ADPREF1 :1;
+[; ;pic12f1840.h: 1628: unsigned :2;
+[; ;pic12f1840.h: 1629: unsigned ADCS0 :1;
+[; ;pic12f1840.h: 1630: unsigned ADCS1 :1;
+[; ;pic12f1840.h: 1631: unsigned ADCS2 :1;
+[; ;pic12f1840.h: 1632: unsigned ADFM :1;
+[; ;pic12f1840.h: 1633: };
+[; ;pic12f1840.h: 1634: struct {
+[; ;pic12f1840.h: 1635: unsigned ADPREF :2;
+[; ;pic12f1840.h: 1636: unsigned :2;
+[; ;pic12f1840.h: 1637: unsigned ADCS :3;
+[; ;pic12f1840.h: 1638: };
+[; ;pic12f1840.h: 1639: } ADCON1bits_t;
+[; ;pic12f1840.h: 1640: extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+[; ;pic12f1840.h: 1684: extern volatile unsigned char LATA @ 0x10C;
+"1686
+[; ;pic12f1840.h: 1686: asm("LATA equ 010Ch");
+[; <" LATA equ 010Ch ;# ">
+[; ;pic12f1840.h: 1689: typedef union {
+[; ;pic12f1840.h: 1690: struct {
+[; ;pic12f1840.h: 1691: unsigned LATA0 :1;
+[; ;pic12f1840.h: 1692: unsigned LATA1 :1;
+[; ;pic12f1840.h: 1693: unsigned LATA2 :1;
+[; ;pic12f1840.h: 1694: unsigned :1;
+[; ;pic12f1840.h: 1695: unsigned LATA4 :1;
+[; ;pic12f1840.h: 1696: unsigned LATA5 :1;
+[; ;pic12f1840.h: 1697: };
+[; ;pic12f1840.h: 1698: } LATAbits_t;
+[; ;pic12f1840.h: 1699: extern volatile LATAbits_t LATAbits @ 0x10C;
+[; ;pic12f1840.h: 1728: extern volatile unsigned char CM1CON0 @ 0x111;
+"1730
+[; ;pic12f1840.h: 1730: asm("CM1CON0 equ 0111h");
+[; <" CM1CON0 equ 0111h ;# ">
+[; ;pic12f1840.h: 1733: typedef union {
+[; ;pic12f1840.h: 1734: struct {
+[; ;pic12f1840.h: 1735: unsigned C1SYNC :1;
+[; ;pic12f1840.h: 1736: unsigned C1HYS :1;
+[; ;pic12f1840.h: 1737: unsigned C1SP :1;
+[; ;pic12f1840.h: 1738: unsigned :1;
+[; ;pic12f1840.h: 1739: unsigned C1POL :1;
+[; ;pic12f1840.h: 1740: unsigned C1OE :1;
+[; ;pic12f1840.h: 1741: unsigned C1OUT :1;
+[; ;pic12f1840.h: 1742: unsigned C1ON :1;
+[; ;pic12f1840.h: 1743: };
+[; ;pic12f1840.h: 1744: } CM1CON0bits_t;
+[; ;pic12f1840.h: 1745: extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+[; ;pic12f1840.h: 1784: extern volatile unsigned char CM1CON1 @ 0x112;
+"1786
+[; ;pic12f1840.h: 1786: asm("CM1CON1 equ 0112h");
+[; <" CM1CON1 equ 0112h ;# ">
+[; ;pic12f1840.h: 1789: typedef union {
+[; ;pic12f1840.h: 1790: struct {
+[; ;pic12f1840.h: 1791: unsigned C1NCH :1;
+[; ;pic12f1840.h: 1792: unsigned :3;
+[; ;pic12f1840.h: 1793: unsigned C1PCH0 :1;
+[; ;pic12f1840.h: 1794: unsigned C1PCH1 :1;
+[; ;pic12f1840.h: 1795: unsigned C1INTN :1;
+[; ;pic12f1840.h: 1796: unsigned C1INTP :1;
+[; ;pic12f1840.h: 1797: };
+[; ;pic12f1840.h: 1798: struct {
+[; ;pic12f1840.h: 1799: unsigned C1NCH0 :1;
+[; ;pic12f1840.h: 1800: unsigned :3;
+[; ;pic12f1840.h: 1801: unsigned C1PCH :2;
+[; ;pic12f1840.h: 1802: };
+[; ;pic12f1840.h: 1803: } CM1CON1bits_t;
+[; ;pic12f1840.h: 1804: extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+[; ;pic12f1840.h: 1843: extern volatile unsigned char CMOUT @ 0x115;
+"1845
+[; ;pic12f1840.h: 1845: asm("CMOUT equ 0115h");
+[; <" CMOUT equ 0115h ;# ">
+[; ;pic12f1840.h: 1848: typedef union {
+[; ;pic12f1840.h: 1849: struct {
+[; ;pic12f1840.h: 1850: unsigned MC1OUT :1;
+[; ;pic12f1840.h: 1851: };
+[; ;pic12f1840.h: 1852: } CMOUTbits_t;
+[; ;pic12f1840.h: 1853: extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+[; ;pic12f1840.h: 1862: extern volatile unsigned char BORCON @ 0x116;
+"1864
+[; ;pic12f1840.h: 1864: asm("BORCON equ 0116h");
+[; <" BORCON equ 0116h ;# ">
+[; ;pic12f1840.h: 1867: typedef union {
+[; ;pic12f1840.h: 1868: struct {
+[; ;pic12f1840.h: 1869: unsigned BORRDY :1;
+[; ;pic12f1840.h: 1870: unsigned :5;
+[; ;pic12f1840.h: 1871: unsigned BORFS :1;
+[; ;pic12f1840.h: 1872: unsigned SBOREN :1;
+[; ;pic12f1840.h: 1873: };
+[; ;pic12f1840.h: 1874: } BORCONbits_t;
+[; ;pic12f1840.h: 1875: extern volatile BORCONbits_t BORCONbits @ 0x116;
+[; ;pic12f1840.h: 1894: extern volatile unsigned char FVRCON @ 0x117;
+"1896
+[; ;pic12f1840.h: 1896: asm("FVRCON equ 0117h");
+[; <" FVRCON equ 0117h ;# ">
+[; ;pic12f1840.h: 1899: typedef union {
+[; ;pic12f1840.h: 1900: struct {
+[; ;pic12f1840.h: 1901: unsigned ADFVR0 :1;
+[; ;pic12f1840.h: 1902: unsigned ADFVR1 :1;
+[; ;pic12f1840.h: 1903: unsigned CDAFVR0 :1;
+[; ;pic12f1840.h: 1904: unsigned CDAFVR1 :1;
+[; ;pic12f1840.h: 1905: unsigned TSRNG :1;
+[; ;pic12f1840.h: 1906: unsigned TSEN :1;
+[; ;pic12f1840.h: 1907: unsigned FVRRDY :1;
+[; ;pic12f1840.h: 1908: unsigned FVREN :1;
+[; ;pic12f1840.h: 1909: };
+[; ;pic12f1840.h: 1910: struct {
+[; ;pic12f1840.h: 1911: unsigned ADFVR :2;
+[; ;pic12f1840.h: 1912: unsigned CDAFVR :2;
+[; ;pic12f1840.h: 1913: };
+[; ;pic12f1840.h: 1914: } FVRCONbits_t;
+[; ;pic12f1840.h: 1915: extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+[; ;pic12f1840.h: 1969: extern volatile unsigned char DACCON0 @ 0x118;
+"1971
+[; ;pic12f1840.h: 1971: asm("DACCON0 equ 0118h");
+[; <" DACCON0 equ 0118h ;# ">
+[; ;pic12f1840.h: 1974: typedef union {
+[; ;pic12f1840.h: 1975: struct {
+[; ;pic12f1840.h: 1976: unsigned :2;
+[; ;pic12f1840.h: 1977: unsigned DACPSS0 :1;
+[; ;pic12f1840.h: 1978: unsigned DACPSS1 :1;
+[; ;pic12f1840.h: 1979: unsigned :1;
+[; ;pic12f1840.h: 1980: unsigned DACOE :1;
+[; ;pic12f1840.h: 1981: unsigned DACLPS :1;
+[; ;pic12f1840.h: 1982: unsigned DACEN :1;
+[; ;pic12f1840.h: 1983: };
+[; ;pic12f1840.h: 1984: struct {
+[; ;pic12f1840.h: 1985: unsigned :2;
+[; ;pic12f1840.h: 1986: unsigned DACPSS :2;
+[; ;pic12f1840.h: 1987: };
+[; ;pic12f1840.h: 1988: } DACCON0bits_t;
+[; ;pic12f1840.h: 1989: extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+[; ;pic12f1840.h: 2023: extern volatile unsigned char DACCON1 @ 0x119;
+"2025
+[; ;pic12f1840.h: 2025: asm("DACCON1 equ 0119h");
+[; <" DACCON1 equ 0119h ;# ">
+[; ;pic12f1840.h: 2028: typedef union {
+[; ;pic12f1840.h: 2029: struct {
+[; ;pic12f1840.h: 2030: unsigned DACR0 :1;
+[; ;pic12f1840.h: 2031: unsigned DACR1 :1;
+[; ;pic12f1840.h: 2032: unsigned DACR2 :1;
+[; ;pic12f1840.h: 2033: unsigned DACR3 :1;
+[; ;pic12f1840.h: 2034: unsigned DACR4 :1;
+[; ;pic12f1840.h: 2035: };
+[; ;pic12f1840.h: 2036: struct {
+[; ;pic12f1840.h: 2037: unsigned DACR :5;
+[; ;pic12f1840.h: 2038: };
+[; ;pic12f1840.h: 2039: } DACCON1bits_t;
+[; ;pic12f1840.h: 2040: extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+[; ;pic12f1840.h: 2074: extern volatile unsigned char SRCON0 @ 0x11A;
+"2076
+[; ;pic12f1840.h: 2076: asm("SRCON0 equ 011Ah");
+[; <" SRCON0 equ 011Ah ;# ">
+[; ;pic12f1840.h: 2079: typedef union {
+[; ;pic12f1840.h: 2080: struct {
+[; ;pic12f1840.h: 2081: unsigned SRPR :1;
+[; ;pic12f1840.h: 2082: unsigned SRPS :1;
+[; ;pic12f1840.h: 2083: unsigned SRNQEN :1;
+[; ;pic12f1840.h: 2084: unsigned SRQEN :1;
+[; ;pic12f1840.h: 2085: unsigned SRCLK0 :1;
+[; ;pic12f1840.h: 2086: unsigned SRCLK1 :1;
+[; ;pic12f1840.h: 2087: unsigned SRCLK2 :1;
+[; ;pic12f1840.h: 2088: unsigned SRLEN :1;
+[; ;pic12f1840.h: 2089: };
+[; ;pic12f1840.h: 2090: struct {
+[; ;pic12f1840.h: 2091: unsigned :4;
+[; ;pic12f1840.h: 2092: unsigned SRCLK :3;
+[; ;pic12f1840.h: 2093: };
+[; ;pic12f1840.h: 2094: } SRCON0bits_t;
+[; ;pic12f1840.h: 2095: extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+[; ;pic12f1840.h: 2144: extern volatile unsigned char SRCON1 @ 0x11B;
+"2146
+[; ;pic12f1840.h: 2146: asm("SRCON1 equ 011Bh");
+[; <" SRCON1 equ 011Bh ;# ">
+[; ;pic12f1840.h: 2149: typedef union {
+[; ;pic12f1840.h: 2150: struct {
+[; ;pic12f1840.h: 2151: unsigned SRRC1E :1;
+[; ;pic12f1840.h: 2152: unsigned :1;
+[; ;pic12f1840.h: 2153: unsigned SRRCKE :1;
+[; ;pic12f1840.h: 2154: unsigned SRRPE :1;
+[; ;pic12f1840.h: 2155: unsigned SRSC1E :1;
+[; ;pic12f1840.h: 2156: unsigned :1;
+[; ;pic12f1840.h: 2157: unsigned SRSCKE :1;
+[; ;pic12f1840.h: 2158: unsigned SRSPE :1;
+[; ;pic12f1840.h: 2159: };
+[; ;pic12f1840.h: 2160: } SRCON1bits_t;
+[; ;pic12f1840.h: 2161: extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+[; ;pic12f1840.h: 2195: extern volatile unsigned char APFCON @ 0x11D;
+"2197
+[; ;pic12f1840.h: 2197: asm("APFCON equ 011Dh");
+[; <" APFCON equ 011Dh ;# ">
+[; ;pic12f1840.h: 2200: extern volatile unsigned char APFCON0 @ 0x11D;
+"2202
+[; ;pic12f1840.h: 2202: asm("APFCON0 equ 011Dh");
+[; <" APFCON0 equ 011Dh ;# ">
+[; ;pic12f1840.h: 2205: typedef union {
+[; ;pic12f1840.h: 2206: struct {
+[; ;pic12f1840.h: 2207: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2208: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2209: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2210: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2211: unsigned :1;
+[; ;pic12f1840.h: 2212: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2213: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2214: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2215: };
+[; ;pic12f1840.h: 2216: struct {
+[; ;pic12f1840.h: 2217: unsigned :5;
+[; ;pic12f1840.h: 2218: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2219: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2220: };
+[; ;pic12f1840.h: 2221: } APFCONbits_t;
+[; ;pic12f1840.h: 2222: extern volatile APFCONbits_t APFCONbits @ 0x11D;
+[; ;pic12f1840.h: 2270: typedef union {
+[; ;pic12f1840.h: 2271: struct {
+[; ;pic12f1840.h: 2272: unsigned CCP1SEL :1;
+[; ;pic12f1840.h: 2273: unsigned P1BSEL :1;
+[; ;pic12f1840.h: 2274: unsigned TXCKSEL :1;
+[; ;pic12f1840.h: 2275: unsigned T1GSEL :1;
+[; ;pic12f1840.h: 2276: unsigned :1;
+[; ;pic12f1840.h: 2277: unsigned SSSEL :1;
+[; ;pic12f1840.h: 2278: unsigned SDOSEL :1;
+[; ;pic12f1840.h: 2279: unsigned RXDTSEL :1;
+[; ;pic12f1840.h: 2280: };
+[; ;pic12f1840.h: 2281: struct {
+[; ;pic12f1840.h: 2282: unsigned :5;
+[; ;pic12f1840.h: 2283: unsigned SS1SEL :1;
+[; ;pic12f1840.h: 2284: unsigned SDO1SEL :1;
+[; ;pic12f1840.h: 2285: };
+[; ;pic12f1840.h: 2286: } APFCON0bits_t;
+[; ;pic12f1840.h: 2287: extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+[; ;pic12f1840.h: 2336: extern volatile unsigned char ANSELA @ 0x18C;
+"2338
+[; ;pic12f1840.h: 2338: asm("ANSELA equ 018Ch");
+[; <" ANSELA equ 018Ch ;# ">
+[; ;pic12f1840.h: 2341: typedef union {
+[; ;pic12f1840.h: 2342: struct {
+[; ;pic12f1840.h: 2343: unsigned ANSA0 :1;
+[; ;pic12f1840.h: 2344: unsigned ANSA1 :1;
+[; ;pic12f1840.h: 2345: unsigned ANSA2 :1;
+[; ;pic12f1840.h: 2346: unsigned :1;
+[; ;pic12f1840.h: 2347: unsigned ANSA4 :1;
+[; ;pic12f1840.h: 2348: };
+[; ;pic12f1840.h: 2349: struct {
+[; ;pic12f1840.h: 2350: unsigned ANSELA :5;
+[; ;pic12f1840.h: 2351: };
+[; ;pic12f1840.h: 2352: } ANSELAbits_t;
+[; ;pic12f1840.h: 2353: extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+[; ;pic12f1840.h: 2382: extern volatile unsigned short EEADR @ 0x191;
+"2384
+[; ;pic12f1840.h: 2384: asm("EEADR equ 0191h");
+[; <" EEADR equ 0191h ;# ">
+[; ;pic12f1840.h: 2388: extern volatile unsigned char EEADRL @ 0x191;
+"2390
+[; ;pic12f1840.h: 2390: asm("EEADRL equ 0191h");
+[; <" EEADRL equ 0191h ;# ">
+[; ;pic12f1840.h: 2393: typedef union {
+[; ;pic12f1840.h: 2394: struct {
+[; ;pic12f1840.h: 2395: unsigned EEADRL :8;
+[; ;pic12f1840.h: 2396: };
+[; ;pic12f1840.h: 2397: } EEADRLbits_t;
+[; ;pic12f1840.h: 2398: extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+[; ;pic12f1840.h: 2407: extern volatile unsigned char EEADRH @ 0x192;
+"2409
+[; ;pic12f1840.h: 2409: asm("EEADRH equ 0192h");
+[; <" EEADRH equ 0192h ;# ">
+[; ;pic12f1840.h: 2412: typedef union {
+[; ;pic12f1840.h: 2413: struct {
+[; ;pic12f1840.h: 2414: unsigned EEADRH :7;
+[; ;pic12f1840.h: 2415: };
+[; ;pic12f1840.h: 2416: } EEADRHbits_t;
+[; ;pic12f1840.h: 2417: extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+[; ;pic12f1840.h: 2426: extern volatile unsigned short EEDAT @ 0x193;
+"2428
+[; ;pic12f1840.h: 2428: asm("EEDAT equ 0193h");
+[; <" EEDAT equ 0193h ;# ">
+[; ;pic12f1840.h: 2432: extern volatile unsigned char EEDATL @ 0x193;
+"2434
+[; ;pic12f1840.h: 2434: asm("EEDATL equ 0193h");
+[; <" EEDATL equ 0193h ;# ">
+[; ;pic12f1840.h: 2437: extern volatile unsigned char EEDATA @ 0x193;
+"2439
+[; ;pic12f1840.h: 2439: asm("EEDATA equ 0193h");
+[; <" EEDATA equ 0193h ;# ">
+[; ;pic12f1840.h: 2442: typedef union {
+[; ;pic12f1840.h: 2443: struct {
+[; ;pic12f1840.h: 2444: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2445: };
+[; ;pic12f1840.h: 2446: } EEDATLbits_t;
+[; ;pic12f1840.h: 2447: extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+[; ;pic12f1840.h: 2455: typedef union {
+[; ;pic12f1840.h: 2456: struct {
+[; ;pic12f1840.h: 2457: unsigned EEDATL :8;
+[; ;pic12f1840.h: 2458: };
+[; ;pic12f1840.h: 2459: } EEDATAbits_t;
+[; ;pic12f1840.h: 2460: extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+[; ;pic12f1840.h: 2469: extern volatile unsigned char EEDATH @ 0x194;
+"2471
+[; ;pic12f1840.h: 2471: asm("EEDATH equ 0194h");
+[; <" EEDATH equ 0194h ;# ">
+[; ;pic12f1840.h: 2474: typedef union {
+[; ;pic12f1840.h: 2475: struct {
+[; ;pic12f1840.h: 2476: unsigned EEDATH :6;
+[; ;pic12f1840.h: 2477: };
+[; ;pic12f1840.h: 2478: } EEDATHbits_t;
+[; ;pic12f1840.h: 2479: extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+[; ;pic12f1840.h: 2488: extern volatile unsigned char EECON1 @ 0x195;
+"2490
+[; ;pic12f1840.h: 2490: asm("EECON1 equ 0195h");
+[; <" EECON1 equ 0195h ;# ">
+[; ;pic12f1840.h: 2493: typedef union {
+[; ;pic12f1840.h: 2494: struct {
+[; ;pic12f1840.h: 2495: unsigned RD :1;
+[; ;pic12f1840.h: 2496: unsigned WR :1;
+[; ;pic12f1840.h: 2497: unsigned WREN :1;
+[; ;pic12f1840.h: 2498: unsigned WRERR :1;
+[; ;pic12f1840.h: 2499: unsigned FREE :1;
+[; ;pic12f1840.h: 2500: unsigned LWLO :1;
+[; ;pic12f1840.h: 2501: unsigned CFGS :1;
+[; ;pic12f1840.h: 2502: unsigned EEPGD :1;
+[; ;pic12f1840.h: 2503: };
+[; ;pic12f1840.h: 2504: } EECON1bits_t;
+[; ;pic12f1840.h: 2505: extern volatile EECON1bits_t EECON1bits @ 0x195;
+[; ;pic12f1840.h: 2549: extern volatile unsigned char EECON2 @ 0x196;
+"2551
+[; ;pic12f1840.h: 2551: asm("EECON2 equ 0196h");
+[; <" EECON2 equ 0196h ;# ">
+[; ;pic12f1840.h: 2554: typedef union {
+[; ;pic12f1840.h: 2555: struct {
+[; ;pic12f1840.h: 2556: unsigned EECON2 :8;
+[; ;pic12f1840.h: 2557: };
+[; ;pic12f1840.h: 2558: } EECON2bits_t;
+[; ;pic12f1840.h: 2559: extern volatile EECON2bits_t EECON2bits @ 0x196;
+[; ;pic12f1840.h: 2568: extern volatile unsigned char VREGCON @ 0x197;
+"2570
+[; ;pic12f1840.h: 2570: asm("VREGCON equ 0197h");
+[; <" VREGCON equ 0197h ;# ">
+[; ;pic12f1840.h: 2573: typedef union {
+[; ;pic12f1840.h: 2574: struct {
+[; ;pic12f1840.h: 2575: unsigned VREGPM0 :1;
+[; ;pic12f1840.h: 2576: unsigned VREGPM1 :1;
+[; ;pic12f1840.h: 2577: };
+[; ;pic12f1840.h: 2578: struct {
+[; ;pic12f1840.h: 2579: unsigned VREGPM :2;
+[; ;pic12f1840.h: 2580: };
+[; ;pic12f1840.h: 2581: } VREGCONbits_t;
+[; ;pic12f1840.h: 2582: extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+[; ;pic12f1840.h: 2601: extern volatile unsigned char RCREG @ 0x199;
+"2603
+[; ;pic12f1840.h: 2603: asm("RCREG equ 0199h");
+[; <" RCREG equ 0199h ;# ">
+[; ;pic12f1840.h: 2606: typedef union {
+[; ;pic12f1840.h: 2607: struct {
+[; ;pic12f1840.h: 2608: unsigned RCREG :8;
+[; ;pic12f1840.h: 2609: };
+[; ;pic12f1840.h: 2610: } RCREGbits_t;
+[; ;pic12f1840.h: 2611: extern volatile RCREGbits_t RCREGbits @ 0x199;
+[; ;pic12f1840.h: 2620: extern volatile unsigned char TXREG @ 0x19A;
+"2622
+[; ;pic12f1840.h: 2622: asm("TXREG equ 019Ah");
+[; <" TXREG equ 019Ah ;# ">
+[; ;pic12f1840.h: 2625: typedef union {
+[; ;pic12f1840.h: 2626: struct {
+[; ;pic12f1840.h: 2627: unsigned TXREG :8;
+[; ;pic12f1840.h: 2628: };
+[; ;pic12f1840.h: 2629: } TXREGbits_t;
+[; ;pic12f1840.h: 2630: extern volatile TXREGbits_t TXREGbits @ 0x19A;
+[; ;pic12f1840.h: 2639: extern volatile unsigned char SPBRGL @ 0x19B;
+"2641
+[; ;pic12f1840.h: 2641: asm("SPBRGL equ 019Bh");
+[; <" SPBRGL equ 019Bh ;# ">
+[; ;pic12f1840.h: 2644: extern volatile unsigned char SPBRG @ 0x19B;
+"2646
+[; ;pic12f1840.h: 2646: asm("SPBRG equ 019Bh");
+[; <" SPBRG equ 019Bh ;# ">
+[; ;pic12f1840.h: 2649: typedef union {
+[; ;pic12f1840.h: 2650: struct {
+[; ;pic12f1840.h: 2651: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2652: };
+[; ;pic12f1840.h: 2653: } SPBRGLbits_t;
+[; ;pic12f1840.h: 2654: extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+[; ;pic12f1840.h: 2662: typedef union {
+[; ;pic12f1840.h: 2663: struct {
+[; ;pic12f1840.h: 2664: unsigned SPBRGL :8;
+[; ;pic12f1840.h: 2665: };
+[; ;pic12f1840.h: 2666: } SPBRGbits_t;
+[; ;pic12f1840.h: 2667: extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+[; ;pic12f1840.h: 2676: extern volatile unsigned char SPBRGH @ 0x19C;
+"2678
+[; ;pic12f1840.h: 2678: asm("SPBRGH equ 019Ch");
+[; <" SPBRGH equ 019Ch ;# ">
+[; ;pic12f1840.h: 2681: typedef union {
+[; ;pic12f1840.h: 2682: struct {
+[; ;pic12f1840.h: 2683: unsigned SPBRGH :8;
+[; ;pic12f1840.h: 2684: };
+[; ;pic12f1840.h: 2685: } SPBRGHbits_t;
+[; ;pic12f1840.h: 2686: extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+[; ;pic12f1840.h: 2695: extern volatile unsigned char RCSTA @ 0x19D;
+"2697
+[; ;pic12f1840.h: 2697: asm("RCSTA equ 019Dh");
+[; <" RCSTA equ 019Dh ;# ">
+[; ;pic12f1840.h: 2700: typedef union {
+[; ;pic12f1840.h: 2701: struct {
+[; ;pic12f1840.h: 2702: unsigned RX9D :1;
+[; ;pic12f1840.h: 2703: unsigned OERR :1;
+[; ;pic12f1840.h: 2704: unsigned FERR :1;
+[; ;pic12f1840.h: 2705: unsigned ADDEN :1;
+[; ;pic12f1840.h: 2706: unsigned CREN :1;
+[; ;pic12f1840.h: 2707: unsigned SREN :1;
+[; ;pic12f1840.h: 2708: unsigned RX9 :1;
+[; ;pic12f1840.h: 2709: unsigned SPEN :1;
+[; ;pic12f1840.h: 2710: };
+[; ;pic12f1840.h: 2711: } RCSTAbits_t;
+[; ;pic12f1840.h: 2712: extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+[; ;pic12f1840.h: 2756: extern volatile unsigned char TXSTA @ 0x19E;
+"2758
+[; ;pic12f1840.h: 2758: asm("TXSTA equ 019Eh");
+[; <" TXSTA equ 019Eh ;# ">
+[; ;pic12f1840.h: 2761: typedef union {
+[; ;pic12f1840.h: 2762: struct {
+[; ;pic12f1840.h: 2763: unsigned TX9D :1;
+[; ;pic12f1840.h: 2764: unsigned TRMT :1;
+[; ;pic12f1840.h: 2765: unsigned BRGH :1;
+[; ;pic12f1840.h: 2766: unsigned SENDB :1;
+[; ;pic12f1840.h: 2767: unsigned SYNC :1;
+[; ;pic12f1840.h: 2768: unsigned TXEN :1;
+[; ;pic12f1840.h: 2769: unsigned TX9 :1;
+[; ;pic12f1840.h: 2770: unsigned CSRC :1;
+[; ;pic12f1840.h: 2771: };
+[; ;pic12f1840.h: 2772: } TXSTAbits_t;
+[; ;pic12f1840.h: 2773: extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+[; ;pic12f1840.h: 2817: extern volatile unsigned char BAUDCON @ 0x19F;
+"2819
+[; ;pic12f1840.h: 2819: asm("BAUDCON equ 019Fh");
+[; <" BAUDCON equ 019Fh ;# ">
+[; ;pic12f1840.h: 2822: typedef union {
+[; ;pic12f1840.h: 2823: struct {
+[; ;pic12f1840.h: 2824: unsigned ABDEN :1;
+[; ;pic12f1840.h: 2825: unsigned WUE :1;
+[; ;pic12f1840.h: 2826: unsigned :1;
+[; ;pic12f1840.h: 2827: unsigned BRG16 :1;
+[; ;pic12f1840.h: 2828: unsigned SCKP :1;
+[; ;pic12f1840.h: 2829: unsigned :1;
+[; ;pic12f1840.h: 2830: unsigned RCIDL :1;
+[; ;pic12f1840.h: 2831: unsigned ABDOVF :1;
+[; ;pic12f1840.h: 2832: };
+[; ;pic12f1840.h: 2833: } BAUDCONbits_t;
+[; ;pic12f1840.h: 2834: extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+[; ;pic12f1840.h: 2868: extern volatile unsigned char WPUA @ 0x20C;
+"2870
+[; ;pic12f1840.h: 2870: asm("WPUA equ 020Ch");
+[; <" WPUA equ 020Ch ;# ">
+[; ;pic12f1840.h: 2873: typedef union {
+[; ;pic12f1840.h: 2874: struct {
+[; ;pic12f1840.h: 2875: unsigned WPUA0 :1;
+[; ;pic12f1840.h: 2876: unsigned WPUA1 :1;
+[; ;pic12f1840.h: 2877: unsigned WPUA2 :1;
+[; ;pic12f1840.h: 2878: unsigned WPUA3 :1;
+[; ;pic12f1840.h: 2879: unsigned WPUA4 :1;
+[; ;pic12f1840.h: 2880: unsigned WPUA5 :1;
+[; ;pic12f1840.h: 2881: };
+[; ;pic12f1840.h: 2882: struct {
+[; ;pic12f1840.h: 2883: unsigned WPUA :6;
+[; ;pic12f1840.h: 2884: };
+[; ;pic12f1840.h: 2885: } WPUAbits_t;
+[; ;pic12f1840.h: 2886: extern volatile WPUAbits_t WPUAbits @ 0x20C;
+[; ;pic12f1840.h: 2925: extern volatile unsigned char SSP1BUF @ 0x211;
+"2927
+[; ;pic12f1840.h: 2927: asm("SSP1BUF equ 0211h");
+[; <" SSP1BUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2930: extern volatile unsigned char SSPBUF @ 0x211;
+"2932
+[; ;pic12f1840.h: 2932: asm("SSPBUF equ 0211h");
+[; <" SSPBUF equ 0211h ;# ">
+[; ;pic12f1840.h: 2935: typedef union {
+[; ;pic12f1840.h: 2936: struct {
+[; ;pic12f1840.h: 2937: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2938: };
+[; ;pic12f1840.h: 2939: } SSP1BUFbits_t;
+[; ;pic12f1840.h: 2940: extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+[; ;pic12f1840.h: 2948: typedef union {
+[; ;pic12f1840.h: 2949: struct {
+[; ;pic12f1840.h: 2950: unsigned SSPBUF :8;
+[; ;pic12f1840.h: 2951: };
+[; ;pic12f1840.h: 2952: } SSPBUFbits_t;
+[; ;pic12f1840.h: 2953: extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+[; ;pic12f1840.h: 2962: extern volatile unsigned char SSP1ADD @ 0x212;
+"2964
+[; ;pic12f1840.h: 2964: asm("SSP1ADD equ 0212h");
+[; <" SSP1ADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2967: extern volatile unsigned char SSPADD @ 0x212;
+"2969
+[; ;pic12f1840.h: 2969: asm("SSPADD equ 0212h");
+[; <" SSPADD equ 0212h ;# ">
+[; ;pic12f1840.h: 2972: typedef union {
+[; ;pic12f1840.h: 2973: struct {
+[; ;pic12f1840.h: 2974: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2975: };
+[; ;pic12f1840.h: 2976: } SSP1ADDbits_t;
+[; ;pic12f1840.h: 2977: extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+[; ;pic12f1840.h: 2985: typedef union {
+[; ;pic12f1840.h: 2986: struct {
+[; ;pic12f1840.h: 2987: unsigned SSPADD :8;
+[; ;pic12f1840.h: 2988: };
+[; ;pic12f1840.h: 2989: } SSPADDbits_t;
+[; ;pic12f1840.h: 2990: extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+[; ;pic12f1840.h: 2999: extern volatile unsigned char SSP1MSK @ 0x213;
+"3001
+[; ;pic12f1840.h: 3001: asm("SSP1MSK equ 0213h");
+[; <" SSP1MSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3004: extern volatile unsigned char SSPMSK @ 0x213;
+"3006
+[; ;pic12f1840.h: 3006: asm("SSPMSK equ 0213h");
+[; <" SSPMSK equ 0213h ;# ">
+[; ;pic12f1840.h: 3009: typedef union {
+[; ;pic12f1840.h: 3010: struct {
+[; ;pic12f1840.h: 3011: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3012: };
+[; ;pic12f1840.h: 3013: } SSP1MSKbits_t;
+[; ;pic12f1840.h: 3014: extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+[; ;pic12f1840.h: 3022: typedef union {
+[; ;pic12f1840.h: 3023: struct {
+[; ;pic12f1840.h: 3024: unsigned SSPMSK :8;
+[; ;pic12f1840.h: 3025: };
+[; ;pic12f1840.h: 3026: } SSPMSKbits_t;
+[; ;pic12f1840.h: 3027: extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+[; ;pic12f1840.h: 3036: extern volatile unsigned char SSP1STAT @ 0x214;
+"3038
+[; ;pic12f1840.h: 3038: asm("SSP1STAT equ 0214h");
+[; <" SSP1STAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3041: extern volatile unsigned char SSPSTAT @ 0x214;
+"3043
+[; ;pic12f1840.h: 3043: asm("SSPSTAT equ 0214h");
+[; <" SSPSTAT equ 0214h ;# ">
+[; ;pic12f1840.h: 3046: typedef union {
+[; ;pic12f1840.h: 3047: struct {
+[; ;pic12f1840.h: 3048: unsigned BF :1;
+[; ;pic12f1840.h: 3049: unsigned UA :1;
+[; ;pic12f1840.h: 3050: unsigned R_nW :1;
+[; ;pic12f1840.h: 3051: unsigned S :1;
+[; ;pic12f1840.h: 3052: unsigned P :1;
+[; ;pic12f1840.h: 3053: unsigned D_nA :1;
+[; ;pic12f1840.h: 3054: unsigned CKE :1;
+[; ;pic12f1840.h: 3055: unsigned SMP :1;
+[; ;pic12f1840.h: 3056: };
+[; ;pic12f1840.h: 3057: } SSP1STATbits_t;
+[; ;pic12f1840.h: 3058: extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+[; ;pic12f1840.h: 3101: typedef union {
+[; ;pic12f1840.h: 3102: struct {
+[; ;pic12f1840.h: 3103: unsigned BF :1;
+[; ;pic12f1840.h: 3104: unsigned UA :1;
+[; ;pic12f1840.h: 3105: unsigned R_nW :1;
+[; ;pic12f1840.h: 3106: unsigned S :1;
+[; ;pic12f1840.h: 3107: unsigned P :1;
+[; ;pic12f1840.h: 3108: unsigned D_nA :1;
+[; ;pic12f1840.h: 3109: unsigned CKE :1;
+[; ;pic12f1840.h: 3110: unsigned SMP :1;
+[; ;pic12f1840.h: 3111: };
+[; ;pic12f1840.h: 3112: } SSPSTATbits_t;
+[; ;pic12f1840.h: 3113: extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+[; ;pic12f1840.h: 3157: extern volatile unsigned char SSP1CON1 @ 0x215;
+"3159
+[; ;pic12f1840.h: 3159: asm("SSP1CON1 equ 0215h");
+[; <" SSP1CON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3162: extern volatile unsigned char SSPCON1 @ 0x215;
+"3164
+[; ;pic12f1840.h: 3164: asm("SSPCON1 equ 0215h");
+[; <" SSPCON1 equ 0215h ;# ">
+[; ;pic12f1840.h: 3166: extern volatile unsigned char SSPCON @ 0x215;
+"3168
+[; ;pic12f1840.h: 3168: asm("SSPCON equ 0215h");
+[; <" SSPCON equ 0215h ;# ">
+[; ;pic12f1840.h: 3171: typedef union {
+[; ;pic12f1840.h: 3172: struct {
+[; ;pic12f1840.h: 3173: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3174: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3175: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3176: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3177: unsigned CKP :1;
+[; ;pic12f1840.h: 3178: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3179: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3180: unsigned WCOL :1;
+[; ;pic12f1840.h: 3181: };
+[; ;pic12f1840.h: 3182: struct {
+[; ;pic12f1840.h: 3183: unsigned SSPM :4;
+[; ;pic12f1840.h: 3184: };
+[; ;pic12f1840.h: 3185: } SSP1CON1bits_t;
+[; ;pic12f1840.h: 3186: extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+[; ;pic12f1840.h: 3234: typedef union {
+[; ;pic12f1840.h: 3235: struct {
+[; ;pic12f1840.h: 3236: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3237: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3238: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3239: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3240: unsigned CKP :1;
+[; ;pic12f1840.h: 3241: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3242: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3243: unsigned WCOL :1;
+[; ;pic12f1840.h: 3244: };
+[; ;pic12f1840.h: 3245: struct {
+[; ;pic12f1840.h: 3246: unsigned SSPM :4;
+[; ;pic12f1840.h: 3247: };
+[; ;pic12f1840.h: 3248: } SSPCON1bits_t;
+[; ;pic12f1840.h: 3249: extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+[; ;pic12f1840.h: 3296: typedef union {
+[; ;pic12f1840.h: 3297: struct {
+[; ;pic12f1840.h: 3298: unsigned SSPM0 :1;
+[; ;pic12f1840.h: 3299: unsigned SSPM1 :1;
+[; ;pic12f1840.h: 3300: unsigned SSPM2 :1;
+[; ;pic12f1840.h: 3301: unsigned SSPM3 :1;
+[; ;pic12f1840.h: 3302: unsigned CKP :1;
+[; ;pic12f1840.h: 3303: unsigned SSPEN :1;
+[; ;pic12f1840.h: 3304: unsigned SSPOV :1;
+[; ;pic12f1840.h: 3305: unsigned WCOL :1;
+[; ;pic12f1840.h: 3306: };
+[; ;pic12f1840.h: 3307: struct {
+[; ;pic12f1840.h: 3308: unsigned SSPM :4;
+[; ;pic12f1840.h: 3309: };
+[; ;pic12f1840.h: 3310: } SSPCONbits_t;
+[; ;pic12f1840.h: 3311: extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+[; ;pic12f1840.h: 3360: extern volatile unsigned char SSP1CON2 @ 0x216;
+"3362
+[; ;pic12f1840.h: 3362: asm("SSP1CON2 equ 0216h");
+[; <" SSP1CON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3365: extern volatile unsigned char SSPCON2 @ 0x216;
+"3367
+[; ;pic12f1840.h: 3367: asm("SSPCON2 equ 0216h");
+[; <" SSPCON2 equ 0216h ;# ">
+[; ;pic12f1840.h: 3370: typedef union {
+[; ;pic12f1840.h: 3371: struct {
+[; ;pic12f1840.h: 3372: unsigned SEN :1;
+[; ;pic12f1840.h: 3373: unsigned RSEN :1;
+[; ;pic12f1840.h: 3374: unsigned PEN :1;
+[; ;pic12f1840.h: 3375: unsigned RCEN :1;
+[; ;pic12f1840.h: 3376: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3377: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3378: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3379: unsigned GCEN :1;
+[; ;pic12f1840.h: 3380: };
+[; ;pic12f1840.h: 3381: } SSP1CON2bits_t;
+[; ;pic12f1840.h: 3382: extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+[; ;pic12f1840.h: 3425: typedef union {
+[; ;pic12f1840.h: 3426: struct {
+[; ;pic12f1840.h: 3427: unsigned SEN :1;
+[; ;pic12f1840.h: 3428: unsigned RSEN :1;
+[; ;pic12f1840.h: 3429: unsigned PEN :1;
+[; ;pic12f1840.h: 3430: unsigned RCEN :1;
+[; ;pic12f1840.h: 3431: unsigned ACKEN :1;
+[; ;pic12f1840.h: 3432: unsigned ACKDT :1;
+[; ;pic12f1840.h: 3433: unsigned ACKSTAT :1;
+[; ;pic12f1840.h: 3434: unsigned GCEN :1;
+[; ;pic12f1840.h: 3435: };
+[; ;pic12f1840.h: 3436: } SSPCON2bits_t;
+[; ;pic12f1840.h: 3437: extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+[; ;pic12f1840.h: 3481: extern volatile unsigned char SSP1CON3 @ 0x217;
+"3483
+[; ;pic12f1840.h: 3483: asm("SSP1CON3 equ 0217h");
+[; <" SSP1CON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3486: extern volatile unsigned char SSPCON3 @ 0x217;
+"3488
+[; ;pic12f1840.h: 3488: asm("SSPCON3 equ 0217h");
+[; <" SSPCON3 equ 0217h ;# ">
+[; ;pic12f1840.h: 3491: typedef union {
+[; ;pic12f1840.h: 3492: struct {
+[; ;pic12f1840.h: 3493: unsigned DHEN :1;
+[; ;pic12f1840.h: 3494: unsigned AHEN :1;
+[; ;pic12f1840.h: 3495: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3496: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3497: unsigned BOEN :1;
+[; ;pic12f1840.h: 3498: unsigned SCIE :1;
+[; ;pic12f1840.h: 3499: unsigned PCIE :1;
+[; ;pic12f1840.h: 3500: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3501: };
+[; ;pic12f1840.h: 3502: } SSP1CON3bits_t;
+[; ;pic12f1840.h: 3503: extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+[; ;pic12f1840.h: 3546: typedef union {
+[; ;pic12f1840.h: 3547: struct {
+[; ;pic12f1840.h: 3548: unsigned DHEN :1;
+[; ;pic12f1840.h: 3549: unsigned AHEN :1;
+[; ;pic12f1840.h: 3550: unsigned SBCDE :1;
+[; ;pic12f1840.h: 3551: unsigned SDAHT :1;
+[; ;pic12f1840.h: 3552: unsigned BOEN :1;
+[; ;pic12f1840.h: 3553: unsigned SCIE :1;
+[; ;pic12f1840.h: 3554: unsigned PCIE :1;
+[; ;pic12f1840.h: 3555: unsigned ACKTIM :1;
+[; ;pic12f1840.h: 3556: };
+[; ;pic12f1840.h: 3557: } SSPCON3bits_t;
+[; ;pic12f1840.h: 3558: extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+[; ;pic12f1840.h: 3602: extern volatile unsigned char CCPR1L @ 0x291;
+"3604
+[; ;pic12f1840.h: 3604: asm("CCPR1L equ 0291h");
+[; <" CCPR1L equ 0291h ;# ">
+[; ;pic12f1840.h: 3607: typedef union {
+[; ;pic12f1840.h: 3608: struct {
+[; ;pic12f1840.h: 3609: unsigned CCPR1L :8;
+[; ;pic12f1840.h: 3610: };
+[; ;pic12f1840.h: 3611: } CCPR1Lbits_t;
+[; ;pic12f1840.h: 3612: extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+[; ;pic12f1840.h: 3621: extern volatile unsigned char CCPR1H @ 0x292;
+"3623
+[; ;pic12f1840.h: 3623: asm("CCPR1H equ 0292h");
+[; <" CCPR1H equ 0292h ;# ">
+[; ;pic12f1840.h: 3626: typedef union {
+[; ;pic12f1840.h: 3627: struct {
+[; ;pic12f1840.h: 3628: unsigned CCPR1H :8;
+[; ;pic12f1840.h: 3629: };
+[; ;pic12f1840.h: 3630: } CCPR1Hbits_t;
+[; ;pic12f1840.h: 3631: extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+[; ;pic12f1840.h: 3640: extern volatile unsigned char CCP1CON @ 0x293;
+"3642
+[; ;pic12f1840.h: 3642: asm("CCP1CON equ 0293h");
+[; <" CCP1CON equ 0293h ;# ">
+[; ;pic12f1840.h: 3645: typedef union {
+[; ;pic12f1840.h: 3646: struct {
+[; ;pic12f1840.h: 3647: unsigned CCP1M0 :1;
+[; ;pic12f1840.h: 3648: unsigned CCP1M1 :1;
+[; ;pic12f1840.h: 3649: unsigned CCP1M2 :1;
+[; ;pic12f1840.h: 3650: unsigned CCP1M3 :1;
+[; ;pic12f1840.h: 3651: unsigned DC1B0 :1;
+[; ;pic12f1840.h: 3652: unsigned DC1B1 :1;
+[; ;pic12f1840.h: 3653: unsigned P1M0 :1;
+[; ;pic12f1840.h: 3654: unsigned P1M1 :1;
+[; ;pic12f1840.h: 3655: };
+[; ;pic12f1840.h: 3656: struct {
+[; ;pic12f1840.h: 3657: unsigned CCP1M :4;
+[; ;pic12f1840.h: 3658: unsigned DC1B :2;
+[; ;pic12f1840.h: 3659: unsigned P1M :2;
+[; ;pic12f1840.h: 3660: };
+[; ;pic12f1840.h: 3661: } CCP1CONbits_t;
+[; ;pic12f1840.h: 3662: extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+[; ;pic12f1840.h: 3721: extern volatile unsigned char PWM1CON @ 0x294;
+"3723
+[; ;pic12f1840.h: 3723: asm("PWM1CON equ 0294h");
+[; <" PWM1CON equ 0294h ;# ">
+[; ;pic12f1840.h: 3726: typedef union {
+[; ;pic12f1840.h: 3727: struct {
+[; ;pic12f1840.h: 3728: unsigned P1DC0 :1;
+[; ;pic12f1840.h: 3729: unsigned P1DC1 :1;
+[; ;pic12f1840.h: 3730: unsigned P1DC2 :1;
+[; ;pic12f1840.h: 3731: unsigned P1DC3 :1;
+[; ;pic12f1840.h: 3732: unsigned P1DC4 :1;
+[; ;pic12f1840.h: 3733: unsigned P1DC5 :1;
+[; ;pic12f1840.h: 3734: unsigned P1DC6 :1;
+[; ;pic12f1840.h: 3735: unsigned P1RSEN :1;
+[; ;pic12f1840.h: 3736: };
+[; ;pic12f1840.h: 3737: struct {
+[; ;pic12f1840.h: 3738: unsigned P1DC :7;
+[; ;pic12f1840.h: 3739: };
+[; ;pic12f1840.h: 3740: } PWM1CONbits_t;
+[; ;pic12f1840.h: 3741: extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+[; ;pic12f1840.h: 3790: extern volatile unsigned char CCP1AS @ 0x295;
+"3792
+[; ;pic12f1840.h: 3792: asm("CCP1AS equ 0295h");
+[; <" CCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3795: extern volatile unsigned char ECCP1AS @ 0x295;
+"3797
+[; ;pic12f1840.h: 3797: asm("ECCP1AS equ 0295h");
+[; <" ECCP1AS equ 0295h ;# ">
+[; ;pic12f1840.h: 3800: typedef union {
+[; ;pic12f1840.h: 3801: struct {
+[; ;pic12f1840.h: 3802: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3803: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3804: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3805: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3806: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3807: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3808: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3809: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3810: };
+[; ;pic12f1840.h: 3811: struct {
+[; ;pic12f1840.h: 3812: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3813: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3814: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3815: };
+[; ;pic12f1840.h: 3816: } CCP1ASbits_t;
+[; ;pic12f1840.h: 3817: extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3875: typedef union {
+[; ;pic12f1840.h: 3876: struct {
+[; ;pic12f1840.h: 3877: unsigned PSS1BD0 :1;
+[; ;pic12f1840.h: 3878: unsigned PSS1BD1 :1;
+[; ;pic12f1840.h: 3879: unsigned PSS1AC0 :1;
+[; ;pic12f1840.h: 3880: unsigned PSS1AC1 :1;
+[; ;pic12f1840.h: 3881: unsigned CCP1AS0 :1;
+[; ;pic12f1840.h: 3882: unsigned CCP1AS1 :1;
+[; ;pic12f1840.h: 3883: unsigned CCP1AS2 :1;
+[; ;pic12f1840.h: 3884: unsigned CCP1ASE :1;
+[; ;pic12f1840.h: 3885: };
+[; ;pic12f1840.h: 3886: struct {
+[; ;pic12f1840.h: 3887: unsigned PSS1BD :2;
+[; ;pic12f1840.h: 3888: unsigned PSS1AC :2;
+[; ;pic12f1840.h: 3889: unsigned CCP1AS :3;
+[; ;pic12f1840.h: 3890: };
+[; ;pic12f1840.h: 3891: } ECCP1ASbits_t;
+[; ;pic12f1840.h: 3892: extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+[; ;pic12f1840.h: 3951: extern volatile unsigned char PSTR1CON @ 0x296;
+"3953
+[; ;pic12f1840.h: 3953: asm("PSTR1CON equ 0296h");
+[; <" PSTR1CON equ 0296h ;# ">
+[; ;pic12f1840.h: 3956: typedef union {
+[; ;pic12f1840.h: 3957: struct {
+[; ;pic12f1840.h: 3958: unsigned STR1A :1;
+[; ;pic12f1840.h: 3959: unsigned STR1B :1;
+[; ;pic12f1840.h: 3960: unsigned :1;
+[; ;pic12f1840.h: 3961: unsigned :1;
+[; ;pic12f1840.h: 3962: unsigned STR1SYNC :1;
+[; ;pic12f1840.h: 3963: };
+[; ;pic12f1840.h: 3964: } PSTR1CONbits_t;
+[; ;pic12f1840.h: 3965: extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+[; ;pic12f1840.h: 3984: extern volatile unsigned char IOCAP @ 0x391;
+"3986
+[; ;pic12f1840.h: 3986: asm("IOCAP equ 0391h");
+[; <" IOCAP equ 0391h ;# ">
+[; ;pic12f1840.h: 3989: typedef union {
+[; ;pic12f1840.h: 3990: struct {
+[; ;pic12f1840.h: 3991: unsigned IOCAP0 :1;
+[; ;pic12f1840.h: 3992: unsigned IOCAP1 :1;
+[; ;pic12f1840.h: 3993: unsigned IOCAP2 :1;
+[; ;pic12f1840.h: 3994: unsigned IOCAP3 :1;
+[; ;pic12f1840.h: 3995: unsigned IOCAP4 :1;
+[; ;pic12f1840.h: 3996: unsigned IOCAP5 :1;
+[; ;pic12f1840.h: 3997: };
+[; ;pic12f1840.h: 3998: struct {
+[; ;pic12f1840.h: 3999: unsigned IOCAP :6;
+[; ;pic12f1840.h: 4000: };
+[; ;pic12f1840.h: 4001: } IOCAPbits_t;
+[; ;pic12f1840.h: 4002: extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+[; ;pic12f1840.h: 4041: extern volatile unsigned char IOCAN @ 0x392;
+"4043
+[; ;pic12f1840.h: 4043: asm("IOCAN equ 0392h");
+[; <" IOCAN equ 0392h ;# ">
+[; ;pic12f1840.h: 4046: typedef union {
+[; ;pic12f1840.h: 4047: struct {
+[; ;pic12f1840.h: 4048: unsigned IOCAN0 :1;
+[; ;pic12f1840.h: 4049: unsigned IOCAN1 :1;
+[; ;pic12f1840.h: 4050: unsigned IOCAN2 :1;
+[; ;pic12f1840.h: 4051: unsigned IOCAN3 :1;
+[; ;pic12f1840.h: 4052: unsigned IOCAN4 :1;
+[; ;pic12f1840.h: 4053: unsigned IOCAN5 :1;
+[; ;pic12f1840.h: 4054: };
+[; ;pic12f1840.h: 4055: struct {
+[; ;pic12f1840.h: 4056: unsigned IOCAN :6;
+[; ;pic12f1840.h: 4057: };
+[; ;pic12f1840.h: 4058: } IOCANbits_t;
+[; ;pic12f1840.h: 4059: extern volatile IOCANbits_t IOCANbits @ 0x392;
+[; ;pic12f1840.h: 4098: extern volatile unsigned char IOCAF @ 0x393;
+"4100
+[; ;pic12f1840.h: 4100: asm("IOCAF equ 0393h");
+[; <" IOCAF equ 0393h ;# ">
+[; ;pic12f1840.h: 4103: typedef union {
+[; ;pic12f1840.h: 4104: struct {
+[; ;pic12f1840.h: 4105: unsigned IOCAF0 :1;
+[; ;pic12f1840.h: 4106: unsigned IOCAF1 :1;
+[; ;pic12f1840.h: 4107: unsigned IOCAF2 :1;
+[; ;pic12f1840.h: 4108: unsigned IOCAF3 :1;
+[; ;pic12f1840.h: 4109: unsigned IOCAF4 :1;
+[; ;pic12f1840.h: 4110: unsigned IOCAF5 :1;
+[; ;pic12f1840.h: 4111: };
+[; ;pic12f1840.h: 4112: struct {
+[; ;pic12f1840.h: 4113: unsigned IOCAF :6;
+[; ;pic12f1840.h: 4114: };
+[; ;pic12f1840.h: 4115: } IOCAFbits_t;
+[; ;pic12f1840.h: 4116: extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+[; ;pic12f1840.h: 4155: extern volatile unsigned char CLKRCON @ 0x39A;
+"4157
+[; ;pic12f1840.h: 4157: asm("CLKRCON equ 039Ah");
+[; <" CLKRCON equ 039Ah ;# ">
+[; ;pic12f1840.h: 4160: typedef union {
+[; ;pic12f1840.h: 4161: struct {
+[; ;pic12f1840.h: 4162: unsigned CLKRDIV0 :1;
+[; ;pic12f1840.h: 4163: unsigned CLKRDIV1 :1;
+[; ;pic12f1840.h: 4164: unsigned CLKRDIV2 :1;
+[; ;pic12f1840.h: 4165: unsigned CLKRDC0 :1;
+[; ;pic12f1840.h: 4166: unsigned CLKRDC1 :1;
+[; ;pic12f1840.h: 4167: unsigned CLKRSLR :1;
+[; ;pic12f1840.h: 4168: unsigned CLKROE :1;
+[; ;pic12f1840.h: 4169: unsigned CLKREN :1;
+[; ;pic12f1840.h: 4170: };
+[; ;pic12f1840.h: 4171: struct {
+[; ;pic12f1840.h: 4172: unsigned CLKRDIV :3;
+[; ;pic12f1840.h: 4173: unsigned CLKRDC :2;
+[; ;pic12f1840.h: 4174: };
+[; ;pic12f1840.h: 4175: } CLKRCONbits_t;
+[; ;pic12f1840.h: 4176: extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+[; ;pic12f1840.h: 4230: extern volatile unsigned char MDCON @ 0x39C;
+"4232
+[; ;pic12f1840.h: 4232: asm("MDCON equ 039Ch");
+[; <" MDCON equ 039Ch ;# ">
+[; ;pic12f1840.h: 4235: typedef union {
+[; ;pic12f1840.h: 4236: struct {
+[; ;pic12f1840.h: 4237: unsigned MDBIT :1;
+[; ;pic12f1840.h: 4238: unsigned :2;
+[; ;pic12f1840.h: 4239: unsigned MDOUT :1;
+[; ;pic12f1840.h: 4240: unsigned MDOPOL :1;
+[; ;pic12f1840.h: 4241: unsigned MDSLR :1;
+[; ;pic12f1840.h: 4242: unsigned MDOE :1;
+[; ;pic12f1840.h: 4243: unsigned MDEN :1;
+[; ;pic12f1840.h: 4244: };
+[; ;pic12f1840.h: 4245: } MDCONbits_t;
+[; ;pic12f1840.h: 4246: extern volatile MDCONbits_t MDCONbits @ 0x39C;
+[; ;pic12f1840.h: 4280: extern volatile unsigned char MDSRC @ 0x39D;
+"4282
+[; ;pic12f1840.h: 4282: asm("MDSRC equ 039Dh");
+[; <" MDSRC equ 039Dh ;# ">
+[; ;pic12f1840.h: 4285: typedef union {
+[; ;pic12f1840.h: 4286: struct {
+[; ;pic12f1840.h: 4287: unsigned MDMS0 :1;
+[; ;pic12f1840.h: 4288: unsigned MDMS1 :1;
+[; ;pic12f1840.h: 4289: unsigned MDMS2 :1;
+[; ;pic12f1840.h: 4290: unsigned MDMS3 :1;
+[; ;pic12f1840.h: 4291: unsigned :3;
+[; ;pic12f1840.h: 4292: unsigned MDMSODIS :1;
+[; ;pic12f1840.h: 4293: };
+[; ;pic12f1840.h: 4294: struct {
+[; ;pic12f1840.h: 4295: unsigned MDMS :4;
+[; ;pic12f1840.h: 4296: };
+[; ;pic12f1840.h: 4297: } MDSRCbits_t;
+[; ;pic12f1840.h: 4298: extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+[; ;pic12f1840.h: 4332: extern volatile unsigned char MDCARL @ 0x39E;
+"4334
+[; ;pic12f1840.h: 4334: asm("MDCARL equ 039Eh");
+[; <" MDCARL equ 039Eh ;# ">
+[; ;pic12f1840.h: 4337: typedef union {
+[; ;pic12f1840.h: 4338: struct {
+[; ;pic12f1840.h: 4339: unsigned MDCL0 :1;
+[; ;pic12f1840.h: 4340: unsigned MDCL1 :1;
+[; ;pic12f1840.h: 4341: unsigned MDCL2 :1;
+[; ;pic12f1840.h: 4342: unsigned MDCL3 :1;
+[; ;pic12f1840.h: 4343: unsigned :1;
+[; ;pic12f1840.h: 4344: unsigned MDCLSYNC :1;
+[; ;pic12f1840.h: 4345: unsigned MDCLPOL :1;
+[; ;pic12f1840.h: 4346: unsigned MDCLODIS :1;
+[; ;pic12f1840.h: 4347: };
+[; ;pic12f1840.h: 4348: struct {
+[; ;pic12f1840.h: 4349: unsigned MDCL :4;
+[; ;pic12f1840.h: 4350: };
+[; ;pic12f1840.h: 4351: } MDCARLbits_t;
+[; ;pic12f1840.h: 4352: extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+[; ;pic12f1840.h: 4396: extern volatile unsigned char MDCARH @ 0x39F;
+"4398
+[; ;pic12f1840.h: 4398: asm("MDCARH equ 039Fh");
+[; <" MDCARH equ 039Fh ;# ">
+[; ;pic12f1840.h: 4401: typedef union {
+[; ;pic12f1840.h: 4402: struct {
+[; ;pic12f1840.h: 4403: unsigned MDCH0 :1;
+[; ;pic12f1840.h: 4404: unsigned MDCH1 :1;
+[; ;pic12f1840.h: 4405: unsigned MDCH2 :1;
+[; ;pic12f1840.h: 4406: unsigned MDCH3 :1;
+[; ;pic12f1840.h: 4407: unsigned :1;
+[; ;pic12f1840.h: 4408: unsigned MDCHSYNC :1;
+[; ;pic12f1840.h: 4409: unsigned MDCHPOL :1;
+[; ;pic12f1840.h: 4410: unsigned MDCHODIS :1;
+[; ;pic12f1840.h: 4411: };
+[; ;pic12f1840.h: 4412: struct {
+[; ;pic12f1840.h: 4413: unsigned MDCH :4;
+[; ;pic12f1840.h: 4414: };
+[; ;pic12f1840.h: 4415: } MDCARHbits_t;
+[; ;pic12f1840.h: 4416: extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+[; ;pic12f1840.h: 4460: extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+"4462
+[; ;pic12f1840.h: 4462: asm("STATUS_SHAD equ 0FE4h");
+[; <" STATUS_SHAD equ 0FE4h ;# ">
+[; ;pic12f1840.h: 4465: typedef union {
+[; ;pic12f1840.h: 4466: struct {
+[; ;pic12f1840.h: 4467: unsigned C_SHAD :1;
+[; ;pic12f1840.h: 4468: unsigned DC_SHAD :1;
+[; ;pic12f1840.h: 4469: unsigned Z_SHAD :1;
+[; ;pic12f1840.h: 4470: };
+[; ;pic12f1840.h: 4471: } STATUS_SHADbits_t;
+[; ;pic12f1840.h: 4472: extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+[; ;pic12f1840.h: 4491: extern volatile unsigned char WREG_SHAD @ 0xFE5;
+"4493
+[; ;pic12f1840.h: 4493: asm("WREG_SHAD equ 0FE5h");
+[; <" WREG_SHAD equ 0FE5h ;# ">
+[; ;pic12f1840.h: 4496: typedef union {
+[; ;pic12f1840.h: 4497: struct {
+[; ;pic12f1840.h: 4498: unsigned WREG_SHAD :8;
+[; ;pic12f1840.h: 4499: };
+[; ;pic12f1840.h: 4500: } WREG_SHADbits_t;
+[; ;pic12f1840.h: 4501: extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+[; ;pic12f1840.h: 4510: extern volatile unsigned char BSR_SHAD @ 0xFE6;
+"4512
+[; ;pic12f1840.h: 4512: asm("BSR_SHAD equ 0FE6h");
+[; <" BSR_SHAD equ 0FE6h ;# ">
+[; ;pic12f1840.h: 4515: typedef union {
+[; ;pic12f1840.h: 4516: struct {
+[; ;pic12f1840.h: 4517: unsigned BSR_SHAD :5;
+[; ;pic12f1840.h: 4518: };
+[; ;pic12f1840.h: 4519: } BSR_SHADbits_t;
+[; ;pic12f1840.h: 4520: extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+[; ;pic12f1840.h: 4529: extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+"4531
+[; ;pic12f1840.h: 4531: asm("PCLATH_SHAD equ 0FE7h");
+[; <" PCLATH_SHAD equ 0FE7h ;# ">
+[; ;pic12f1840.h: 4534: typedef union {
+[; ;pic12f1840.h: 4535: struct {
+[; ;pic12f1840.h: 4536: unsigned PCLATH_SHAD :7;
+[; ;pic12f1840.h: 4537: };
+[; ;pic12f1840.h: 4538: } PCLATH_SHADbits_t;
+[; ;pic12f1840.h: 4539: extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+[; ;pic12f1840.h: 4548: extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+"4550
+[; ;pic12f1840.h: 4550: asm("FSR0L_SHAD equ 0FE8h");
+[; <" FSR0L_SHAD equ 0FE8h ;# ">
+[; ;pic12f1840.h: 4553: typedef union {
+[; ;pic12f1840.h: 4554: struct {
+[; ;pic12f1840.h: 4555: unsigned FSR0L_SHAD :8;
+[; ;pic12f1840.h: 4556: };
+[; ;pic12f1840.h: 4557: } FSR0L_SHADbits_t;
+[; ;pic12f1840.h: 4558: extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+[; ;pic12f1840.h: 4567: extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+"4569
+[; ;pic12f1840.h: 4569: asm("FSR0H_SHAD equ 0FE9h");
+[; <" FSR0H_SHAD equ 0FE9h ;# ">
+[; ;pic12f1840.h: 4572: typedef union {
+[; ;pic12f1840.h: 4573: struct {
+[; ;pic12f1840.h: 4574: unsigned FSR0H_SHAD :8;
+[; ;pic12f1840.h: 4575: };
+[; ;pic12f1840.h: 4576: } FSR0H_SHADbits_t;
+[; ;pic12f1840.h: 4577: extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+[; ;pic12f1840.h: 4586: extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+"4588
+[; ;pic12f1840.h: 4588: asm("FSR1L_SHAD equ 0FEAh");
+[; <" FSR1L_SHAD equ 0FEAh ;# ">
+[; ;pic12f1840.h: 4591: typedef union {
+[; ;pic12f1840.h: 4592: struct {
+[; ;pic12f1840.h: 4593: unsigned FSR1L_SHAD :8;
+[; ;pic12f1840.h: 4594: };
+[; ;pic12f1840.h: 4595: } FSR1L_SHADbits_t;
+[; ;pic12f1840.h: 4596: extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+[; ;pic12f1840.h: 4605: extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+"4607
+[; ;pic12f1840.h: 4607: asm("FSR1H_SHAD equ 0FEBh");
+[; <" FSR1H_SHAD equ 0FEBh ;# ">
+[; ;pic12f1840.h: 4610: typedef union {
+[; ;pic12f1840.h: 4611: struct {
+[; ;pic12f1840.h: 4612: unsigned FSR1H_SHAD :8;
+[; ;pic12f1840.h: 4613: };
+[; ;pic12f1840.h: 4614: } FSR1H_SHADbits_t;
+[; ;pic12f1840.h: 4615: extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+[; ;pic12f1840.h: 4624: extern volatile unsigned char STKPTR @ 0xFED;
+"4626
+[; ;pic12f1840.h: 4626: asm("STKPTR equ 0FEDh");
+[; <" STKPTR equ 0FEDh ;# ">
+[; ;pic12f1840.h: 4629: typedef union {
+[; ;pic12f1840.h: 4630: struct {
+[; ;pic12f1840.h: 4631: unsigned STKPTR :5;
+[; ;pic12f1840.h: 4632: };
+[; ;pic12f1840.h: 4633: } STKPTRbits_t;
+[; ;pic12f1840.h: 4634: extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+[; ;pic12f1840.h: 4643: extern volatile unsigned char TOSL @ 0xFEE;
+"4645
+[; ;pic12f1840.h: 4645: asm("TOSL equ 0FEEh");
+[; <" TOSL equ 0FEEh ;# ">
+[; ;pic12f1840.h: 4648: typedef union {
+[; ;pic12f1840.h: 4649: struct {
+[; ;pic12f1840.h: 4650: unsigned TOSL :8;
+[; ;pic12f1840.h: 4651: };
+[; ;pic12f1840.h: 4652: } TOSLbits_t;
+[; ;pic12f1840.h: 4653: extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+[; ;pic12f1840.h: 4662: extern volatile unsigned char TOSH @ 0xFEF;
+"4664
+[; ;pic12f1840.h: 4664: asm("TOSH equ 0FEFh");
+[; <" TOSH equ 0FEFh ;# ">
+[; ;pic12f1840.h: 4667: typedef union {
+[; ;pic12f1840.h: 4668: struct {
+[; ;pic12f1840.h: 4669: unsigned TOSH :7;
+[; ;pic12f1840.h: 4670: };
+[; ;pic12f1840.h: 4671: } TOSHbits_t;
+[; ;pic12f1840.h: 4672: extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+[; ;pic12f1840.h: 4687: extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+[; ;pic12f1840.h: 4689: extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+[; ;pic12f1840.h: 4691: extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+[; ;pic12f1840.h: 4693: extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+[; ;pic12f1840.h: 4695: extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+[; ;pic12f1840.h: 4697: extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+[; ;pic12f1840.h: 4699: extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+[; ;pic12f1840.h: 4701: extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+[; ;pic12f1840.h: 4703: extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+[; ;pic12f1840.h: 4705: extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+[; ;pic12f1840.h: 4707: extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+[; ;pic12f1840.h: 4709: extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+[; ;pic12f1840.h: 4711: extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+[; ;pic12f1840.h: 4713: extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4715: extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+[; ;pic12f1840.h: 4717: extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+[; ;pic12f1840.h: 4719: extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+[; ;pic12f1840.h: 4721: extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+[; ;pic12f1840.h: 4723: extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+[; ;pic12f1840.h: 4725: extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+[; ;pic12f1840.h: 4727: extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+[; ;pic12f1840.h: 4729: extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+[; ;pic12f1840.h: 4731: extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+[; ;pic12f1840.h: 4733: extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+[; ;pic12f1840.h: 4735: extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+[; ;pic12f1840.h: 4737: extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+[; ;pic12f1840.h: 4739: extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+[; ;pic12f1840.h: 4741: extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+[; ;pic12f1840.h: 4743: extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+[; ;pic12f1840.h: 4745: extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+[; ;pic12f1840.h: 4747: extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+[; ;pic12f1840.h: 4749: extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+[; ;pic12f1840.h: 4751: extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+[; ;pic12f1840.h: 4753: extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+[; ;pic12f1840.h: 4755: extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+[; ;pic12f1840.h: 4757: extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+[; ;pic12f1840.h: 4759: extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+[; ;pic12f1840.h: 4761: extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+[; ;pic12f1840.h: 4763: extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+[; ;pic12f1840.h: 4765: extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+[; ;pic12f1840.h: 4767: extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+[; ;pic12f1840.h: 4769: extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+[; ;pic12f1840.h: 4771: extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4773: extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+[; ;pic12f1840.h: 4775: extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+[; ;pic12f1840.h: 4777: extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+[; ;pic12f1840.h: 4779: extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+[; ;pic12f1840.h: 4781: extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+[; ;pic12f1840.h: 4783: extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+[; ;pic12f1840.h: 4785: extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+[; ;pic12f1840.h: 4787: extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+[; ;pic12f1840.h: 4789: extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+[; ;pic12f1840.h: 4791: extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+[; ;pic12f1840.h: 4793: extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+[; ;pic12f1840.h: 4795: extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+[; ;pic12f1840.h: 4797: extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+[; ;pic12f1840.h: 4799: extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+[; ;pic12f1840.h: 4801: extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+[; ;pic12f1840.h: 4803: extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+[; ;pic12f1840.h: 4805: extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+[; ;pic12f1840.h: 4807: extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+[; ;pic12f1840.h: 4809: extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+[; ;pic12f1840.h: 4811: extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+[; ;pic12f1840.h: 4813: extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+[; ;pic12f1840.h: 4815: extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+[; ;pic12f1840.h: 4817: extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+[; ;pic12f1840.h: 4819: extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+[; ;pic12f1840.h: 4821: extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+[; ;pic12f1840.h: 4823: extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+[; ;pic12f1840.h: 4825: extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+[; ;pic12f1840.h: 4827: extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+[; ;pic12f1840.h: 4829: extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+[; ;pic12f1840.h: 4831: extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+[; ;pic12f1840.h: 4833: extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+[; ;pic12f1840.h: 4835: extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+[; ;pic12f1840.h: 4837: extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+[; ;pic12f1840.h: 4839: extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+[; ;pic12f1840.h: 4841: extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+[; ;pic12f1840.h: 4843: extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+[; ;pic12f1840.h: 4845: extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+[; ;pic12f1840.h: 4847: extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+[; ;pic12f1840.h: 4849: extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+[; ;pic12f1840.h: 4851: extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+[; ;pic12f1840.h: 4853: extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+[; ;pic12f1840.h: 4855: extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+[; ;pic12f1840.h: 4857: extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+[; ;pic12f1840.h: 4859: extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+[; ;pic12f1840.h: 4861: extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+[; ;pic12f1840.h: 4863: extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+[; ;pic12f1840.h: 4865: extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+[; ;pic12f1840.h: 4867: extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+[; ;pic12f1840.h: 4869: extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+[; ;pic12f1840.h: 4871: extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+[; ;pic12f1840.h: 4873: extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+[; ;pic12f1840.h: 4875: extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+[; ;pic12f1840.h: 4877: extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+[; ;pic12f1840.h: 4879: extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+[; ;pic12f1840.h: 4881: extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+[; ;pic12f1840.h: 4883: extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+[; ;pic12f1840.h: 4885: extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+[; ;pic12f1840.h: 4887: extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+[; ;pic12f1840.h: 4889: extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+[; ;pic12f1840.h: 4891: extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+[; ;pic12f1840.h: 4893: extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+[; ;pic12f1840.h: 4895: extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+[; ;pic12f1840.h: 4897: extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+[; ;pic12f1840.h: 4899: extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+[; ;pic12f1840.h: 4901: extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+[; ;pic12f1840.h: 4903: extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+[; ;pic12f1840.h: 4905: extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+[; ;pic12f1840.h: 4907: extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+[; ;pic12f1840.h: 4909: extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+[; ;pic12f1840.h: 4911: extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+[; ;pic12f1840.h: 4913: extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+[; ;pic12f1840.h: 4915: extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+[; ;pic12f1840.h: 4917: extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+[; ;pic12f1840.h: 4919: extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+[; ;pic12f1840.h: 4921: extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4923: extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+[; ;pic12f1840.h: 4925: extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+[; ;pic12f1840.h: 4927: extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+[; ;pic12f1840.h: 4929: extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+[; ;pic12f1840.h: 4931: extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+[; ;pic12f1840.h: 4933: extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+[; ;pic12f1840.h: 4935: extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+[; ;pic12f1840.h: 4937: extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+[; ;pic12f1840.h: 4939: extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+[; ;pic12f1840.h: 4941: extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+[; ;pic12f1840.h: 4943: extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+[; ;pic12f1840.h: 4945: extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+[; ;pic12f1840.h: 4947: extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+[; ;pic12f1840.h: 4949: extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+[; ;pic12f1840.h: 4951: extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+[; ;pic12f1840.h: 4953: extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+[; ;pic12f1840.h: 4955: extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+[; ;pic12f1840.h: 4957: extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+[; ;pic12f1840.h: 4959: extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+[; ;pic12f1840.h: 4961: extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+[; ;pic12f1840.h: 4963: extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+[; ;pic12f1840.h: 4965: extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+[; ;pic12f1840.h: 4967: extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+[; ;pic12f1840.h: 4969: extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+[; ;pic12f1840.h: 4971: extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+[; ;pic12f1840.h: 4973: extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+[; ;pic12f1840.h: 4975: extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+[; ;pic12f1840.h: 4977: extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+[; ;pic12f1840.h: 4979: extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+[; ;pic12f1840.h: 4981: extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+[; ;pic12f1840.h: 4983: extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+[; ;pic12f1840.h: 4985: extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+[; ;pic12f1840.h: 4987: extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+[; ;pic12f1840.h: 4989: extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+[; ;pic12f1840.h: 4991: extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+[; ;pic12f1840.h: 4993: extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+[; ;pic12f1840.h: 4995: extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+[; ;pic12f1840.h: 4997: extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+[; ;pic12f1840.h: 4999: extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+[; ;pic12f1840.h: 5001: extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+[; ;pic12f1840.h: 5003: extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+[; ;pic12f1840.h: 5005: extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+[; ;pic12f1840.h: 5007: extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+[; ;pic12f1840.h: 5009: extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+[; ;pic12f1840.h: 5011: extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+[; ;pic12f1840.h: 5013: extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+[; ;pic12f1840.h: 5015: extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+[; ;pic12f1840.h: 5017: extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+[; ;pic12f1840.h: 5019: extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+[; ;pic12f1840.h: 5021: extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+[; ;pic12f1840.h: 5023: extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+[; ;pic12f1840.h: 5025: extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+[; ;pic12f1840.h: 5027: extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+[; ;pic12f1840.h: 5029: extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+[; ;pic12f1840.h: 5031: extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+[; ;pic12f1840.h: 5033: extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+[; ;pic12f1840.h: 5035: extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+[; ;pic12f1840.h: 5037: extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+[; ;pic12f1840.h: 5039: extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+[; ;pic12f1840.h: 5041: extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+[; ;pic12f1840.h: 5043: extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+[; ;pic12f1840.h: 5045: extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+[; ;pic12f1840.h: 5047: extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+[; ;pic12f1840.h: 5049: extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+[; ;pic12f1840.h: 5051: extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+[; ;pic12f1840.h: 5053: extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+[; ;pic12f1840.h: 5055: extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+[; ;pic12f1840.h: 5057: extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+[; ;pic12f1840.h: 5059: extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+[; ;pic12f1840.h: 5061: extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+[; ;pic12f1840.h: 5063: extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+[; ;pic12f1840.h: 5065: extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+[; ;pic12f1840.h: 5067: extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+[; ;pic12f1840.h: 5069: extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+[; ;pic12f1840.h: 5071: extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+[; ;pic12f1840.h: 5073: extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+[; ;pic12f1840.h: 5075: extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+[; ;pic12f1840.h: 5077: extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+[; ;pic12f1840.h: 5079: extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+[; ;pic12f1840.h: 5081: extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+[; ;pic12f1840.h: 5083: extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+[; ;pic12f1840.h: 5085: extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+[; ;pic12f1840.h: 5087: extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+[; ;pic12f1840.h: 5089: extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+[; ;pic12f1840.h: 5091: extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+[; ;pic12f1840.h: 5093: extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+[; ;pic12f1840.h: 5095: extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+[; ;pic12f1840.h: 5097: extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+[; ;pic12f1840.h: 5099: extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+[; ;pic12f1840.h: 5101: extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+[; ;pic12f1840.h: 5103: extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+[; ;pic12f1840.h: 5105: extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+[; ;pic12f1840.h: 5107: extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+[; ;pic12f1840.h: 5109: extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+[; ;pic12f1840.h: 5111: extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+[; ;pic12f1840.h: 5113: extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+[; ;pic12f1840.h: 5115: extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+[; ;pic12f1840.h: 5117: extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+[; ;pic12f1840.h: 5119: extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+[; ;pic12f1840.h: 5121: extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+[; ;pic12f1840.h: 5123: extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+[; ;pic12f1840.h: 5125: extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+[; ;pic12f1840.h: 5127: extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+[; ;pic12f1840.h: 5129: extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+[; ;pic12f1840.h: 5131: extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+[; ;pic12f1840.h: 5133: extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+[; ;pic12f1840.h: 5135: extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+[; ;pic12f1840.h: 5137: extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+[; ;pic12f1840.h: 5139: extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+[; ;pic12f1840.h: 5141: extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+[; ;pic12f1840.h: 5143: extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+[; ;pic12f1840.h: 5145: extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+[; ;pic12f1840.h: 5147: extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+[; ;pic12f1840.h: 5149: extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+[; ;pic12f1840.h: 5151: extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+[; ;pic12f1840.h: 5153: extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5155: extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+[; ;pic12f1840.h: 5157: extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+[; ;pic12f1840.h: 5159: extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+[; ;pic12f1840.h: 5161: extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+[; ;pic12f1840.h: 5163: extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+[; ;pic12f1840.h: 5165: extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+[; ;pic12f1840.h: 5167: extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+[; ;pic12f1840.h: 5169: extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+[; ;pic12f1840.h: 5171: extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+[; ;pic12f1840.h: 5173: extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+[; ;pic12f1840.h: 5175: extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+[; ;pic12f1840.h: 5177: extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+[; ;pic12f1840.h: 5179: extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+[; ;pic12f1840.h: 5181: extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+[; ;pic12f1840.h: 5183: extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+[; ;pic12f1840.h: 5185: extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+[; ;pic12f1840.h: 5187: extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+[; ;pic12f1840.h: 5189: extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+[; ;pic12f1840.h: 5191: extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+[; ;pic12f1840.h: 5193: extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+[; ;pic12f1840.h: 5195: extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+[; ;pic12f1840.h: 5197: extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5199: extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+[; ;pic12f1840.h: 5201: extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+[; ;pic12f1840.h: 5203: extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+[; ;pic12f1840.h: 5205: extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+[; ;pic12f1840.h: 5207: extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+[; ;pic12f1840.h: 5209: extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+[; ;pic12f1840.h: 5211: extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+[; ;pic12f1840.h: 5213: extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+[; ;pic12f1840.h: 5215: extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+[; ;pic12f1840.h: 5217: extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+[; ;pic12f1840.h: 5219: extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+[; ;pic12f1840.h: 5221: extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+[; ;pic12f1840.h: 5223: extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+[; ;pic12f1840.h: 5225: extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+[; ;pic12f1840.h: 5227: extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+[; ;pic12f1840.h: 5229: extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+[; ;pic12f1840.h: 5231: extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5233: extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5235: extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5237: extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5239: extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+[; ;pic12f1840.h: 5241: extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+[; ;pic12f1840.h: 5243: extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+[; ;pic12f1840.h: 5245: extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5247: extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+[; ;pic12f1840.h: 5249: extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+[; ;pic12f1840.h: 5251: extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+[; ;pic12f1840.h: 5253: extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+[; ;pic12f1840.h: 5255: extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+[; ;pic12f1840.h: 5257: extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+[; ;pic12f1840.h: 5259: extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+[; ;pic12f1840.h: 5261: extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+[; ;pic12f1840.h: 5263: extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+[; ;pic12f1840.h: 5265: extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+[; ;pic12f1840.h: 5267: extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+[; ;pic12f1840.h: 5269: extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+[; ;pic12f1840.h: 5271: extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+[; ;pic12f1840.h: 5273: extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+[; ;pic12f1840.h: 5275: extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+[; ;pic12f1840.h: 5277: extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+[; ;pic12f1840.h: 5279: extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+[; ;pic12f1840.h: 5281: extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+[; ;pic12f1840.h: 5283: extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+[; ;pic12f1840.h: 5285: extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+[; ;pic12f1840.h: 5287: extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+[; ;pic12f1840.h: 5289: extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+[; ;pic12f1840.h: 5291: extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+[; ;pic12f1840.h: 5293: extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+[; ;pic12f1840.h: 5295: extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+[; ;pic12f1840.h: 5297: extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+[; ;pic12f1840.h: 5299: extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+[; ;pic12f1840.h: 5301: extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+[; ;pic12f1840.h: 5303: extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+[; ;pic12f1840.h: 5305: extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+[; ;pic12f1840.h: 5307: extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+[; ;pic12f1840.h: 5309: extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+[; ;pic12f1840.h: 5311: extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+[; ;pic12f1840.h: 5313: extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+[; ;pic12f1840.h: 5315: extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+[; ;pic12f1840.h: 5317: extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+[; ;pic12f1840.h: 5319: extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+[; ;pic12f1840.h: 5321: extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+[; ;pic12f1840.h: 5323: extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+[; ;pic12f1840.h: 5325: extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+[; ;pic12f1840.h: 5327: extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+[; ;pic12f1840.h: 5329: extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+[; ;pic12f1840.h: 5331: extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+[; ;pic12f1840.h: 5333: extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+[; ;pic12f1840.h: 5335: extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+[; ;pic12f1840.h: 5337: extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+[; ;pic12f1840.h: 5339: extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+[; ;pic12f1840.h: 5341: extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+[; ;pic12f1840.h: 5343: extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+[; ;pic12f1840.h: 5345: extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+[; ;pic12f1840.h: 5347: extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+[; ;pic12f1840.h: 5349: extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+[; ;pic12f1840.h: 5351: extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+[; ;pic12f1840.h: 5353: extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+[; ;pic12f1840.h: 5355: extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+[; ;pic12f1840.h: 5357: extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+[; ;pic12f1840.h: 5359: extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+[; ;pic12f1840.h: 5361: extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+[; ;pic12f1840.h: 5363: extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+[; ;pic12f1840.h: 5365: extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+[; ;pic12f1840.h: 5367: extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+[; ;pic12f1840.h: 5369: extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+[; ;pic12f1840.h: 5371: extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+[; ;pic12f1840.h: 5373: extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+[; ;pic12f1840.h: 5375: extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+[; ;pic12f1840.h: 5377: extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+[; ;pic12f1840.h: 5379: extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+[; ;pic12f1840.h: 5381: extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+[; ;pic12f1840.h: 5383: extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+[; ;pic12f1840.h: 5385: extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+[; ;pic12f1840.h: 5387: extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+[; ;pic12f1840.h: 5389: extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+[; ;pic12f1840.h: 5391: extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+[; ;pic12f1840.h: 5393: extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+[; ;pic12f1840.h: 5395: extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+[; ;pic12f1840.h: 5397: extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+[; ;pic12f1840.h: 5399: extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+[; ;pic12f1840.h: 5401: extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+[; ;pic12f1840.h: 5403: extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+[; ;pic12f1840.h: 5405: extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+[; ;pic12f1840.h: 5407: extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+[; ;pic.h: 28: extern void _nop(void);
+[; ;pic.h: 77: extern unsigned int flash_read(unsigned short addr);
+[; ;eeprom_routines.h: 41: extern void eeprom_write(unsigned char addr, unsigned char value);
+[; ;eeprom_routines.h: 42: extern unsigned char eeprom_read(unsigned char addr);
+[; ;eeprom_routines.h: 43: extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+[; ;eeprom_routines.h: 44: extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+[; ;pic.h: 151: extern void _delay(unsigned long);
+[; ;stdint.h: 13: typedef signed char int8_t;
+[; ;stdint.h: 20: typedef signed int int16_t;
+[; ;stdint.h: 28: typedef signed short long int int24_t;
+[; ;stdint.h: 36: typedef signed long int int32_t;
+[; ;stdint.h: 43: typedef unsigned char uint8_t;
+[; ;stdint.h: 49: typedef unsigned int uint16_t;
+[; ;stdint.h: 56: typedef unsigned short long int uint24_t;
+[; ;stdint.h: 63: typedef unsigned long int uint32_t;
+[; ;stdint.h: 71: typedef signed char int_least8_t;
+[; ;stdint.h: 78: typedef signed int int_least16_t;
+[; ;stdint.h: 90: typedef signed short long int int_least24_t;
+[; ;stdint.h: 98: typedef signed long int int_least32_t;
+[; ;stdint.h: 105: typedef unsigned char uint_least8_t;
+[; ;stdint.h: 111: typedef unsigned int uint_least16_t;
+[; ;stdint.h: 121: typedef unsigned short long int uint_least24_t;
+[; ;stdint.h: 128: typedef unsigned long int uint_least32_t;
+[; ;stdint.h: 137: typedef signed char int_fast8_t;
+[; ;stdint.h: 144: typedef signed int int_fast16_t;
+[; ;stdint.h: 156: typedef signed short long int int_fast24_t;
+[; ;stdint.h: 164: typedef signed long int int_fast32_t;
+[; ;stdint.h: 171: typedef unsigned char uint_fast8_t;
+[; ;stdint.h: 177: typedef unsigned int uint_fast16_t;
+[; ;stdint.h: 187: typedef unsigned short long int uint_fast24_t;
+[; ;stdint.h: 194: typedef unsigned long int uint_fast32_t;
+[; ;stdint.h: 200: typedef int32_t intmax_t;
+[; ;stdint.h: 205: typedef uint32_t uintmax_t;
+[; ;stdint.h: 210: typedef int16_t intptr_t;
+[; ;stdint.h: 215: typedef uint16_t uintptr_t;
+[; ;stdbool.h: 12: typedef unsigned char bool;
+[; ;user.h: 13: void InitApp(void);
+"23 user.c
+[v _InitApp `(v ~T0 @X0 1 ef ]
+{
+[; ;user.c: 22: void InitApp(void)
+[; ;user.c: 23: {
+[e :U _InitApp ]
+[f ]
+[; ;user.c: 27: OSCCONbits.SPLLEN = 0;
+"27
+[e = . . _OSCCONbits 0 7 -> -> 0 `i `uc ]
+[; ;user.c: 28: OSCCONbits.IRCF = 0b1101;
+"28
+[e = . . _OSCCONbits 1 2 -> -> 13 `i `uc ]
+[; ;user.c: 29: OSCCONbits.SCS = 0b11;
+"29
+[e = . . _OSCCONbits 1 0 -> -> 3 `i `uc ]
+[; ;user.c: 32: TXSTAbits.TXEN = 1;
+"32
+[e = . . _TXSTAbits 0 5 -> -> 1 `i `uc ]
+[; ;user.c: 33: TXSTAbits.SYNC = 0;
+"33
+[e = . . _TXSTAbits 0 4 -> -> 0 `i `uc ]
+[; ;user.c: 34: RCSTAbits.SPEN = 1;
+"34
+[e = . . _RCSTAbits 0 7 -> -> 1 `i `uc ]
+[; ;user.c: 36: RCSTAbits.CREN = 1;
+"36
+[e = . . _RCSTAbits 0 4 -> -> 1 `i `uc ]
+[; ;user.c: 39: TXSTAbits.BRGH = 1;
+"39
+[e = . . _TXSTAbits 0 2 -> -> 1 `i `uc ]
+[; ;user.c: 40: BAUDCONbits.BRG16 = 1;
+"40
+[e = . . _BAUDCONbits 0 3 -> -> 1 `i `uc ]
+[; ;user.c: 41: SPBRG = 8;
+"41
+[e = _SPBRG -> -> 8 `i `uc ]
+[; ;user.c: 44: APFCONbits.RXDTSEL = 1;
+"44
+[e = . . _APFCONbits 0 7 -> -> 1 `i `uc ]
+[; ;user.c: 45: APFCONbits.TXCKSEL = 1;
+"45
+[e = . . _APFCONbits 0 2 -> -> 1 `i `uc ]
+[; ;user.c: 46: TRISAbits.TRISA5 = 1;
+"46
+[e = . . _TRISAbits 0 5 -> -> 1 `i `uc ]
+[; ;user.c: 47: TRISAbits.TRISA4 = 0;
+"47
+[e = . . _TRISAbits 0 4 -> -> 0 `i `uc ]
+[; ;user.c: 49: ANSELA = 0;
+"49
+[e = _ANSELA -> -> 0 `i `uc ]
+[; ;user.c: 53: WPUA = 0;
+"53
+[e = _WPUA -> -> 0 `i `uc ]
+[; ;user.c: 54: OPTION_REGbits.nWPUEN = 0;
+"54
+[e = . . _OPTION_REGbits 0 7 -> -> 0 `i `uc ]
+[; ;user.c: 62: }
+"62
+[e :UE 259 ]
+}

diff --git a/build/XC8_PIC12F609/production/user.p1.d b/build/XC8_PIC12F609/production/user.p1.d
new file mode 100644 (file)
index 0000000..2c5ab6e
--- /dev/null
+++ b/build/XC8_PIC12F609/production/user.p1.d
@@ -0,0 +1,4 @@
+ build/XC8_PIC12F609/production/user.d  \
+ build/XC8_PIC12F609/production/user.p1:  \
+ user.c  \
+user.h 
\ No newline at end of file

diff --git a/build/XC8_PIC12F609/production/user.pre b/build/XC8_PIC12F609/production/user.pre
new file mode 100644 (file)
index 0000000..7605519
--- /dev/null
+++ b/build/XC8_PIC12F609/production/user.pre
@@ -0,0 +1,2855 @@
+
+# 1 "user.c"
+
+# 44 "/opt/microchip/xc8/v1.12/include/pic12f1840.h"
+extern volatile unsigned char INDF0 @ 0x000;
+
+asm("INDF0 equ 00h");
+
+
+typedef union {
+struct {
+unsigned INDF0 :8;
+};
+} INDF0bits_t;
+extern volatile INDF0bits_t INDF0bits @ 0x000;
+
+# 63
+extern volatile unsigned char INDF1 @ 0x001;
+
+asm("INDF1 equ 01h");
+
+
+typedef union {
+struct {
+unsigned INDF1 :8;
+};
+} INDF1bits_t;
+extern volatile INDF1bits_t INDF1bits @ 0x001;
+
+# 82
+extern volatile unsigned char PCL @ 0x002;
+
+asm("PCL equ 02h");
+
+
+typedef union {
+struct {
+unsigned PCL :8;
+};
+} PCLbits_t;
+extern volatile PCLbits_t PCLbits @ 0x002;
+
+# 101
+extern volatile unsigned char STATUS @ 0x003;
+
+asm("STATUS equ 03h");
+
+
+typedef union {
+struct {
+unsigned C :1;
+unsigned DC :1;
+unsigned Z :1;
+unsigned nPD :1;
+unsigned nTO :1;
+};
+struct {
+unsigned CARRY :1;
+};
+struct {
+unsigned :2;
+unsigned ZERO :1;
+};
+} STATUSbits_t;
+extern volatile STATUSbits_t STATUSbits @ 0x003;
+
+# 161
+extern volatile unsigned short FSR0 @ 0x004;
+
+
+extern volatile unsigned char FSR0L @ 0x004;
+
+asm("FSR0L equ 04h");
+
+
+typedef union {
+struct {
+unsigned FSR0L :8;
+};
+} FSR0Lbits_t;
+extern volatile FSR0Lbits_t FSR0Lbits @ 0x004;
+
+# 183
+extern volatile unsigned char FSR0H @ 0x005;
+
+asm("FSR0H equ 05h");
+
+
+typedef union {
+struct {
+unsigned FSR0H :8;
+};
+} FSR0Hbits_t;
+extern volatile FSR0Hbits_t FSR0Hbits @ 0x005;
+
+# 202
+extern volatile unsigned short FSR1 @ 0x006;
+
+
+extern volatile unsigned char FSR1L @ 0x006;
+
+asm("FSR1L equ 06h");
+
+
+typedef union {
+struct {
+unsigned FSR1L :8;
+};
+} FSR1Lbits_t;
+extern volatile FSR1Lbits_t FSR1Lbits @ 0x006;
+
+# 224
+extern volatile unsigned char FSR1H @ 0x007;
+
+asm("FSR1H equ 07h");
+
+
+typedef union {
+struct {
+unsigned FSR1H :8;
+};
+} FSR1Hbits_t;
+extern volatile FSR1Hbits_t FSR1Hbits @ 0x007;
+
+# 243
+extern volatile unsigned char BSR @ 0x008;
+
+asm("BSR equ 08h");
+
+
+typedef union {
+struct {
+unsigned BSR0 :1;
+unsigned BSR1 :1;
+unsigned BSR2 :1;
+unsigned BSR3 :1;
+unsigned BSR4 :1;
+};
+struct {
+unsigned BSR :5;
+};
+} BSRbits_t;
+extern volatile BSRbits_t BSRbits @ 0x008;
+
+# 294
+extern volatile unsigned char WREG @ 0x009;
+
+asm("WREG equ 09h");
+
+
+typedef union {
+struct {
+unsigned WREG0 :8;
+};
+} WREGbits_t;
+extern volatile WREGbits_t WREGbits @ 0x009;
+
+# 313
+extern volatile unsigned char PCLATH @ 0x00A;
+
+asm("PCLATH equ 0Ah");
+
+
+typedef union {
+struct {
+unsigned PCLATH :7;
+};
+} PCLATHbits_t;
+extern volatile PCLATHbits_t PCLATHbits @ 0x00A;
+
+# 332
+extern volatile unsigned char INTCON @ 0x00B;
+
+asm("INTCON equ 0Bh");
+
+
+typedef union {
+struct {
+unsigned IOCIF :1;
+unsigned INTF :1;
+unsigned TMR0IF :1;
+unsigned IOCIE :1;
+unsigned INTE :1;
+unsigned TMR0IE :1;
+unsigned PEIE :1;
+unsigned GIE :1;
+};
+struct {
+unsigned :2;
+unsigned T0IF :1;
+unsigned :2;
+unsigned T0IE :1;
+};
+} INTCONbits_t;
+extern volatile INTCONbits_t INTCONbits @ 0x00B;
+
+# 409
+extern volatile unsigned char PORTA @ 0x00C;
+
+asm("PORTA equ 0Ch");
+
+
+typedef union {
+struct {
+unsigned RA0 :1;
+unsigned RA1 :1;
+unsigned RA2 :1;
+unsigned RA3 :1;
+unsigned RA4 :1;
+unsigned RA5 :1;
+};
+} PORTAbits_t;
+extern volatile PORTAbits_t PORTAbits @ 0x00C;
+
+# 458
+extern volatile unsigned char PIR1 @ 0x011;
+
+asm("PIR1 equ 011h");
+
+
+typedef union {
+struct {
+unsigned TMR1IF :1;
+unsigned TMR2IF :1;
+unsigned CCP1IF :1;
+unsigned SSP1IF :1;
+unsigned TXIF :1;
+unsigned RCIF :1;
+unsigned ADIF :1;
+unsigned TMR1GIF :1;
+};
+} PIR1bits_t;
+extern volatile PIR1bits_t PIR1bits @ 0x011;
+
+# 519
+extern volatile unsigned char PIR2 @ 0x012;
+
+asm("PIR2 equ 012h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IF :1;
+unsigned EEIF :1;
+unsigned C1IF :1;
+unsigned :1;
+unsigned OSFIF :1;
+};
+} PIR2bits_t;
+extern volatile PIR2bits_t PIR2bits @ 0x012;
+
+# 558
+extern volatile unsigned char TMR0 @ 0x015;
+
+asm("TMR0 equ 015h");
+
+
+typedef union {
+struct {
+unsigned TMR0 :8;
+};
+} TMR0bits_t;
+extern volatile TMR0bits_t TMR0bits @ 0x015;
+
+# 577
+extern volatile unsigned short TMR1 @ 0x016;
+
+asm("TMR1 equ 016h");
+
+
+
+extern volatile unsigned char TMR1L @ 0x016;
+
+asm("TMR1L equ 016h");
+
+
+typedef union {
+struct {
+unsigned TMR1L :8;
+};
+} TMR1Lbits_t;
+extern volatile TMR1Lbits_t TMR1Lbits @ 0x016;
+
+# 602
+extern volatile unsigned char TMR1H @ 0x017;
+
+asm("TMR1H equ 017h");
+
+
+typedef union {
+struct {
+unsigned TMR1H :8;
+};
+} TMR1Hbits_t;
+extern volatile TMR1Hbits_t TMR1Hbits @ 0x017;
+
+# 621
+extern volatile unsigned char T1CON @ 0x018;
+
+asm("T1CON equ 018h");
+
+
+typedef union {
+struct {
+unsigned TMR1ON :1;
+unsigned :1;
+unsigned nT1SYNC :1;
+unsigned T1OSCEN :1;
+unsigned T1CKPS0 :1;
+unsigned T1CKPS1 :1;
+unsigned TMR1CS0 :1;
+unsigned TMR1CS1 :1;
+};
+struct {
+unsigned :4;
+unsigned T1CKPS :2;
+unsigned TMR1CS :2;
+};
+} T1CONbits_t;
+extern volatile T1CONbits_t T1CONbits @ 0x018;
+
+# 692
+extern volatile unsigned char T1GCON @ 0x019;
+
+asm("T1GCON equ 019h");
+
+
+typedef union {
+struct {
+unsigned T1GSS0 :1;
+unsigned T1GSS1 :1;
+unsigned T1GVAL :1;
+unsigned T1GGO_nDONE :1;
+unsigned T1GSPM :1;
+unsigned T1GTM :1;
+unsigned T1GPOL :1;
+unsigned TMR1GE :1;
+};
+struct {
+unsigned T1GSS :2;
+unsigned :1;
+unsigned T1GGO :1;
+};
+} T1GCONbits_t;
+extern volatile T1GCONbits_t T1GCONbits @ 0x019;
+
+# 768
+extern volatile unsigned char TMR2 @ 0x01A;
+
+asm("TMR2 equ 01Ah");
+
+
+typedef union {
+struct {
+unsigned TMR2 :8;
+};
+} TMR2bits_t;
+extern volatile TMR2bits_t TMR2bits @ 0x01A;
+
+# 787
+extern volatile unsigned char PR2 @ 0x01B;
+
+asm("PR2 equ 01Bh");
+
+
+typedef union {
+struct {
+unsigned PR2 :8;
+};
+} PR2bits_t;
+extern volatile PR2bits_t PR2bits @ 0x01B;
+
+# 806
+extern volatile unsigned char T2CON @ 0x01C;
+
+asm("T2CON equ 01Ch");
+
+
+typedef union {
+struct {
+unsigned T2CKPS0 :1;
+unsigned T2CKPS1 :1;
+unsigned TMR2ON :1;
+unsigned T2OUTPS0 :1;
+unsigned T2OUTPS1 :1;
+unsigned T2OUTPS2 :1;
+unsigned T2OUTPS3 :1;
+};
+struct {
+unsigned T2CKPS :2;
+unsigned :1;
+unsigned T2OUTPS :4;
+};
+} T2CONbits_t;
+extern volatile T2CONbits_t T2CONbits @ 0x01C;
+
+# 876
+extern volatile unsigned char CPSCON0 @ 0x01E;
+
+asm("CPSCON0 equ 01Eh");
+
+
+typedef union {
+struct {
+unsigned T0XCS :1;
+unsigned CPSOUT :1;
+unsigned CPSRNG0 :1;
+unsigned CPSRNG1 :1;
+unsigned :2;
+unsigned CPSRM :1;
+unsigned CPSON :1;
+};
+struct {
+unsigned :2;
+unsigned CPSRNG :2;
+};
+} CPSCON0bits_t;
+extern volatile CPSCON0bits_t CPSCON0bits @ 0x01E;
+
+# 935
+extern volatile unsigned char CPSCON1 @ 0x01F;
+
+asm("CPSCON1 equ 01Fh");
+
+
+typedef union {
+struct {
+unsigned CPSCH0 :1;
+unsigned CPSCH1 :1;
+};
+struct {
+unsigned CPSCH :2;
+};
+} CPSCON1bits_t;
+extern volatile CPSCON1bits_t CPSCON1bits @ 0x01F;
+
+# 968
+extern volatile unsigned char TRISA @ 0x08C;
+
+asm("TRISA equ 08Ch");
+
+
+typedef union {
+struct {
+unsigned TRISA0 :1;
+unsigned TRISA1 :1;
+unsigned TRISA2 :1;
+unsigned TRISA3 :1;
+unsigned TRISA4 :1;
+unsigned TRISA5 :1;
+};
+} TRISAbits_t;
+extern volatile TRISAbits_t TRISAbits @ 0x08C;
+
+# 1017
+extern volatile unsigned char PIE1 @ 0x091;
+
+asm("PIE1 equ 091h");
+
+
+typedef union {
+struct {
+unsigned TMR1IE :1;
+unsigned TMR2IE :1;
+unsigned CCP1IE :1;
+unsigned SSP1IE :1;
+unsigned TXIE :1;
+unsigned RCIE :1;
+unsigned ADIE :1;
+unsigned TMR1GIE :1;
+};
+} PIE1bits_t;
+extern volatile PIE1bits_t PIE1bits @ 0x091;
+
+# 1078
+extern volatile unsigned char PIE2 @ 0x092;
+
+asm("PIE2 equ 092h");
+
+
+typedef union {
+struct {
+unsigned :3;
+unsigned BCL1IE :1;
+unsigned EEIE :1;
+unsigned C1IE :1;
+unsigned :1;
+unsigned OSFIE :1;
+};
+} PIE2bits_t;
+extern volatile PIE2bits_t PIE2bits @ 0x092;
+
+# 1117
+extern volatile unsigned char OPTION_REG @ 0x095;
+
+asm("OPTION_REG equ 095h");
+
+
+typedef union {
+struct {
+unsigned PS0 :1;
+unsigned PS1 :1;
+unsigned PS2 :1;
+unsigned PSA :1;
+unsigned TMR0SE :1;
+unsigned TMR0CS :1;
+unsigned INTEDG :1;
+unsigned nWPUEN :1;
+};
+struct {
+unsigned PS :3;
+unsigned :1;
+unsigned T0SE :1;
+unsigned T0CS :1;
+};
+} OPTION_REGbits_t;
+extern volatile OPTION_REGbits_t OPTION_REGbits @ 0x095;
+
+# 1199
+extern volatile unsigned char PCON @ 0x096;
+
+asm("PCON equ 096h");
+
+
+typedef union {
+struct {
+unsigned nBOR :1;
+unsigned nPOR :1;
+unsigned nRI :1;
+unsigned nRMCLR :1;
+unsigned :2;
+unsigned STKUNF :1;
+unsigned STKOVF :1;
+};
+} PCONbits_t;
+extern volatile PCONbits_t PCONbits @ 0x096;
+
+# 1249
+extern volatile unsigned char WDTCON @ 0x097;
+
+asm("WDTCON equ 097h");
+
+
+typedef union {
+struct {
+unsigned SWDTEN :1;
+unsigned WDTPS0 :1;
+unsigned WDTPS1 :1;
+unsigned WDTPS2 :1;
+unsigned WDTPS3 :1;
+unsigned WDTPS4 :1;
+};
+struct {
+unsigned :1;
+unsigned WDTPS :5;
+};
+} WDTCONbits_t;
+extern volatile WDTCONbits_t WDTCONbits @ 0x097;
+
+# 1307
+extern volatile unsigned char OSCTUNE @ 0x098;
+
+asm("OSCTUNE equ 098h");
+
+
+typedef union {
+struct {
+unsigned TUN0 :1;
+unsigned TUN1 :1;
+unsigned TUN2 :1;
+unsigned TUN3 :1;
+unsigned TUN4 :1;
+unsigned TUN5 :1;
+};
+struct {
+unsigned TUN :6;
+};
+} OSCTUNEbits_t;
+extern volatile OSCTUNEbits_t OSCTUNEbits @ 0x098;
+
+# 1364
+extern volatile unsigned char OSCCON @ 0x099;
+
+asm("OSCCON equ 099h");
+
+
+typedef union {
+struct {
+unsigned SCS0 :1;
+unsigned SCS1 :1;
+unsigned :1;
+unsigned IRCF0 :1;
+unsigned IRCF1 :1;
+unsigned IRCF2 :1;
+unsigned IRCF3 :1;
+unsigned SPLLEN :1;
+};
+struct {
+unsigned SCS :2;
+unsigned :1;
+unsigned IRCF :4;
+};
+} OSCCONbits_t;
+extern volatile OSCCONbits_t OSCCONbits @ 0x099;
+
+# 1435
+extern volatile unsigned char OSCSTAT @ 0x09A;
+
+asm("OSCSTAT equ 09Ah");
+
+
+typedef union {
+struct {
+unsigned HFIOFS :1;
+unsigned LFIOFR :1;
+unsigned MFIOFR :1;
+unsigned HFIOFL :1;
+unsigned HFIOFR :1;
+unsigned OSTS :1;
+unsigned PLLR :1;
+unsigned T1OSCR :1;
+};
+} OSCSTATbits_t;
+extern volatile OSCSTATbits_t OSCSTATbits @ 0x09A;
+
+# 1496
+extern volatile unsigned short ADRES @ 0x09B;
+
+asm("ADRES equ 09Bh");
+
+
+
+extern volatile unsigned char ADRESL @ 0x09B;
+
+asm("ADRESL equ 09Bh");
+
+
+typedef union {
+struct {
+unsigned ADRESL :8;
+};
+} ADRESLbits_t;
+extern volatile ADRESLbits_t ADRESLbits @ 0x09B;
+
+# 1521
+extern volatile unsigned char ADRESH @ 0x09C;
+
+asm("ADRESH equ 09Ch");
+
+
+typedef union {
+struct {
+unsigned ADRESH :8;
+};
+} ADRESHbits_t;
+extern volatile ADRESHbits_t ADRESHbits @ 0x09C;
+
+# 1540
+extern volatile unsigned char ADCON0 @ 0x09D;
+
+asm("ADCON0 equ 09Dh");
+
+
+typedef union {
+struct {
+unsigned ADON :1;
+unsigned GO_nDONE :1;
+unsigned CHS0 :1;
+unsigned CHS1 :1;
+unsigned CHS2 :1;
+unsigned CHS3 :1;
+unsigned CHS4 :1;
+};
+struct {
+unsigned :1;
+unsigned ADGO :1;
+unsigned CHS :5;
+};
+struct {
+unsigned :1;
+unsigned GO :1;
+};
+} ADCON0bits_t;
+extern volatile ADCON0bits_t ADCON0bits @ 0x09D;
+
+# 1619
+extern volatile unsigned char ADCON1 @ 0x09E;
+
+asm("ADCON1 equ 09Eh");
+
+
+typedef union {
+struct {
+unsigned ADPREF0 :1;
+unsigned ADPREF1 :1;
+unsigned :2;
+unsigned ADCS0 :1;
+unsigned ADCS1 :1;
+unsigned ADCS2 :1;
+unsigned ADFM :1;
+};
+struct {
+unsigned ADPREF :2;
+unsigned :2;
+unsigned ADCS :3;
+};
+} ADCON1bits_t;
+extern volatile ADCON1bits_t ADCON1bits @ 0x09E;
+
+# 1684
+extern volatile unsigned char LATA @ 0x10C;
+
+asm("LATA equ 010Ch");
+
+
+typedef union {
+struct {
+unsigned LATA0 :1;
+unsigned LATA1 :1;
+unsigned LATA2 :1;
+unsigned :1;
+unsigned LATA4 :1;
+unsigned LATA5 :1;
+};
+} LATAbits_t;
+extern volatile LATAbits_t LATAbits @ 0x10C;
+
+# 1728
+extern volatile unsigned char CM1CON0 @ 0x111;
+
+asm("CM1CON0 equ 0111h");
+
+
+typedef union {
+struct {
+unsigned C1SYNC :1;
+unsigned C1HYS :1;
+unsigned C1SP :1;
+unsigned :1;
+unsigned C1POL :1;
+unsigned C1OE :1;
+unsigned C1OUT :1;
+unsigned C1ON :1;
+};
+} CM1CON0bits_t;
+extern volatile CM1CON0bits_t CM1CON0bits @ 0x111;
+
+# 1784
+extern volatile unsigned char CM1CON1 @ 0x112;
+
+asm("CM1CON1 equ 0112h");
+
+
+typedef union {
+struct {
+unsigned C1NCH :1;
+unsigned :3;
+unsigned C1PCH0 :1;
+unsigned C1PCH1 :1;
+unsigned C1INTN :1;
+unsigned C1INTP :1;
+};
+struct {
+unsigned C1NCH0 :1;
+unsigned :3;
+unsigned C1PCH :2;
+};
+} CM1CON1bits_t;
+extern volatile CM1CON1bits_t CM1CON1bits @ 0x112;
+
+# 1843
+extern volatile unsigned char CMOUT @ 0x115;
+
+asm("CMOUT equ 0115h");
+
+
+typedef union {
+struct {
+unsigned MC1OUT :1;
+};
+} CMOUTbits_t;
+extern volatile CMOUTbits_t CMOUTbits @ 0x115;
+
+# 1862
+extern volatile unsigned char BORCON @ 0x116;
+
+asm("BORCON equ 0116h");
+
+
+typedef union {
+struct {
+unsigned BORRDY :1;
+unsigned :5;
+unsigned BORFS :1;
+unsigned SBOREN :1;
+};
+} BORCONbits_t;
+extern volatile BORCONbits_t BORCONbits @ 0x116;
+
+# 1894
+extern volatile unsigned char FVRCON @ 0x117;
+
+asm("FVRCON equ 0117h");
+
+
+typedef union {
+struct {
+unsigned ADFVR0 :1;
+unsigned ADFVR1 :1;
+unsigned CDAFVR0 :1;
+unsigned CDAFVR1 :1;
+unsigned TSRNG :1;
+unsigned TSEN :1;
+unsigned FVRRDY :1;
+unsigned FVREN :1;
+};
+struct {
+unsigned ADFVR :2;
+unsigned CDAFVR :2;
+};
+} FVRCONbits_t;
+extern volatile FVRCONbits_t FVRCONbits @ 0x117;
+
+# 1969
+extern volatile unsigned char DACCON0 @ 0x118;
+
+asm("DACCON0 equ 0118h");
+
+
+typedef union {
+struct {
+unsigned :2;
+unsigned DACPSS0 :1;
+unsigned DACPSS1 :1;
+unsigned :1;
+unsigned DACOE :1;
+unsigned DACLPS :1;
+unsigned DACEN :1;
+};
+struct {
+unsigned :2;
+unsigned DACPSS :2;
+};
+} DACCON0bits_t;
+extern volatile DACCON0bits_t DACCON0bits @ 0x118;
+
+# 2023
+extern volatile unsigned char DACCON1 @ 0x119;
+
+asm("DACCON1 equ 0119h");
+
+
+typedef union {
+struct {
+unsigned DACR0 :1;
+unsigned DACR1 :1;
+unsigned DACR2 :1;
+unsigned DACR3 :1;
+unsigned DACR4 :1;
+};
+struct {
+unsigned DACR :5;
+};
+} DACCON1bits_t;
+extern volatile DACCON1bits_t DACCON1bits @ 0x119;
+
+# 2074
+extern volatile unsigned char SRCON0 @ 0x11A;
+
+asm("SRCON0 equ 011Ah");
+
+
+typedef union {
+struct {
+unsigned SRPR :1;
+unsigned SRPS :1;
+unsigned SRNQEN :1;
+unsigned SRQEN :1;
+unsigned SRCLK0 :1;
+unsigned SRCLK1 :1;
+unsigned SRCLK2 :1;
+unsigned SRLEN :1;
+};
+struct {
+unsigned :4;
+unsigned SRCLK :3;
+};
+} SRCON0bits_t;
+extern volatile SRCON0bits_t SRCON0bits @ 0x11A;
+
+# 2144
+extern volatile unsigned char SRCON1 @ 0x11B;
+
+asm("SRCON1 equ 011Bh");
+
+
+typedef union {
+struct {
+unsigned SRRC1E :1;
+unsigned :1;
+unsigned SRRCKE :1;
+unsigned SRRPE :1;
+unsigned SRSC1E :1;
+unsigned :1;
+unsigned SRSCKE :1;
+unsigned SRSPE :1;
+};
+} SRCON1bits_t;
+extern volatile SRCON1bits_t SRCON1bits @ 0x11B;
+
+# 2195
+extern volatile unsigned char APFCON @ 0x11D;
+
+asm("APFCON equ 011Dh");
+
+
+extern volatile unsigned char APFCON0 @ 0x11D;
+
+asm("APFCON0 equ 011Dh");
+
+
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCONbits_t;
+extern volatile APFCONbits_t APFCONbits @ 0x11D;
+
+# 2270
+typedef union {
+struct {
+unsigned CCP1SEL :1;
+unsigned P1BSEL :1;
+unsigned TXCKSEL :1;
+unsigned T1GSEL :1;
+unsigned :1;
+unsigned SSSEL :1;
+unsigned SDOSEL :1;
+unsigned RXDTSEL :1;
+};
+struct {
+unsigned :5;
+unsigned SS1SEL :1;
+unsigned SDO1SEL :1;
+};
+} APFCON0bits_t;
+extern volatile APFCON0bits_t APFCON0bits @ 0x11D;
+
+# 2336
+extern volatile unsigned char ANSELA @ 0x18C;
+
+asm("ANSELA equ 018Ch");
+
+
+typedef union {
+struct {
+unsigned ANSA0 :1;
+unsigned ANSA1 :1;
+unsigned ANSA2 :1;
+unsigned :1;
+unsigned ANSA4 :1;
+};
+struct {
+unsigned ANSELA :5;
+};
+} ANSELAbits_t;
+extern volatile ANSELAbits_t ANSELAbits @ 0x18C;
+
+# 2382
+extern volatile unsigned short EEADR @ 0x191;
+
+asm("EEADR equ 0191h");
+
+
+
+extern volatile unsigned char EEADRL @ 0x191;
+
+asm("EEADRL equ 0191h");
+
+
+typedef union {
+struct {
+unsigned EEADRL :8;
+};
+} EEADRLbits_t;
+extern volatile EEADRLbits_t EEADRLbits @ 0x191;
+
+# 2407
+extern volatile unsigned char EEADRH @ 0x192;
+
+asm("EEADRH equ 0192h");
+
+
+typedef union {
+struct {
+unsigned EEADRH :7;
+};
+} EEADRHbits_t;
+extern volatile EEADRHbits_t EEADRHbits @ 0x192;
+
+# 2426
+extern volatile unsigned short EEDAT @ 0x193;
+
+asm("EEDAT equ 0193h");
+
+
+
+extern volatile unsigned char EEDATL @ 0x193;
+
+asm("EEDATL equ 0193h");
+
+
+extern volatile unsigned char EEDATA @ 0x193;
+
+asm("EEDATA equ 0193h");
+
+
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATLbits_t;
+extern volatile EEDATLbits_t EEDATLbits @ 0x193;
+
+# 2455
+typedef union {
+struct {
+unsigned EEDATL :8;
+};
+} EEDATAbits_t;
+extern volatile EEDATAbits_t EEDATAbits @ 0x193;
+
+# 2469
+extern volatile unsigned char EEDATH @ 0x194;
+
+asm("EEDATH equ 0194h");
+
+
+typedef union {
+struct {
+unsigned EEDATH :6;
+};
+} EEDATHbits_t;
+extern volatile EEDATHbits_t EEDATHbits @ 0x194;
+
+# 2488
+extern volatile unsigned char EECON1 @ 0x195;
+
+asm("EECON1 equ 0195h");
+
+
+typedef union {
+struct {
+unsigned RD :1;
+unsigned WR :1;
+unsigned WREN :1;
+unsigned WRERR :1;
+unsigned FREE :1;
+unsigned LWLO :1;
+unsigned CFGS :1;
+unsigned EEPGD :1;
+};
+} EECON1bits_t;
+extern volatile EECON1bits_t EECON1bits @ 0x195;
+
+# 2549
+extern volatile unsigned char EECON2 @ 0x196;
+
+asm("EECON2 equ 0196h");
+
+
+typedef union {
+struct {
+unsigned EECON2 :8;
+};
+} EECON2bits_t;
+extern volatile EECON2bits_t EECON2bits @ 0x196;
+
+# 2568
+extern volatile unsigned char VREGCON @ 0x197;
+
+asm("VREGCON equ 0197h");
+
+
+typedef union {
+struct {
+unsigned VREGPM0 :1;
+unsigned VREGPM1 :1;
+};
+struct {
+unsigned VREGPM :2;
+};
+} VREGCONbits_t;
+extern volatile VREGCONbits_t VREGCONbits @ 0x197;
+
+# 2601
+extern volatile unsigned char RCREG @ 0x199;
+
+asm("RCREG equ 0199h");
+
+
+typedef union {
+struct {
+unsigned RCREG :8;
+};
+} RCREGbits_t;
+extern volatile RCREGbits_t RCREGbits @ 0x199;
+
+# 2620
+extern volatile unsigned char TXREG @ 0x19A;
+
+asm("TXREG equ 019Ah");
+
+
+typedef union {
+struct {
+unsigned TXREG :8;
+};
+} TXREGbits_t;
+extern volatile TXREGbits_t TXREGbits @ 0x19A;
+
+# 2639
+extern volatile unsigned char SPBRGL @ 0x19B;
+
+asm("SPBRGL equ 019Bh");
+
+
+extern volatile unsigned char SPBRG @ 0x19B;
+
+asm("SPBRG equ 019Bh");
+
+
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGLbits_t;
+extern volatile SPBRGLbits_t SPBRGLbits @ 0x19B;
+
+# 2662
+typedef union {
+struct {
+unsigned SPBRGL :8;
+};
+} SPBRGbits_t;
+extern volatile SPBRGbits_t SPBRGbits @ 0x19B;
+
+# 2676
+extern volatile unsigned char SPBRGH @ 0x19C;
+
+asm("SPBRGH equ 019Ch");
+
+
+typedef union {
+struct {
+unsigned SPBRGH :8;
+};
+} SPBRGHbits_t;
+extern volatile SPBRGHbits_t SPBRGHbits @ 0x19C;
+
+# 2695
+extern volatile unsigned char RCSTA @ 0x19D;
+
+asm("RCSTA equ 019Dh");
+
+
+typedef union {
+struct {
+unsigned RX9D :1;
+unsigned OERR :1;
+unsigned FERR :1;
+unsigned ADDEN :1;
+unsigned CREN :1;
+unsigned SREN :1;
+unsigned RX9 :1;
+unsigned SPEN :1;
+};
+} RCSTAbits_t;
+extern volatile RCSTAbits_t RCSTAbits @ 0x19D;
+
+# 2756
+extern volatile unsigned char TXSTA @ 0x19E;
+
+asm("TXSTA equ 019Eh");
+
+
+typedef union {
+struct {
+unsigned TX9D :1;
+unsigned TRMT :1;
+unsigned BRGH :1;
+unsigned SENDB :1;
+unsigned SYNC :1;
+unsigned TXEN :1;
+unsigned TX9 :1;
+unsigned CSRC :1;
+};
+} TXSTAbits_t;
+extern volatile TXSTAbits_t TXSTAbits @ 0x19E;
+
+# 2817
+extern volatile unsigned char BAUDCON @ 0x19F;
+
+asm("BAUDCON equ 019Fh");
+
+
+typedef union {
+struct {
+unsigned ABDEN :1;
+unsigned WUE :1;
+unsigned :1;
+unsigned BRG16 :1;
+unsigned SCKP :1;
+unsigned :1;
+unsigned RCIDL :1;
+unsigned ABDOVF :1;
+};
+} BAUDCONbits_t;
+extern volatile BAUDCONbits_t BAUDCONbits @ 0x19F;
+
+# 2868
+extern volatile unsigned char WPUA @ 0x20C;
+
+asm("WPUA equ 020Ch");
+
+
+typedef union {
+struct {
+unsigned WPUA0 :1;
+unsigned WPUA1 :1;
+unsigned WPUA2 :1;
+unsigned WPUA3 :1;
+unsigned WPUA4 :1;
+unsigned WPUA5 :1;
+};
+struct {
+unsigned WPUA :6;
+};
+} WPUAbits_t;
+extern volatile WPUAbits_t WPUAbits @ 0x20C;
+
+# 2925
+extern volatile unsigned char SSP1BUF @ 0x211;
+
+asm("SSP1BUF equ 0211h");
+
+
+extern volatile unsigned char SSPBUF @ 0x211;
+
+asm("SSPBUF equ 0211h");
+
+
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSP1BUFbits_t;
+extern volatile SSP1BUFbits_t SSP1BUFbits @ 0x211;
+
+# 2948
+typedef union {
+struct {
+unsigned SSPBUF :8;
+};
+} SSPBUFbits_t;
+extern volatile SSPBUFbits_t SSPBUFbits @ 0x211;
+
+# 2962
+extern volatile unsigned char SSP1ADD @ 0x212;
+
+asm("SSP1ADD equ 0212h");
+
+
+extern volatile unsigned char SSPADD @ 0x212;
+
+asm("SSPADD equ 0212h");
+
+
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSP1ADDbits_t;
+extern volatile SSP1ADDbits_t SSP1ADDbits @ 0x212;
+
+# 2985
+typedef union {
+struct {
+unsigned SSPADD :8;
+};
+} SSPADDbits_t;
+extern volatile SSPADDbits_t SSPADDbits @ 0x212;
+
+# 2999
+extern volatile unsigned char SSP1MSK @ 0x213;
+
+asm("SSP1MSK equ 0213h");
+
+
+extern volatile unsigned char SSPMSK @ 0x213;
+
+asm("SSPMSK equ 0213h");
+
+
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSP1MSKbits_t;
+extern volatile SSP1MSKbits_t SSP1MSKbits @ 0x213;
+
+# 3022
+typedef union {
+struct {
+unsigned SSPMSK :8;
+};
+} SSPMSKbits_t;
+extern volatile SSPMSKbits_t SSPMSKbits @ 0x213;
+
+# 3036
+extern volatile unsigned char SSP1STAT @ 0x214;
+
+asm("SSP1STAT equ 0214h");
+
+
+extern volatile unsigned char SSPSTAT @ 0x214;
+
+asm("SSPSTAT equ 0214h");
+
+
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSP1STATbits_t;
+extern volatile SSP1STATbits_t SSP1STATbits @ 0x214;
+
+# 3101
+typedef union {
+struct {
+unsigned BF :1;
+unsigned UA :1;
+unsigned R_nW :1;
+unsigned S :1;
+unsigned P :1;
+unsigned D_nA :1;
+unsigned CKE :1;
+unsigned SMP :1;
+};
+} SSPSTATbits_t;
+extern volatile SSPSTATbits_t SSPSTATbits @ 0x214;
+
+# 3157
+extern volatile unsigned char SSP1CON1 @ 0x215;
+
+asm("SSP1CON1 equ 0215h");
+
+
+extern volatile unsigned char SSPCON1 @ 0x215;
+
+asm("SSPCON1 equ 0215h");
+
+extern volatile unsigned char SSPCON @ 0x215;
+
+asm("SSPCON equ 0215h");
+
+
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSP1CON1bits_t;
+extern volatile SSP1CON1bits_t SSP1CON1bits @ 0x215;
+
+# 3234
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCON1bits_t;
+extern volatile SSPCON1bits_t SSPCON1bits @ 0x215;
+
+# 3296
+typedef union {
+struct {
+unsigned SSPM0 :1;
+unsigned SSPM1 :1;
+unsigned SSPM2 :1;
+unsigned SSPM3 :1;
+unsigned CKP :1;
+unsigned SSPEN :1;
+unsigned SSPOV :1;
+unsigned WCOL :1;
+};
+struct {
+unsigned SSPM :4;
+};
+} SSPCONbits_t;
+extern volatile SSPCONbits_t SSPCONbits @ 0x215;
+
+# 3360
+extern volatile unsigned char SSP1CON2 @ 0x216;
+
+asm("SSP1CON2 equ 0216h");
+
+
+extern volatile unsigned char SSPCON2 @ 0x216;
+
+asm("SSPCON2 equ 0216h");
+
+
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSP1CON2bits_t;
+extern volatile SSP1CON2bits_t SSP1CON2bits @ 0x216;
+
+# 3425
+typedef union {
+struct {
+unsigned SEN :1;
+unsigned RSEN :1;
+unsigned PEN :1;
+unsigned RCEN :1;
+unsigned ACKEN :1;
+unsigned ACKDT :1;
+unsigned ACKSTAT :1;
+unsigned GCEN :1;
+};
+} SSPCON2bits_t;
+extern volatile SSPCON2bits_t SSPCON2bits @ 0x216;
+
+# 3481
+extern volatile unsigned char SSP1CON3 @ 0x217;
+
+asm("SSP1CON3 equ 0217h");
+
+
+extern volatile unsigned char SSPCON3 @ 0x217;
+
+asm("SSPCON3 equ 0217h");
+
+
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSP1CON3bits_t;
+extern volatile SSP1CON3bits_t SSP1CON3bits @ 0x217;
+
+# 3546
+typedef union {
+struct {
+unsigned DHEN :1;
+unsigned AHEN :1;
+unsigned SBCDE :1;
+unsigned SDAHT :1;
+unsigned BOEN :1;
+unsigned SCIE :1;
+unsigned PCIE :1;
+unsigned ACKTIM :1;
+};
+} SSPCON3bits_t;
+extern volatile SSPCON3bits_t SSPCON3bits @ 0x217;
+
+# 3602
+extern volatile unsigned char CCPR1L @ 0x291;
+
+asm("CCPR1L equ 0291h");
+
+
+typedef union {
+struct {
+unsigned CCPR1L :8;
+};
+} CCPR1Lbits_t;
+extern volatile CCPR1Lbits_t CCPR1Lbits @ 0x291;
+
+# 3621
+extern volatile unsigned char CCPR1H @ 0x292;
+
+asm("CCPR1H equ 0292h");
+
+
+typedef union {
+struct {
+unsigned CCPR1H :8;
+};
+} CCPR1Hbits_t;
+extern volatile CCPR1Hbits_t CCPR1Hbits @ 0x292;
+
+# 3640
+extern volatile unsigned char CCP1CON @ 0x293;
+
+asm("CCP1CON equ 0293h");
+
+
+typedef union {
+struct {
+unsigned CCP1M0 :1;
+unsigned CCP1M1 :1;
+unsigned CCP1M2 :1;
+unsigned CCP1M3 :1;
+unsigned DC1B0 :1;
+unsigned DC1B1 :1;
+unsigned P1M0 :1;
+unsigned P1M1 :1;
+};
+struct {
+unsigned CCP1M :4;
+unsigned DC1B :2;
+unsigned P1M :2;
+};
+} CCP1CONbits_t;
+extern volatile CCP1CONbits_t CCP1CONbits @ 0x293;
+
+# 3721
+extern volatile unsigned char PWM1CON @ 0x294;
+
+asm("PWM1CON equ 0294h");
+
+
+typedef union {
+struct {
+unsigned P1DC0 :1;
+unsigned P1DC1 :1;
+unsigned P1DC2 :1;
+unsigned P1DC3 :1;
+unsigned P1DC4 :1;
+unsigned P1DC5 :1;
+unsigned P1DC6 :1;
+unsigned P1RSEN :1;
+};
+struct {
+unsigned P1DC :7;
+};
+} PWM1CONbits_t;
+extern volatile PWM1CONbits_t PWM1CONbits @ 0x294;
+
+# 3790
+extern volatile unsigned char CCP1AS @ 0x295;
+
+asm("CCP1AS equ 0295h");
+
+
+extern volatile unsigned char ECCP1AS @ 0x295;
+
+asm("ECCP1AS equ 0295h");
+
+
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} CCP1ASbits_t;
+extern volatile CCP1ASbits_t CCP1ASbits @ 0x295;
+
+# 3875
+typedef union {
+struct {
+unsigned PSS1BD0 :1;
+unsigned PSS1BD1 :1;
+unsigned PSS1AC0 :1;
+unsigned PSS1AC1 :1;
+unsigned CCP1AS0 :1;
+unsigned CCP1AS1 :1;
+unsigned CCP1AS2 :1;
+unsigned CCP1ASE :1;
+};
+struct {
+unsigned PSS1BD :2;
+unsigned PSS1AC :2;
+unsigned CCP1AS :3;
+};
+} ECCP1ASbits_t;
+extern volatile ECCP1ASbits_t ECCP1ASbits @ 0x295;
+
+# 3951
+extern volatile unsigned char PSTR1CON @ 0x296;
+
+asm("PSTR1CON equ 0296h");
+
+
+typedef union {
+struct {
+unsigned STR1A :1;
+unsigned STR1B :1;
+unsigned :1;
+unsigned :1;
+unsigned STR1SYNC :1;
+};
+} PSTR1CONbits_t;
+extern volatile PSTR1CONbits_t PSTR1CONbits @ 0x296;
+
+# 3984
+extern volatile unsigned char IOCAP @ 0x391;
+
+asm("IOCAP equ 0391h");
+
+
+typedef union {
+struct {
+unsigned IOCAP0 :1;
+unsigned IOCAP1 :1;
+unsigned IOCAP2 :1;
+unsigned IOCAP3 :1;
+unsigned IOCAP4 :1;
+unsigned IOCAP5 :1;
+};
+struct {
+unsigned IOCAP :6;
+};
+} IOCAPbits_t;
+extern volatile IOCAPbits_t IOCAPbits @ 0x391;
+
+# 4041
+extern volatile unsigned char IOCAN @ 0x392;
+
+asm("IOCAN equ 0392h");
+
+
+typedef union {
+struct {
+unsigned IOCAN0 :1;
+unsigned IOCAN1 :1;
+unsigned IOCAN2 :1;
+unsigned IOCAN3 :1;
+unsigned IOCAN4 :1;
+unsigned IOCAN5 :1;
+};
+struct {
+unsigned IOCAN :6;
+};
+} IOCANbits_t;
+extern volatile IOCANbits_t IOCANbits @ 0x392;
+
+# 4098
+extern volatile unsigned char IOCAF @ 0x393;
+
+asm("IOCAF equ 0393h");
+
+
+typedef union {
+struct {
+unsigned IOCAF0 :1;
+unsigned IOCAF1 :1;
+unsigned IOCAF2 :1;
+unsigned IOCAF3 :1;
+unsigned IOCAF4 :1;
+unsigned IOCAF5 :1;
+};
+struct {
+unsigned IOCAF :6;
+};
+} IOCAFbits_t;
+extern volatile IOCAFbits_t IOCAFbits @ 0x393;
+
+# 4155
+extern volatile unsigned char CLKRCON @ 0x39A;
+
+asm("CLKRCON equ 039Ah");
+
+
+typedef union {
+struct {
+unsigned CLKRDIV0 :1;
+unsigned CLKRDIV1 :1;
+unsigned CLKRDIV2 :1;
+unsigned CLKRDC0 :1;
+unsigned CLKRDC1 :1;
+unsigned CLKRSLR :1;
+unsigned CLKROE :1;
+unsigned CLKREN :1;
+};
+struct {
+unsigned CLKRDIV :3;
+unsigned CLKRDC :2;
+};
+} CLKRCONbits_t;
+extern volatile CLKRCONbits_t CLKRCONbits @ 0x39A;
+
+# 4230
+extern volatile unsigned char MDCON @ 0x39C;
+
+asm("MDCON equ 039Ch");
+
+
+typedef union {
+struct {
+unsigned MDBIT :1;
+unsigned :2;
+unsigned MDOUT :1;
+unsigned MDOPOL :1;
+unsigned MDSLR :1;
+unsigned MDOE :1;
+unsigned MDEN :1;
+};
+} MDCONbits_t;
+extern volatile MDCONbits_t MDCONbits @ 0x39C;
+
+# 4280
+extern volatile unsigned char MDSRC @ 0x39D;
+
+asm("MDSRC equ 039Dh");
+
+
+typedef union {
+struct {
+unsigned MDMS0 :1;
+unsigned MDMS1 :1;
+unsigned MDMS2 :1;
+unsigned MDMS3 :1;
+unsigned :3;
+unsigned MDMSODIS :1;
+};
+struct {
+unsigned MDMS :4;
+};
+} MDSRCbits_t;
+extern volatile MDSRCbits_t MDSRCbits @ 0x39D;
+
+# 4332
+extern volatile unsigned char MDCARL @ 0x39E;
+
+asm("MDCARL equ 039Eh");
+
+
+typedef union {
+struct {
+unsigned MDCL0 :1;
+unsigned MDCL1 :1;
+unsigned MDCL2 :1;
+unsigned MDCL3 :1;
+unsigned :1;
+unsigned MDCLSYNC :1;
+unsigned MDCLPOL :1;
+unsigned MDCLODIS :1;
+};
+struct {
+unsigned MDCL :4;
+};
+} MDCARLbits_t;
+extern volatile MDCARLbits_t MDCARLbits @ 0x39E;
+
+# 4396
+extern volatile unsigned char MDCARH @ 0x39F;
+
+asm("MDCARH equ 039Fh");
+
+
+typedef union {
+struct {
+unsigned MDCH0 :1;
+unsigned MDCH1 :1;
+unsigned MDCH2 :1;
+unsigned MDCH3 :1;
+unsigned :1;
+unsigned MDCHSYNC :1;
+unsigned MDCHPOL :1;
+unsigned MDCHODIS :1;
+};
+struct {
+unsigned MDCH :4;
+};
+} MDCARHbits_t;
+extern volatile MDCARHbits_t MDCARHbits @ 0x39F;
+
+# 4460
+extern volatile unsigned char STATUS_SHAD @ 0xFE4;
+
+asm("STATUS_SHAD equ 0FE4h");
+
+
+typedef union {
+struct {
+unsigned C_SHAD :1;
+unsigned DC_SHAD :1;
+unsigned Z_SHAD :1;
+};
+} STATUS_SHADbits_t;
+extern volatile STATUS_SHADbits_t STATUS_SHADbits @ 0xFE4;
+
+# 4491
+extern volatile unsigned char WREG_SHAD @ 0xFE5;
+
+asm("WREG_SHAD equ 0FE5h");
+
+
+typedef union {
+struct {
+unsigned WREG_SHAD :8;
+};
+} WREG_SHADbits_t;
+extern volatile WREG_SHADbits_t WREG_SHADbits @ 0xFE5;
+
+# 4510
+extern volatile unsigned char BSR_SHAD @ 0xFE6;
+
+asm("BSR_SHAD equ 0FE6h");
+
+
+typedef union {
+struct {
+unsigned BSR_SHAD :5;
+};
+} BSR_SHADbits_t;
+extern volatile BSR_SHADbits_t BSR_SHADbits @ 0xFE6;
+
+# 4529
+extern volatile unsigned char PCLATH_SHAD @ 0xFE7;
+
+asm("PCLATH_SHAD equ 0FE7h");
+
+
+typedef union {
+struct {
+unsigned PCLATH_SHAD :7;
+};
+} PCLATH_SHADbits_t;
+extern volatile PCLATH_SHADbits_t PCLATH_SHADbits @ 0xFE7;
+
+# 4548
+extern volatile unsigned char FSR0L_SHAD @ 0xFE8;
+
+asm("FSR0L_SHAD equ 0FE8h");
+
+
+typedef union {
+struct {
+unsigned FSR0L_SHAD :8;
+};
+} FSR0L_SHADbits_t;
+extern volatile FSR0L_SHADbits_t FSR0L_SHADbits @ 0xFE8;
+
+# 4567
+extern volatile unsigned char FSR0H_SHAD @ 0xFE9;
+
+asm("FSR0H_SHAD equ 0FE9h");
+
+
+typedef union {
+struct {
+unsigned FSR0H_SHAD :8;
+};
+} FSR0H_SHADbits_t;
+extern volatile FSR0H_SHADbits_t FSR0H_SHADbits @ 0xFE9;
+
+# 4586
+extern volatile unsigned char FSR1L_SHAD @ 0xFEA;
+
+asm("FSR1L_SHAD equ 0FEAh");
+
+
+typedef union {
+struct {
+unsigned FSR1L_SHAD :8;
+};
+} FSR1L_SHADbits_t;
+extern volatile FSR1L_SHADbits_t FSR1L_SHADbits @ 0xFEA;
+
+# 4605
+extern volatile unsigned char FSR1H_SHAD @ 0xFEB;
+
+asm("FSR1H_SHAD equ 0FEBh");
+
+
+typedef union {
+struct {
+unsigned FSR1H_SHAD :8;
+};
+} FSR1H_SHADbits_t;
+extern volatile FSR1H_SHADbits_t FSR1H_SHADbits @ 0xFEB;
+
+# 4624
+extern volatile unsigned char STKPTR @ 0xFED;
+
+asm("STKPTR equ 0FEDh");
+
+
+typedef union {
+struct {
+unsigned STKPTR :5;
+};
+} STKPTRbits_t;
+extern volatile STKPTRbits_t STKPTRbits @ 0xFED;
+
+# 4643
+extern volatile unsigned char TOSL @ 0xFEE;
+
+asm("TOSL equ 0FEEh");
+
+
+typedef union {
+struct {
+unsigned TOSL :8;
+};
+} TOSLbits_t;
+extern volatile TOSLbits_t TOSLbits @ 0xFEE;
+
+# 4662
+extern volatile unsigned char TOSH @ 0xFEF;
+
+asm("TOSH equ 0FEFh");
+
+
+typedef union {
+struct {
+unsigned TOSH :7;
+};
+} TOSHbits_t;
+extern volatile TOSHbits_t TOSHbits @ 0xFEF;
+
+# 4687
+extern volatile __bit ABDEN @ (((unsigned) &BAUDCON)*8) + 0;
+
+extern volatile __bit ABDOVF @ (((unsigned) &BAUDCON)*8) + 7;
+
+extern volatile __bit ACKDT @ (((unsigned) &SSP1CON2)*8) + 5;
+
+extern volatile __bit ACKEN @ (((unsigned) &SSP1CON2)*8) + 4;
+
+extern volatile __bit ACKSTAT @ (((unsigned) &SSP1CON2)*8) + 6;
+
+extern volatile __bit ACKTIM @ (((unsigned) &SSP1CON3)*8) + 7;
+
+extern volatile __bit ADCS0 @ (((unsigned) &ADCON1)*8) + 4;
+
+extern volatile __bit ADCS1 @ (((unsigned) &ADCON1)*8) + 5;
+
+extern volatile __bit ADCS2 @ (((unsigned) &ADCON1)*8) + 6;
+
+extern volatile __bit ADDEN @ (((unsigned) &RCSTA)*8) + 3;
+
+extern volatile __bit ADFM @ (((unsigned) &ADCON1)*8) + 7;
+
+extern volatile __bit ADFVR0 @ (((unsigned) &FVRCON)*8) + 0;
+
+extern volatile __bit ADFVR1 @ (((unsigned) &FVRCON)*8) + 1;
+
+extern volatile __bit ADGO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit ADIE @ (((unsigned) &PIE1)*8) + 6;
+
+extern volatile __bit ADIF @ (((unsigned) &PIR1)*8) + 6;
+
+extern volatile __bit ADON @ (((unsigned) &ADCON0)*8) + 0;
+
+extern volatile __bit ADPREF0 @ (((unsigned) &ADCON1)*8) + 0;
+
+extern volatile __bit ADPREF1 @ (((unsigned) &ADCON1)*8) + 1;
+
+extern volatile __bit AHEN @ (((unsigned) &SSP1CON3)*8) + 1;
+
+extern volatile __bit ANSA0 @ (((unsigned) &ANSELA)*8) + 0;
+
+extern volatile __bit ANSA1 @ (((unsigned) &ANSELA)*8) + 1;
+
+extern volatile __bit ANSA2 @ (((unsigned) &ANSELA)*8) + 2;
+
+extern volatile __bit ANSA4 @ (((unsigned) &ANSELA)*8) + 4;
+
+extern volatile __bit BCL1IE @ (((unsigned) &PIE2)*8) + 3;
+
+extern volatile __bit BCL1IF @ (((unsigned) &PIR2)*8) + 3;
+
+extern volatile __bit BF @ (((unsigned) &SSP1STAT)*8) + 0;
+
+extern volatile __bit BOEN @ (((unsigned) &SSP1CON3)*8) + 4;
+
+extern volatile __bit BORFS @ (((unsigned) &BORCON)*8) + 6;
+
+extern volatile __bit BORRDY @ (((unsigned) &BORCON)*8) + 0;
+
+extern volatile __bit BRG16 @ (((unsigned) &BAUDCON)*8) + 3;
+
+extern volatile __bit BRGH @ (((unsigned) &TXSTA)*8) + 2;
+
+extern volatile __bit BSR0 @ (((unsigned) &BSR)*8) + 0;
+
+extern volatile __bit BSR1 @ (((unsigned) &BSR)*8) + 1;
+
+extern volatile __bit BSR2 @ (((unsigned) &BSR)*8) + 2;
+
+extern volatile __bit BSR3 @ (((unsigned) &BSR)*8) + 3;
+
+extern volatile __bit BSR4 @ (((unsigned) &BSR)*8) + 4;
+
+extern volatile __bit C1HYS @ (((unsigned) &CM1CON0)*8) + 1;
+
+extern volatile __bit C1IE @ (((unsigned) &PIE2)*8) + 5;
+
+extern volatile __bit C1IF @ (((unsigned) &PIR2)*8) + 5;
+
+extern volatile __bit C1INTN @ (((unsigned) &CM1CON1)*8) + 6;
+
+extern volatile __bit C1INTP @ (((unsigned) &CM1CON1)*8) + 7;
+
+extern volatile __bit C1NCH @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1NCH0 @ (((unsigned) &CM1CON1)*8) + 0;
+
+extern volatile __bit C1OE @ (((unsigned) &CM1CON0)*8) + 5;
+
+extern volatile __bit C1ON @ (((unsigned) &CM1CON0)*8) + 7;
+
+extern volatile __bit C1OUT @ (((unsigned) &CM1CON0)*8) + 6;
+
+extern volatile __bit C1PCH0 @ (((unsigned) &CM1CON1)*8) + 4;
+
+extern volatile __bit C1PCH1 @ (((unsigned) &CM1CON1)*8) + 5;
+
+extern volatile __bit C1POL @ (((unsigned) &CM1CON0)*8) + 4;
+
+extern volatile __bit C1SP @ (((unsigned) &CM1CON0)*8) + 2;
+
+extern volatile __bit C1SYNC @ (((unsigned) &CM1CON0)*8) + 0;
+
+extern volatile __bit CARRY @ (((unsigned) &STATUS)*8) + 0;
+
+extern volatile __bit CCP1AS0 @ (((unsigned) &CCP1AS)*8) + 4;
+
+extern volatile __bit CCP1AS1 @ (((unsigned) &CCP1AS)*8) + 5;
+
+extern volatile __bit CCP1AS2 @ (((unsigned) &CCP1AS)*8) + 6;
+
+extern volatile __bit CCP1ASE @ (((unsigned) &CCP1AS)*8) + 7;
+
+extern volatile __bit CCP1IE @ (((unsigned) &PIE1)*8) + 2;
+
+extern volatile __bit CCP1IF @ (((unsigned) &PIR1)*8) + 2;
+
+extern volatile __bit CCP1M0 @ (((unsigned) &CCP1CON)*8) + 0;
+
+extern volatile __bit CCP1M1 @ (((unsigned) &CCP1CON)*8) + 1;
+
+extern volatile __bit CCP1M2 @ (((unsigned) &CCP1CON)*8) + 2;
+
+extern volatile __bit CCP1M3 @ (((unsigned) &CCP1CON)*8) + 3;
+
+extern volatile __bit CCP1SEL @ (((unsigned) &APFCON)*8) + 0;
+
+extern volatile __bit CDAFVR0 @ (((unsigned) &FVRCON)*8) + 2;
+
+extern volatile __bit CDAFVR1 @ (((unsigned) &FVRCON)*8) + 3;
+
+extern volatile __bit CFGS @ (((unsigned) &EECON1)*8) + 6;
+
+extern volatile __bit CHS0 @ (((unsigned) &ADCON0)*8) + 2;
+
+extern volatile __bit CHS1 @ (((unsigned) &ADCON0)*8) + 3;
+
+extern volatile __bit CHS2 @ (((unsigned) &ADCON0)*8) + 4;
+
+extern volatile __bit CHS3 @ (((unsigned) &ADCON0)*8) + 5;
+
+extern volatile __bit CHS4 @ (((unsigned) &ADCON0)*8) + 6;
+
+extern volatile __bit CKE @ (((unsigned) &SSP1STAT)*8) + 6;
+
+extern volatile __bit CKP @ (((unsigned) &SSP1CON1)*8) + 4;
+
+extern volatile __bit CLKRDC0 @ (((unsigned) &CLKRCON)*8) + 3;
+
+extern volatile __bit CLKRDC1 @ (((unsigned) &CLKRCON)*8) + 4;
+
+extern volatile __bit CLKRDIV0 @ (((unsigned) &CLKRCON)*8) + 0;
+
+extern volatile __bit CLKRDIV1 @ (((unsigned) &CLKRCON)*8) + 1;
+
+extern volatile __bit CLKRDIV2 @ (((unsigned) &CLKRCON)*8) + 2;
+
+extern volatile __bit CLKREN @ (((unsigned) &CLKRCON)*8) + 7;
+
+extern volatile __bit CLKROE @ (((unsigned) &CLKRCON)*8) + 6;
+
+extern volatile __bit CLKRSLR @ (((unsigned) &CLKRCON)*8) + 5;
+
+extern volatile __bit CPSCH0 @ (((unsigned) &CPSCON1)*8) + 0;
+
+extern volatile __bit CPSCH1 @ (((unsigned) &CPSCON1)*8) + 1;
+
+extern volatile __bit CPSON @ (((unsigned) &CPSCON0)*8) + 7;
+
+extern volatile __bit CPSOUT @ (((unsigned) &CPSCON0)*8) + 1;
+
+extern volatile __bit CPSRM @ (((unsigned) &CPSCON0)*8) + 6;
+
+extern volatile __bit CPSRNG0 @ (((unsigned) &CPSCON0)*8) + 2;
+
+extern volatile __bit CPSRNG1 @ (((unsigned) &CPSCON0)*8) + 3;
+
+extern volatile __bit CREN @ (((unsigned) &RCSTA)*8) + 4;
+
+extern volatile __bit CSRC @ (((unsigned) &TXSTA)*8) + 7;
+
+extern volatile __bit C_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 0;
+
+extern volatile __bit DACEN @ (((unsigned) &DACCON0)*8) + 7;
+
+extern volatile __bit DACLPS @ (((unsigned) &DACCON0)*8) + 6;
+
+extern volatile __bit DACOE @ (((unsigned) &DACCON0)*8) + 5;
+
+extern volatile __bit DACPSS0 @ (((unsigned) &DACCON0)*8) + 2;
+
+extern volatile __bit DACPSS1 @ (((unsigned) &DACCON0)*8) + 3;
+
+extern volatile __bit DACR0 @ (((unsigned) &DACCON1)*8) + 0;
+
+extern volatile __bit DACR1 @ (((unsigned) &DACCON1)*8) + 1;
+
+extern volatile __bit DACR2 @ (((unsigned) &DACCON1)*8) + 2;
+
+extern volatile __bit DACR3 @ (((unsigned) &DACCON1)*8) + 3;
+
+extern volatile __bit DACR4 @ (((unsigned) &DACCON1)*8) + 4;
+
+extern volatile __bit DC @ (((unsigned) &STATUS)*8) + 1;
+
+extern volatile __bit DC1B0 @ (((unsigned) &CCP1CON)*8) + 4;
+
+extern volatile __bit DC1B1 @ (((unsigned) &CCP1CON)*8) + 5;
+
+extern volatile __bit DC_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 1;
+
+extern volatile __bit DHEN @ (((unsigned) &SSP1CON3)*8) + 0;
+
+extern volatile __bit D_nA @ (((unsigned) &SSP1STAT)*8) + 5;
+
+extern volatile __bit EEIE @ (((unsigned) &PIE2)*8) + 4;
+
+extern volatile __bit EEIF @ (((unsigned) &PIR2)*8) + 4;
+
+extern volatile __bit EEPGD @ (((unsigned) &EECON1)*8) + 7;
+
+extern volatile __bit FERR @ (((unsigned) &RCSTA)*8) + 2;
+
+extern volatile __bit FREE @ (((unsigned) &EECON1)*8) + 4;
+
+extern volatile __bit FVREN @ (((unsigned) &FVRCON)*8) + 7;
+
+extern volatile __bit FVRRDY @ (((unsigned) &FVRCON)*8) + 6;
+
+extern volatile __bit GCEN @ (((unsigned) &SSP1CON2)*8) + 7;
+
+extern volatile __bit GIE @ (((unsigned) &INTCON)*8) + 7;
+
+extern volatile __bit GO @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit GO_nDONE @ (((unsigned) &ADCON0)*8) + 1;
+
+extern volatile __bit HFIOFL @ (((unsigned) &OSCSTAT)*8) + 3;
+
+extern volatile __bit HFIOFR @ (((unsigned) &OSCSTAT)*8) + 4;
+
+extern volatile __bit HFIOFS @ (((unsigned) &OSCSTAT)*8) + 0;
+
+extern volatile __bit INTE @ (((unsigned) &INTCON)*8) + 4;
+
+extern volatile __bit INTEDG @ (((unsigned) &OPTION_REG)*8) + 6;
+
+extern volatile __bit INTF @ (((unsigned) &INTCON)*8) + 1;
+
+extern volatile __bit IOCAF0 @ (((unsigned) &IOCAF)*8) + 0;
+
+extern volatile __bit IOCAF1 @ (((unsigned) &IOCAF)*8) + 1;
+
+extern volatile __bit IOCAF2 @ (((unsigned) &IOCAF)*8) + 2;
+
+extern volatile __bit IOCAF3 @ (((unsigned) &IOCAF)*8) + 3;
+
+extern volatile __bit IOCAF4 @ (((unsigned) &IOCAF)*8) + 4;
+
+extern volatile __bit IOCAF5 @ (((unsigned) &IOCAF)*8) + 5;
+
+extern volatile __bit IOCAN0 @ (((unsigned) &IOCAN)*8) + 0;
+
+extern volatile __bit IOCAN1 @ (((unsigned) &IOCAN)*8) + 1;
+
+extern volatile __bit IOCAN2 @ (((unsigned) &IOCAN)*8) + 2;
+
+extern volatile __bit IOCAN3 @ (((unsigned) &IOCAN)*8) + 3;
+
+extern volatile __bit IOCAN4 @ (((unsigned) &IOCAN)*8) + 4;
+
+extern volatile __bit IOCAN5 @ (((unsigned) &IOCAN)*8) + 5;
+
+extern volatile __bit IOCAP0 @ (((unsigned) &IOCAP)*8) + 0;
+
+extern volatile __bit IOCAP1 @ (((unsigned) &IOCAP)*8) + 1;
+
+extern volatile __bit IOCAP2 @ (((unsigned) &IOCAP)*8) + 2;
+
+extern volatile __bit IOCAP3 @ (((unsigned) &IOCAP)*8) + 3;
+
+extern volatile __bit IOCAP4 @ (((unsigned) &IOCAP)*8) + 4;
+
+extern volatile __bit IOCAP5 @ (((unsigned) &IOCAP)*8) + 5;
+
+extern volatile __bit IOCIE @ (((unsigned) &INTCON)*8) + 3;
+
+extern volatile __bit IOCIF @ (((unsigned) &INTCON)*8) + 0;
+
+extern volatile __bit IRCF0 @ (((unsigned) &OSCCON)*8) + 3;
+
+extern volatile __bit IRCF1 @ (((unsigned) &OSCCON)*8) + 4;
+
+extern volatile __bit IRCF2 @ (((unsigned) &OSCCON)*8) + 5;
+
+extern volatile __bit IRCF3 @ (((unsigned) &OSCCON)*8) + 6;
+
+extern volatile __bit LATA0 @ (((unsigned) &LATA)*8) + 0;
+
+extern volatile __bit LATA1 @ (((unsigned) &LATA)*8) + 1;
+
+extern volatile __bit LATA2 @ (((unsigned) &LATA)*8) + 2;
+
+extern volatile __bit LATA4 @ (((unsigned) &LATA)*8) + 4;
+
+extern volatile __bit LATA5 @ (((unsigned) &LATA)*8) + 5;
+
+extern volatile __bit LFIOFR @ (((unsigned) &OSCSTAT)*8) + 1;
+
+extern volatile __bit LWLO @ (((unsigned) &EECON1)*8) + 5;
+
+extern volatile __bit MC1OUT @ (((unsigned) &CMOUT)*8) + 0;
+
+extern volatile __bit MDBIT @ (((unsigned) &MDCON)*8) + 0;
+
+extern volatile __bit MDCH0 @ (((unsigned) &MDCARH)*8) + 0;
+
+extern volatile __bit MDCH1 @ (((unsigned) &MDCARH)*8) + 1;
+
+extern volatile __bit MDCH2 @ (((unsigned) &MDCARH)*8) + 2;
+
+extern volatile __bit MDCH3 @ (((unsigned) &MDCARH)*8) + 3;
+
+extern volatile __bit MDCHODIS @ (((unsigned) &MDCARH)*8) + 7;
+
+extern volatile __bit MDCHPOL @ (((unsigned) &MDCARH)*8) + 6;
+
+extern volatile __bit MDCHSYNC @ (((unsigned) &MDCARH)*8) + 5;
+
+extern volatile __bit MDCL0 @ (((unsigned) &MDCARL)*8) + 0;
+
+extern volatile __bit MDCL1 @ (((unsigned) &MDCARL)*8) + 1;
+
+extern volatile __bit MDCL2 @ (((unsigned) &MDCARL)*8) + 2;
+
+extern volatile __bit MDCL3 @ (((unsigned) &MDCARL)*8) + 3;
+
+extern volatile __bit MDCLODIS @ (((unsigned) &MDCARL)*8) + 7;
+
+extern volatile __bit MDCLPOL @ (((unsigned) &MDCARL)*8) + 6;
+
+extern volatile __bit MDCLSYNC @ (((unsigned) &MDCARL)*8) + 5;
+
+extern volatile __bit MDEN @ (((unsigned) &MDCON)*8) + 7;
+
+extern volatile __bit MDMS0 @ (((unsigned) &MDSRC)*8) + 0;
+
+extern volatile __bit MDMS1 @ (((unsigned) &MDSRC)*8) + 1;
+
+extern volatile __bit MDMS2 @ (((unsigned) &MDSRC)*8) + 2;
+
+extern volatile __bit MDMS3 @ (((unsigned) &MDSRC)*8) + 3;
+
+extern volatile __bit MDMSODIS @ (((unsigned) &MDSRC)*8) + 7;
+
+extern volatile __bit MDOE @ (((unsigned) &MDCON)*8) + 6;
+
+extern volatile __bit MDOPOL @ (((unsigned) &MDCON)*8) + 4;
+
+extern volatile __bit MDOUT @ (((unsigned) &MDCON)*8) + 3;
+
+extern volatile __bit MDSLR @ (((unsigned) &MDCON)*8) + 5;
+
+extern volatile __bit MFIOFR @ (((unsigned) &OSCSTAT)*8) + 2;
+
+extern volatile __bit OERR @ (((unsigned) &RCSTA)*8) + 1;
+
+extern volatile __bit OSFIE @ (((unsigned) &PIE2)*8) + 7;
+
+extern volatile __bit OSFIF @ (((unsigned) &PIR2)*8) + 7;
+
+extern volatile __bit OSTS @ (((unsigned) &OSCSTAT)*8) + 5;
+
+extern volatile __bit P1BSEL @ (((unsigned) &APFCON)*8) + 1;
+
+extern volatile __bit P1DC0 @ (((unsigned) &PWM1CON)*8) + 0;
+
+extern volatile __bit P1DC1 @ (((unsigned) &PWM1CON)*8) + 1;
+
+extern volatile __bit P1DC2 @ (((unsigned) &PWM1CON)*8) + 2;
+
+extern volatile __bit P1DC3 @ (((unsigned) &PWM1CON)*8) + 3;
+
+extern volatile __bit P1DC4 @ (((unsigned) &PWM1CON)*8) + 4;
+
+extern volatile __bit P1DC5 @ (((unsigned) &PWM1CON)*8) + 5;
+
+extern volatile __bit P1DC6 @ (((unsigned) &PWM1CON)*8) + 6;
+
+extern volatile __bit P1M0 @ (((unsigned) &CCP1CON)*8) + 6;
+
+extern volatile __bit P1M1 @ (((unsigned) &CCP1CON)*8) + 7;
+
+extern volatile __bit P1RSEN @ (((unsigned) &PWM1CON)*8) + 7;
+
+extern volatile __bit PCIE @ (((unsigned) &SSP1CON3)*8) + 6;
+
+extern volatile __bit PEIE @ (((unsigned) &INTCON)*8) + 6;
+
+extern volatile __bit PEN @ (((unsigned) &SSP1CON2)*8) + 2;
+
+extern volatile __bit PLLR @ (((unsigned) &OSCSTAT)*8) + 6;
+
+extern volatile __bit PS0 @ (((unsigned) &OPTION_REG)*8) + 0;
+
+extern volatile __bit PS1 @ (((unsigned) &OPTION_REG)*8) + 1;
+
+extern volatile __bit PS2 @ (((unsigned) &OPTION_REG)*8) + 2;
+
+extern volatile __bit PSA @ (((unsigned) &OPTION_REG)*8) + 3;
+
+extern volatile __bit PSS1AC0 @ (((unsigned) &CCP1AS)*8) + 2;
+
+extern volatile __bit PSS1AC1 @ (((unsigned) &CCP1AS)*8) + 3;
+
+extern volatile __bit PSS1BD0 @ (((unsigned) &CCP1AS)*8) + 0;
+
+extern volatile __bit PSS1BD1 @ (((unsigned) &CCP1AS)*8) + 1;
+
+extern volatile __bit RA0 @ (((unsigned) &PORTA)*8) + 0;
+
+extern volatile __bit RA1 @ (((unsigned) &PORTA)*8) + 1;
+
+extern volatile __bit RA2 @ (((unsigned) &PORTA)*8) + 2;
+
+extern volatile __bit RA3 @ (((unsigned) &PORTA)*8) + 3;
+
+extern volatile __bit RA4 @ (((unsigned) &PORTA)*8) + 4;
+
+extern volatile __bit RA5 @ (((unsigned) &PORTA)*8) + 5;
+
+extern volatile __bit RCEN @ (((unsigned) &SSP1CON2)*8) + 3;
+
+extern volatile __bit RCIDL @ (((unsigned) &BAUDCON)*8) + 6;
+
+extern volatile __bit RCIE @ (((unsigned) &PIE1)*8) + 5;
+
+extern volatile __bit RCIF @ (((unsigned) &PIR1)*8) + 5;
+
+extern volatile __bit RD @ (((unsigned) &EECON1)*8) + 0;
+
+extern volatile __bit RSEN @ (((unsigned) &SSP1CON2)*8) + 1;
+
+extern volatile __bit RX9 @ (((unsigned) &RCSTA)*8) + 6;
+
+extern volatile __bit RX9D @ (((unsigned) &RCSTA)*8) + 0;
+
+extern volatile __bit RXDTSEL @ (((unsigned) &APFCON)*8) + 7;
+
+extern volatile __bit R_nW @ (((unsigned) &SSP1STAT)*8) + 2;
+
+extern volatile __bit SBCDE @ (((unsigned) &SSP1CON3)*8) + 2;
+
+extern volatile __bit SBOREN @ (((unsigned) &BORCON)*8) + 7;
+
+extern volatile __bit SCIE @ (((unsigned) &SSP1CON3)*8) + 5;
+
+extern volatile __bit SCKP @ (((unsigned) &BAUDCON)*8) + 4;
+
+extern volatile __bit SCS0 @ (((unsigned) &OSCCON)*8) + 0;
+
+extern volatile __bit SCS1 @ (((unsigned) &OSCCON)*8) + 1;
+
+extern volatile __bit SDAHT @ (((unsigned) &SSP1CON3)*8) + 3;
+
+extern volatile __bit SDO1SEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SDOSEL @ (((unsigned) &APFCON)*8) + 6;
+
+extern volatile __bit SEN @ (((unsigned) &SSP1CON2)*8) + 0;
+
+extern volatile __bit SENDB @ (((unsigned) &TXSTA)*8) + 3;
+
+extern volatile __bit SMP @ (((unsigned) &SSP1STAT)*8) + 7;
+
+extern volatile __bit SPEN @ (((unsigned) &RCSTA)*8) + 7;
+
+extern volatile __bit SPLLEN @ (((unsigned) &OSCCON)*8) + 7;
+
+extern volatile __bit SRCLK0 @ (((unsigned) &SRCON0)*8) + 4;
+
+extern volatile __bit SRCLK1 @ (((unsigned) &SRCON0)*8) + 5;
+
+extern volatile __bit SRCLK2 @ (((unsigned) &SRCON0)*8) + 6;
+
+extern volatile __bit SREN @ (((unsigned) &RCSTA)*8) + 5;
+
+extern volatile __bit SRLEN @ (((unsigned) &SRCON0)*8) + 7;
+
+extern volatile __bit SRNQEN @ (((unsigned) &SRCON0)*8) + 2;
+
+extern volatile __bit SRPR @ (((unsigned) &SRCON0)*8) + 0;
+
+extern volatile __bit SRPS @ (((unsigned) &SRCON0)*8) + 1;
+
+extern volatile __bit SRQEN @ (((unsigned) &SRCON0)*8) + 3;
+
+extern volatile __bit SRRC1E @ (((unsigned) &SRCON1)*8) + 0;
+
+extern volatile __bit SRRCKE @ (((unsigned) &SRCON1)*8) + 2;
+
+extern volatile __bit SRRPE @ (((unsigned) &SRCON1)*8) + 3;
+
+extern volatile __bit SRSC1E @ (((unsigned) &SRCON1)*8) + 4;
+
+extern volatile __bit SRSCKE @ (((unsigned) &SRCON1)*8) + 6;
+
+extern volatile __bit SRSPE @ (((unsigned) &SRCON1)*8) + 7;
+
+extern volatile __bit SS1SEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit SSP1IE @ (((unsigned) &PIE1)*8) + 3;
+
+extern volatile __bit SSP1IF @ (((unsigned) &PIR1)*8) + 3;
+
+extern volatile __bit SSPEN @ (((unsigned) &SSP1CON1)*8) + 5;
+
+extern volatile __bit SSPM0 @ (((unsigned) &SSP1CON1)*8) + 0;
+
+extern volatile __bit SSPM1 @ (((unsigned) &SSP1CON1)*8) + 1;
+
+extern volatile __bit SSPM2 @ (((unsigned) &SSP1CON1)*8) + 2;
+
+extern volatile __bit SSPM3 @ (((unsigned) &SSP1CON1)*8) + 3;
+
+extern volatile __bit SSPOV @ (((unsigned) &SSP1CON1)*8) + 6;
+
+extern volatile __bit SSSEL @ (((unsigned) &APFCON)*8) + 5;
+
+extern volatile __bit STKOVF @ (((unsigned) &PCON)*8) + 7;
+
+extern volatile __bit STKUNF @ (((unsigned) &PCON)*8) + 6;
+
+extern volatile __bit STR1A @ (((unsigned) &PSTR1CON)*8) + 0;
+
+extern volatile __bit STR1B @ (((unsigned) &PSTR1CON)*8) + 1;
+
+extern volatile __bit STR1SYNC @ (((unsigned) &PSTR1CON)*8) + 4;
+
+extern volatile __bit SWDTEN @ (((unsigned) &WDTCON)*8) + 0;
+
+extern volatile __bit SYNC @ (((unsigned) &TXSTA)*8) + 4;
+
+extern volatile __bit T0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit T0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit T0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit T0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit T0XCS @ (((unsigned) &CPSCON0)*8) + 0;
+
+extern volatile __bit T1CKPS0 @ (((unsigned) &T1CON)*8) + 4;
+
+extern volatile __bit T1CKPS1 @ (((unsigned) &T1CON)*8) + 5;
+
+extern volatile __bit T1GGO @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GGO_nDONE @ (((unsigned) &T1GCON)*8) + 3;
+
+extern volatile __bit T1GPOL @ (((unsigned) &T1GCON)*8) + 6;
+
+extern volatile __bit T1GSEL @ (((unsigned) &APFCON)*8) + 3;
+
+extern volatile __bit T1GSPM @ (((unsigned) &T1GCON)*8) + 4;
+
+extern volatile __bit T1GSS0 @ (((unsigned) &T1GCON)*8) + 0;
+
+extern volatile __bit T1GSS1 @ (((unsigned) &T1GCON)*8) + 1;
+
+extern volatile __bit T1GTM @ (((unsigned) &T1GCON)*8) + 5;
+
+extern volatile __bit T1GVAL @ (((unsigned) &T1GCON)*8) + 2;
+
+extern volatile __bit T1OSCEN @ (((unsigned) &T1CON)*8) + 3;
+
+extern volatile __bit T1OSCR @ (((unsigned) &OSCSTAT)*8) + 7;
+
+extern volatile __bit T2CKPS0 @ (((unsigned) &T2CON)*8) + 0;
+
+extern volatile __bit T2CKPS1 @ (((unsigned) &T2CON)*8) + 1;
+
+extern volatile __bit T2OUTPS0 @ (((unsigned) &T2CON)*8) + 3;
+
+extern volatile __bit T2OUTPS1 @ (((unsigned) &T2CON)*8) + 4;
+
+extern volatile __bit T2OUTPS2 @ (((unsigned) &T2CON)*8) + 5;
+
+extern volatile __bit T2OUTPS3 @ (((unsigned) &T2CON)*8) + 6;
+
+extern volatile __bit TMR0CS @ (((unsigned) &OPTION_REG)*8) + 5;
+
+extern volatile __bit TMR0IE @ (((unsigned) &INTCON)*8) + 5;
+
+extern volatile __bit TMR0IF @ (((unsigned) &INTCON)*8) + 2;
+
+extern volatile __bit TMR0SE @ (((unsigned) &OPTION_REG)*8) + 4;
+
+extern volatile __bit TMR1CS0 @ (((unsigned) &T1CON)*8) + 6;
+
+extern volatile __bit TMR1CS1 @ (((unsigned) &T1CON)*8) + 7;
+
+extern volatile __bit TMR1GE @ (((unsigned) &T1GCON)*8) + 7;
+
+extern volatile __bit TMR1GIE @ (((unsigned) &PIE1)*8) + 7;
+
+extern volatile __bit TMR1GIF @ (((unsigned) &PIR1)*8) + 7;
+
+extern volatile __bit TMR1IE @ (((unsigned) &PIE1)*8) + 0;
+
+extern volatile __bit TMR1IF @ (((unsigned) &PIR1)*8) + 0;
+
+extern volatile __bit TMR1ON @ (((unsigned) &T1CON)*8) + 0;
+
+extern volatile __bit TMR2IE @ (((unsigned) &PIE1)*8) + 1;
+
+extern volatile __bit TMR2IF @ (((unsigned) &PIR1)*8) + 1;
+
+extern volatile __bit TMR2ON @ (((unsigned) &T2CON)*8) + 2;
+
+extern volatile __bit TRISA0 @ (((unsigned) &TRISA)*8) + 0;
+
+extern volatile __bit TRISA1 @ (((unsigned) &TRISA)*8) + 1;
+
+extern volatile __bit TRISA2 @ (((unsigned) &TRISA)*8) + 2;
+
+extern volatile __bit TRISA3 @ (((unsigned) &TRISA)*8) + 3;
+
+extern volatile __bit TRISA4 @ (((unsigned) &TRISA)*8) + 4;
+
+extern volatile __bit TRISA5 @ (((unsigned) &TRISA)*8) + 5;
+
+extern volatile __bit TRMT @ (((unsigned) &TXSTA)*8) + 1;
+
+extern volatile __bit TSEN @ (((unsigned) &FVRCON)*8) + 5;
+
+extern volatile __bit TSRNG @ (((unsigned) &FVRCON)*8) + 4;
+
+extern volatile __bit TUN0 @ (((unsigned) &OSCTUNE)*8) + 0;
+
+extern volatile __bit TUN1 @ (((unsigned) &OSCTUNE)*8) + 1;
+
+extern volatile __bit TUN2 @ (((unsigned) &OSCTUNE)*8) + 2;
+
+extern volatile __bit TUN3 @ (((unsigned) &OSCTUNE)*8) + 3;
+
+extern volatile __bit TUN4 @ (((unsigned) &OSCTUNE)*8) + 4;
+
+extern volatile __bit TUN5 @ (((unsigned) &OSCTUNE)*8) + 5;
+
+extern volatile __bit TX9 @ (((unsigned) &TXSTA)*8) + 6;
+
+extern volatile __bit TX9D @ (((unsigned) &TXSTA)*8) + 0;
+
+extern volatile __bit TXCKSEL @ (((unsigned) &APFCON)*8) + 2;
+
+extern volatile __bit TXEN @ (((unsigned) &TXSTA)*8) + 5;
+
+extern volatile __bit TXIE @ (((unsigned) &PIE1)*8) + 4;
+
+extern volatile __bit TXIF @ (((unsigned) &PIR1)*8) + 4;
+
+extern volatile __bit UA @ (((unsigned) &SSP1STAT)*8) + 1;
+
+extern volatile __bit VREGPM0 @ (((unsigned) &VREGCON)*8) + 0;
+
+extern volatile __bit VREGPM1 @ (((unsigned) &VREGCON)*8) + 1;
+
+extern volatile __bit WCOL @ (((unsigned) &SSP1CON1)*8) + 7;
+
+extern volatile __bit WDTPS0 @ (((unsigned) &WDTCON)*8) + 1;
+
+extern volatile __bit WDTPS1 @ (((unsigned) &WDTCON)*8) + 2;
+
+extern volatile __bit WDTPS2 @ (((unsigned) &WDTCON)*8) + 3;
+
+extern volatile __bit WDTPS3 @ (((unsigned) &WDTCON)*8) + 4;
+
+extern volatile __bit WDTPS4 @ (((unsigned) &WDTCON)*8) + 5;
+
+extern volatile __bit WPUA0 @ (((unsigned) &WPUA)*8) + 0;
+
+extern volatile __bit WPUA1 @ (((unsigned) &WPUA)*8) + 1;
+
+extern volatile __bit WPUA2 @ (((unsigned) &WPUA)*8) + 2;
+
+extern volatile __bit WPUA3 @ (((unsigned) &WPUA)*8) + 3;
+
+extern volatile __bit WPUA4 @ (((unsigned) &WPUA)*8) + 4;
+
+extern volatile __bit WPUA5 @ (((unsigned) &WPUA)*8) + 5;
+
+extern volatile __bit WR @ (((unsigned) &EECON1)*8) + 1;
+
+extern volatile __bit WREN @ (((unsigned) &EECON1)*8) + 2;
+
+extern volatile __bit WRERR @ (((unsigned) &EECON1)*8) + 3;
+
+extern volatile __bit WUE @ (((unsigned) &BAUDCON)*8) + 1;
+
+extern volatile __bit ZERO @ (((unsigned) &STATUS)*8) + 2;
+
+extern volatile __bit Z_SHAD @ (((unsigned) &STATUS_SHAD)*8) + 2;
+
+extern volatile __bit nBOR @ (((unsigned) &PCON)*8) + 0;
+
+extern volatile __bit nPD @ (((unsigned) &STATUS)*8) + 3;
+
+extern volatile __bit nPOR @ (((unsigned) &PCON)*8) + 1;
+
+extern volatile __bit nRI @ (((unsigned) &PCON)*8) + 2;
+
+extern volatile __bit nRMCLR @ (((unsigned) &PCON)*8) + 3;
+
+extern volatile __bit nT1SYNC @ (((unsigned) &T1CON)*8) + 2;
+
+extern volatile __bit nTO @ (((unsigned) &STATUS)*8) + 4;
+
+extern volatile __bit nWPUEN @ (((unsigned) &OPTION_REG)*8) + 7;
+
+
+# 27 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_nop)
+extern void _nop(void);
+
+# 77
+extern unsigned int flash_read(unsigned short addr);
+
+# 41 "/opt/microchip/xc8/v1.12/include/eeprom_routines.h"
+extern void eeprom_write(unsigned char addr, unsigned char value);
+extern unsigned char eeprom_read(unsigned char addr);
+extern void eecpymem(volatile unsigned char *to, __eeprom unsigned char *from, unsigned char size);
+extern void memcpyee(__eeprom unsigned char *to, const unsigned char *from, unsigned char size);
+
+
+# 150 "/opt/microchip/xc8/v1.12/include/pic.h"
+#pragma intrinsic(_delay)
+extern void _delay(unsigned long);
+
+# 13 "/opt/microchip/xc8/v1.12/include/stdint.h"
+typedef signed char int8_t;
+
+# 20
+typedef signed int int16_t;
+
+# 28
+typedef signed short long int int24_t;
+
+# 36
+typedef signed long int int32_t;
+
+# 43
+typedef unsigned char uint8_t;
+
+# 49
+typedef unsigned int uint16_t;
+
+# 56
+typedef unsigned short long int uint24_t;
+
+# 63
+typedef unsigned long int uint32_t;
+
+# 71
+typedef signed char int_least8_t;
+
+# 78
+typedef signed int int_least16_t;
+
+# 90
+typedef signed short long int int_least24_t;
+
+# 98
+typedef signed long int int_least32_t;
+
+# 105
+typedef unsigned char uint_least8_t;
+
+# 111
+typedef unsigned int uint_least16_t;
+
+# 121
+typedef unsigned short long int uint_least24_t;
+
+# 128
+typedef unsigned long int uint_least32_t;
+
+# 137
+typedef signed char int_fast8_t;
+
+# 144
+typedef signed int int_fast16_t;
+
+# 156
+typedef signed short long int int_fast24_t;
+
+# 164
+typedef signed long int int_fast32_t;
+
+# 171
+typedef unsigned char uint_fast8_t;
+
+# 177
+typedef unsigned int uint_fast16_t;
+
+# 187
+typedef unsigned short long int uint_fast24_t;
+
+# 194
+typedef unsigned long int uint_fast32_t;
+
+# 200
+typedef int32_t intmax_t;
+
+
+
+
+typedef uint32_t uintmax_t;
+
+
+
+
+typedef int16_t intptr_t;
+
+
+
+
+typedef uint16_t uintptr_t;
+
+# 12 "/opt/microchip/xc8/v1.12/include/stdbool.h"
+typedef unsigned char bool;
+
+# 13 "user.h"
+void InitApp(void);
+
+# 22 "user.c"
+void InitApp(void)
+{
+
+
+
+OSCCONbits.SPLLEN = 0;
+OSCCONbits.IRCF = 0b1101;
+OSCCONbits.SCS = 0b11;
+
+
+TXSTAbits.TXEN = 1;
+TXSTAbits.SYNC = 0;
+RCSTAbits.SPEN = 1;
+
+RCSTAbits.CREN = 1;
+
+
+TXSTAbits.BRGH = 1;
+BAUDCONbits.BRG16 = 1;
+SPBRG = 8;
+
+
+APFCONbits.RXDTSEL = 1;
+APFCONbits.TXCKSEL = 1;
+TRISAbits.TRISA5 = 1;
+TRISAbits.TRISA4 = 0;
+
+ANSELA = 0;
+
+
+
+WPUA = 0;
+OPTION_REGbits.nWPUEN = 0;
+
+# 62
+}
+

diff --git a/configuration_bits.c b/configuration_bits.c
new file mode 100644 (file)
index 0000000..fdfc510
--- /dev/null
+++ b/configuration_bits.c
@@ -0,0 +1,55 @@
+/******************************************************************************/
+/* Main Files to Include                                                      */
+/******************************************************************************/
+
+#if defined(__XC)
+    #include <xc.h>         /* XC8 General Include File */
+#elif defined(HI_TECH_C)
+    #include <htc.h>        /* HiTech General Include File */
+#endif
+
+/******************************************************************************/
+/* Configuration Bits                                                         */
+/*                                                                            */
+/* Refer to your Hi-Tech User Manual in the PICC installation directory       */
+/* /doc folder for more information on filling in configuration bits.         */
+/* In addition, configuration bit mnemonics can be found in your              */
+/* PICC\version\include\<processor name>.h file for your device.  The XC8     */
+/* compiler contains documentation on the configuration bit macros within     */
+/* the compiler installation /docs folder in a file called                    */
+/* pic18_chipinfo.html.                                                       */
+/*                                                                            */
+/* For additional information about what the hardware configurations mean in  */
+/* terms of device operation, refer to the device datasheet.                  */
+/*                                                                            */
+/* A feature of MPLAB X is the 'Generate Source Code to Output' utility in    */
+/* the Configuration Bits window.  Under Window > PIC Memory Views >          */
+/* Configuration Bits, a user controllable configuration bits window is       */
+/* available to Generate Configuration Bits source code which the user can    */
+/* paste into this project.                                                   */
+/*                                                                            */
+/******************************************************************************/
+
+
+// PIC12F1840 Configuration Bit Settings
+
+// CONFIG1
+#pragma config FOSC = INTOSC    // Oscillator Selection (INTOSC oscillator: I/O function on CLKIN pin)
+#pragma config WDTE = SWDTEN    // Watchdog Timer Enable (WDT software enabled)
+#pragma config PWRTE = OFF      // Power-up Timer Enable (PWRT disabled)
+#pragma config MCLRE = OFF      // MCLR Pin Function Select (MCLR/VPP pin function is digital input)
+#pragma config CP = OFF         // Flash Program Memory Code Protection (Program memory code protection is disabled)
+#pragma config CPD = OFF        // Data Memory Code Protection (Data memory code protection is disabled)
+#pragma config BOREN = ON       // Brown-out Reset Enable (Brown-out Reset enabled)
+#pragma config CLKOUTEN = OFF   // Clock Out Enable (CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin)
+#pragma config IESO = OFF       // Internal/External Switchover (Internal/External Switchover mode is disabled)
+#pragma config FCMEN = ON       // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor is enabled)
+
+// CONFIG2
+#pragma config WRT = OFF        // Flash Memory Self-Write Protection (Write protection off)
+#pragma config PLLEN = ON       // PLL Enable (4x PLL enabled)
+#pragma config STVREN = ON      // Stack Overflow/Underflow Reset Enable (Stack Overflow or Underflow will cause a Reset)
+#pragma config BORV = LO        // Brown-out Reset Voltage Selection (Brown-out Reset Voltage (Vbor), low trip point selected.)
+#pragma config LVP = ON         // Low-Voltage Programming Enable (Low-voltage programming enabled)
+
+

diff --git a/disassembly/listing.disasm b/disassembly/listing.disasm
new file mode 100644 (file)
index 0000000..df440f6
--- /dev/null
+++ b/disassembly/listing.disasm
@@ -0,0 +1,3427 @@
+Disassembly Listing for uart test
+Generated From:
+/home/justin/MPLABXProjects/uart test.X/dist/XC8_12F1840/production/uart_test.X.production.cof
+10-Jun-2013 16:52:45
+
+---  /home/justin/MPLABXProjects/uart test.X/user.c  ----------------------------------------------------
+1:             /******************************************************************************/
+2:             /* Files to Include                                                           */
+3:             /******************************************************************************/
+4:             
+5:             #if defined(__XC)
+6:                 #include <xc.h>         /* XC8 General Include File */
+7:             #elif defined(HI_TECH_C)
+8:                 #include <htc.h>        /* HiTech General Include File */
+9:             #endif
+10:            
+11:            #include <stdint.h>         /* For uint8_t definition */
+12:            #include <stdbool.h>        /* For true/false definition */
+13:            
+14:            #include "system.h"
+15:            #include "user.h"
+16:            
+17:            /******************************************************************************/
+18:            /* User Functions                                                             */
+19:            /******************************************************************************/
+20:            
+21:            /* <Initialize variables in user.h and insert code for user algorithms.> */
+22:            
+23:            void InitApp(void)
+24:            {
+25:                /* TODO Initialize User Ports/Peripherals/Project here */
+26:                
+27:                /* configure 4MHz mode */
+28:                OSCCONbits.SPLLEN = 0;
+0BCE  0021     MOVLB 0x1
+0BCF  1399     BCF T1GCON, 0x7
+29:                OSCCONbits.IRCF = 0b1101;
+0BD0  0819     MOVF T1GCON, W
+0BD1  3987     ANDLW 0x87
+0BD2  3868     IORLW 0x68
+0BD3  0099     MOVWF T1GCON
+30:                OSCCONbits.SCS = 0b00;
+0BD4  30FC     MOVLW 0xFC
+0BD5  0599     ANDWF T1GCON, F
+31:                
+32:                /* Enabling transmitter 26.1.1.1 page 259 - TX/CK I/O pin */
+33:                TXSTAbits.TXEN = 1;
+0BD6  0023     MOVLB 0x3
+0BD7  169E     BSF CPSCON0, 0x5
+34:                TXSTAbits.SYNC = 0;
+0BD8  121E     BCF CPSCON0, 0x4
+35:                RCSTAbits.SPEN = 1;
+0BD9  179D     BSF 0x1D, 0x7
+36:                /* Enabling receiver 26.1.2 page 262 - RX/DT I/O pin */
+37:                RCSTAbits.CREN = 1;
+0BDA  161D     BSF 0x1D, 0x4
+38:            
+39:                /* 4MHz clock, 19k2 baud */
+40:                TXSTAbits.BRGH = 0;
+0BDB  111E     BCF CPSCON0, 0x2
+41:                BAUDCONbits.BRG16 = 1;
+0BDC  159F     BSF CPSCON1, 0x3
+42:                SPBRG = 12;
+0BDD  300C     MOVLW 0xC
+0BDE  009B     MOVWF PR2
+43:            
+44:                /* Select pins 4&5 as the uart - page 102 */
+45:                APFCONbits.RXDTSEL = 1; /* RX/DT on RA5 */
+0BDF  0022     MOVLB 0x2
+0BE0  179D     BSF 0x1D, 0x7
+46:                APFCONbits.TXCKSEL = 1; /* TX/CK on RA4 */
+0BE1  151D     BSF 0x1D, 0x2
+47:                TRISAbits.TRISA5 = 1;   /* RA5 as input  */
+0BE2  0021     MOVLB 0x1
+0BE3  168C     BSF PORTA, 0x5
+48:                TRISAbits.TRISA4 = 0;   /* RA4 as output */
+0BE4  120C     BCF PORTA, 0x4
+49:            
+50:                ANSELA = 0; /* no analog */
+0BE5  0023     MOVLB 0x3
+0BE6  018C     CLRF PORTA
+51:            
+52:            
+53:                /* enable weak pullups, clear them all */
+54:                WPUA = 0;
+0BE7  0024     MOVLB 0x4
+0BE8  018C     CLRF PORTA
+55:                //WPUAbits.WPUA0 = 0x00000100; // RA0 pullup for 1-wire bus
+56:                OPTION_REGbits.nWPUEN = 1;
+0BE9  0021     MOVLB 0x1
+0BEA  1795     BSF TMR0, 0x7
+57:            
+58:                /* Enable interrupts */
+59:                INTCONbits.GIE = 1;
+0BEB  178B     BSF INTCON, 0x7
+60:                INTCONbits.PEIE = 1;
+0BEC  170B     BSF INTCON, 0x6
+61:            
+62:                /* enable uart receiver interupt */
+63:                PIE1bits.RCIE = 1;
+0BED  1691     BSF PIR1, 0x5
+64:            }
+0BEE  0008     RETURN
+65:            
+---  /home/justin/MPLABXProjects/uart test.X/system.c  --------------------------------------------------
+1:             /******************************************************************************/
+2:             /* Files to Include                                                           */
+3:             /******************************************************************************/
+4:             
+5:             #if defined(__XC)
+6:                 #include <xc.h>         /* XC8 General Include File */
+7:             #elif defined(HI_TECH_C)
+8:                 #include <htc.h>        /* HiTech General Include File */
+9:             #endif
+10:            
+11:            #include <stdint.h>        /* For uint8_t definition */
+12:            #include <stdbool.h>       /* For true/false definition */
+13:            
+14:            #include "system.h"
+15:            
+16:            /* Refer to the device datasheet for information about available
+17:            oscillator configurations and to compiler documentation for macro details. */
+18:            void ConfigureOscillator(void)
+19:            {
+20:            
+21:                /*If the PIC12 device has an OSCCAL value, the HiTech Compiler provides
+22:                a macro called _READ_OSCCAL_DATA which can be loaded using this: */
+23:            
+24:                /* TODO Configure OSCCAL if the device has an OSCCAL register */
+25:            
+26:            #if 0
+27:            
+28:                OSCCAL=_READ_OSCCAL_DATA(); /* _READ_OSCCAL_DATA macro unloads cal memory */
+29:            
+30:            #endif
+31:            
+32:                /*Not all PIC12 devices require this.
+33:            
+34:                /* TODO Add clock switching code if appropriate.  */
+35:            
+36:                /* Typical actions in this function are to tweak the oscillator tuning
+37:                register, select new clock sources, and to wait until new clock sources
+38:                are stable before resuming execution of the main project. */
+39:            
+40:            }
+0B1F  0008     RETURN
+---  /home/justin/MPLABXProjects/uart test.X/onewire.c  -------------------------------------------------
+1:             /* Dallas 1-Wire bus routines */
+2:             
+3:             #if defined(__XC)
+4:                 #include <xc.h>         /* XC8 General Include File */
+5:             #elif defined(HI_TECH_C)
+6:                 #include <htc.h>        /* HiTech General Include File */
+7:             #endif
+8:             
+9:             #include <stdint.h>         /* For uint8_t definition */
+10:            #include <stdbool.h>        /* For true/false definition */
+11:            
+12:            #include "system.h"
+13:            #include "user.h"
+14:            #include "onewire.h"
+15:            
+16:            // fast way, macros
+17:            #define OWLOW { PORTAbits.RA2 = 0; TRISAbits.TRISA2 = 0; }
+18:            #define OWHIGH { PORTAbits.RA2 = 1; TRISAbits.TRISA2 = 0; }
+19:            #define OWTRI { TRISAbits.TRISA2 = 1; }
+20:            #define OWREAD (PORTAbits.RA2)
+21:            
+22:            
+23:            // slow way, causes a function call
+24:            inline void drive_OW_low(void)
+25:            {
+26:                PORTAbits.RA2 = 0;
+0B2D  0020     MOVLB 0x0
+0B2E  110C     BCF PORTA, 0x2
+27:                TRISAbits.TRISA2 = 0;
+0B2F  0021     MOVLB 0x1
+0B30  110C     BCF PORTA, 0x2
+28:            }
+0B31  0008     RETURN
+29:            
+30:            inline void drive_OW_high(void)
+31:            {
+32:                PORTAbits.RA2 = 1;
+0B28  0020     MOVLB 0x0
+0B29  150C     BSF PORTA, 0x2
+33:                TRISAbits.TRISA2 = 0;
+0B2A  0021     MOVLB 0x1
+0B2B  110C     BCF PORTA, 0x2
+34:            }
+0B2C  0008     RETURN
+35:            
+36:            inline void float_OW(void)
+37:            {
+38:                TRISAbits.TRISA2 = 1;
+04FD  0021     MOVLB 0x1
+04FE  150C     BSF PORTA, 0x2
+39:            }
+04FF  0008     RETURN
+40:            
+41:            inline bool read_OW(void)
+42:            {
+43:                TRISAbits.TRISA2 = 1;
+0B32  0021     MOVLB 0x1
+0B33  150C     BSF PORTA, 0x2
+44:                return PORTAbits.RA2;
+0B34  0020     MOVLB 0x0
+0B35  0C0C     RRF PORTA, W
+0B36  0C89     RRF WREG, F
+0B37  3901     ANDLW 0x1
+0B38  2B39     GOTO 0x339
+45:            }
+0B39  0008     RETURN
+46:            
+47:            
+48:            /* start the 1-Wire bus
+49:             *
+50:             */
+51:            void OW_start(void)
+52:            {
+53:                //drive_OW_high();
+54:                float_OW();
+0B24  3184     MOVLP 0x4
+0B25  24FD     CALL 0x4FD
+0B26  318B     MOVLP 0xB
+55:            }
+0B27  0008     RETURN
+56:            
+57:            /* reset the bus, test for presence signal */
+58:            bool OW_reset(void)
+59:            {
+60:                bool presence = 0;
+0C37  01F5     CLRF presence
+61:            
+62:                OWLOW; //drive_OW_low();
+0C38  0020     MOVLB 0x0
+0C39  110C     BCF PORTA, 0x2
+0C3A  0021     MOVLB 0x1
+0C3B  110C     BCF PORTA, 0x2
+63:                DelayUs(250);
+0C3C  3053     MOVLW 0x53
+0C3D  00F4     MOVWF i
+0C3E  0BF4     DECFSZ i, F
+0C3F  2C3E     GOTO 0x43E
+64:                DelayUs(250);
+0C40  3053     MOVLW 0x53
+0C41  00F4     MOVWF i
+0C42  0BF4     DECFSZ i, F
+0C43  2C42     GOTO 0x442
+65:                OWTRI; //float_OW(); // let it float high
+0C44  0021     MOVLB 0x1
+0C45  150C     BSF PORTA, 0x2
+66:                DelayUs(70);
+0C46  3017     MOVLW 0x17
+0C47  00F4     MOVWF i
+0C48  0BF4     DECFSZ i, F
+0C49  2C48     GOTO 0x448
+67:                presence = OWREAD; //read_OW(); // now sample
+0C4A  3000     MOVLW 0x0
+0C4B  0020     MOVLB 0x0
+0C4C  190C     BTFSC PORTA, 0x2
+0C4D  3001     MOVLW 0x1
+0C4E  00F5     MOVWF presence
+68:                DelayUs(215);
+0C4F  3047     MOVLW 0x47
+0C50  00F4     MOVWF i
+0C51  0BF4     DECFSZ i, F
+0C52  2C51     GOTO 0x451
+0C53  0000     NOP
+69:                DelayUs(215);
+0C54  3047     MOVLW 0x47
+0C55  00F4     MOVWF i
+0C56  0BF4     DECFSZ i, F
+0C57  2C56     GOTO 0x456
+0C58  0000     NOP
+70:                
+71:                return ! presence;
+0C59  0875     MOVF presence, W
+0C5A  3A00     XORLW 0x0
+0C5B  3000     MOVLW 0x0
+0C5C  1903     BTFSC STATUS, 0x2
+0C5D  3001     MOVLW 0x1
+0C5E  2C5F     GOTO 0x45F
+72:            }
+0C5F  0008     RETURN
+73:            
+74:            void OW_write_bit(bool val)
+75:            {
+76:            #if 0  // Maxim dev note 2420
+77:                drive_OW_low();
+78:                DelayUs(3);
+79:                if (val) float_OW();
+80:                DelayUs(60);
+81:                float_OW();
+82:                DelayUs(2);
+83:            #else
+84:                OWLOW;
+0B5C  00F5     MOVWF presence
+0B5D  0020     MOVLB 0x0
+0B5E  110C     BCF PORTA, 0x2
+0B5F  0021     MOVLB 0x1
+0B60  110C     BCF PORTA, 0x2
+85:                NOP();
+0B61  0000     NOP
+86:                NOP();
+0B62  0000     NOP
+87:            //    NOP();  // doc one for other delays
+88:                if (val) OWTRI;
+0B63  0875     MOVF presence, W
+0B64  1D03     BTFSS STATUS, 0x2
+0B65  2B67     GOTO 0x367
+0B66  2B6A     GOTO 0x36A
+0B67  0021     MOVLB 0x1
+0B68  150C     BSF PORTA, 0x2
+0B69  2B6A     GOTO 0x36A
+89:                DelayUs(60);
+0B6A  3013     MOVLW 0x13
+0B6B  00F4     MOVWF i
+0B6C  0BF4     DECFSZ i, F
+0B6D  2B6C     GOTO 0x36C
+0B6E  2B6F     GOTO 0x36F
+90:                OWTRI;
+0B6F  0021     MOVLB 0x1
+0B70  150C     BSF PORTA, 0x2
+91:                NOP();
+0B71  0000     NOP
+92:                NOP();
+0B72  0000     NOP
+93:            #endif
+94:            }
+0B73  0008     RETURN
+95:            
+96:            bool OW_read_bit()
+97:            {
+98:                bool val;
+99:            #if 0  /* Maxim dev note 2420 */
+100:               drive_OW_low();
+101:               DelayUs(6);
+102:               float_OW();
+103:               DelayUs(4);
+104:               val = read_OW();
+105:               DelayUs(50);
+106:           #else
+107:               OWLOW;
+0B74  0020     MOVLB 0x0
+0B75  110C     BCF PORTA, 0x2
+0B76  0021     MOVLB 0x1
+0B77  110C     BCF PORTA, 0x2
+108:           //    NOP();
+109:               NOP();
+0B78  0000     NOP
+110:               NOP();
+0B79  0000     NOP
+111:               NOP();
+0B7A  0000     NOP
+112:               NOP();
+0B7B  0000     NOP
+113:               NOP();
+0B7C  0000     NOP
+114:               OWTRI;
+0B7D  0021     MOVLB 0x1
+0B7E  150C     BSF PORTA, 0x2
+115:           //    NOP();
+116:               NOP();
+0B7F  0000     NOP
+117:               NOP();
+0B80  0000     NOP
+118:               NOP();
+0B81  0000     NOP
+119:               val = read_OW();
+0B82  318B     MOVLP 0xB
+0B83  2332     CALL 0x332
+0B84  318B     MOVLP 0xB
+0B85  00F4     MOVWF i
+0B86  0874     MOVF i, W
+0B87  00F5     MOVWF presence
+120:               DelayUs(50);
+0B88  3010     MOVLW 0x10
+0B89  00F4     MOVWF i
+0B8A  0BF4     DECFSZ i, F
+0B8B  2B8A     GOTO 0x38A
+0B8C  0000     NOP
+121:               
+122:           #endif
+123:               return val;
+0B8D  0875     MOVF presence, W
+0B8E  2B8F     GOTO 0x38F
+124:           }
+0B8F  0008     RETURN
+125:           
+126:           void OW_write_byte(unsigned char byte)
+127:           {
+0B90  0020     MOVLB 0x0
+0B91  00B6     MOVWF p
+128:               for (char i=8; i!=0; i--)
+0B92  3008     MOVLW 0x8
+0B93  00B5     MOVWF in
+0B94  0835     MOVF in, W
+0B95  00B7     MOVWF i
+0B96  08B7     MOVF i, F
+0B97  1D03     BTFSS STATUS, 0x2
+0B98  2B9A     GOTO 0x39A
+0B99  2B9B     GOTO 0x39B
+0B9A  2B9D     GOTO 0x39D
+0B9B  2BAD     GOTO 0x3AD
+0B9C  2BAD     GOTO 0x3AD
+0BA5  3001     MOVLW 0x1
+0BA6  02B7     SUBWF i, F
+0BA7  08B7     MOVF i, F
+0BA8  1D03     BTFSS STATUS, 0x2
+0BA9  2BAB     GOTO 0x3AB
+0BAA  2BAC     GOTO 0x3AC
+0BAB  2B9D     GOTO 0x39D
+0BAC  2BAD     GOTO 0x3AD
+129:               {
+130:                   OW_write_bit( byte & 0x01 );
+0B9D  0836     MOVF p, W
+0B9E  3901     ANDLW 0x1
+0B9F  318B     MOVLP 0xB
+0BA0  235C     CALL 0x35C
+0BA1  318B     MOVLP 0xB
+131:                   byte >>= 1;
+0BA2  1003     BCF STATUS, 0x0
+0BA3  0020     MOVLB 0x0
+0BA4  0CB6     RRF p, F
+132:               }
+133:           }
+0BAD  0008     RETURN
+134:           
+135:           unsigned char OW_read_byte(void)
+136:           {
+137:               unsigned char byte = 0;
+0C11  0020     MOVLB 0x0
+0C12  01B6     CLRF p
+138:               for (char i=8; i!=0; i--)
+0C13  3008     MOVLW 0x8
+0C14  00B5     MOVWF in
+0C15  0835     MOVF in, W
+0C16  00B7     MOVWF i
+0C17  08B7     MOVF i, F
+0C18  1D03     BTFSS STATUS, 0x2
+0C19  2C1B     GOTO 0x41B
+0C1A  2C1C     GOTO 0x41C
+0C1B  2C1E     GOTO 0x41E
+0C1C  2C34     GOTO 0x434
+0C1D  2C34     GOTO 0x434
+0C2B  3001     MOVLW 0x1
+0C2C  0020     MOVLB 0x0
+0C2D  02B7     SUBWF i, F
+0C2E  08B7     MOVF i, F
+0C2F  1D03     BTFSS STATUS, 0x2
+0C30  2C32     GOTO 0x432
+0C31  2C33     GOTO 0x433
+0C32  2C1E     GOTO 0x41E
+0C33  2C34     GOTO 0x434
+139:               {
+140:                   byte >>= 1;
+0C1E  1003     BCF STATUS, 0x0
+0C1F  0CB6     RRF p, F
+141:                   if (OW_read_bit())
+0C20  318B     MOVLP 0xB
+0C21  2374     CALL 0x374
+0C22  318C     MOVLP 0xC
+0C23  3A00     XORLW 0x0
+0C24  1903     BTFSC STATUS, 0x2
+0C25  2C27     GOTO 0x427
+0C26  2C28     GOTO 0x428
+0C27  2C2B     GOTO 0x42B
+142:                       byte |= 0x80;
+0C28  0020     MOVLB 0x0
+0C29  17B6     BSF p, 0x7
+0C2A  2C2B     GOTO 0x42B
+143:           
+144:               }
+145:               return byte;
+0C34  0836     MOVF p, W
+0C35  2C36     GOTO 0x436
+146:           }
+0C36  0008     RETURN
+147:           
+148:           static const unsigned char dscrc_table[] = {
+149:                0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,
+150:                 157,195, 33,127,252,162, 64, 30, 95,  1,227,189, 62, 96,130,220,
+151:                  35,125,159,193, 66, 28,254,160,225,191, 93,  3,128,222, 60, 98,
+152:                 190,224,  2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,
+153:                  70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89,  7,
+154:                 219,133,103, 57,186,228,  6, 88, 25, 71,165,251,120, 38,196,154,
+155:                 101, 59,217,135,  4, 90,184,230,167,249, 27, 69,198,152,122, 36,
+156:                 248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91,  5,231,185,
+157:                 140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,
+158:                  17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,
+159:                 175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,
+160:                  50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,
+161:                 202,148,118, 40,171,245, 23, 73,  8, 86,180,234,105, 55,213,139,
+162:                  87,  9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,
+163:                 233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,
+164:                 116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53
+165:           };
+166:           
+167:           unsigned char romid[8];
+168:           char LastDiscrepancy = 0;
+169:           char LastFamilyDiscrepancy = 0;
+170:           char LastDeviceFlag = false;
+171:           unsigned char crc8;
+172:           
+173:           static unsigned char docrc8(unsigned char value)
+174:           {
+04ED  00F5     MOVWF presence
+175:               crc8 = dscrc_table[crc8 ^ value];
+04EE  0020     MOVLB 0x0
+04EF  082B     MOVF crc8, W
+04F0  0675     XORWF presence, W
+04F1  3E01     ADDLW 0x1
+04F2  0084     MOVWF FSR0L
+04F3  3085     MOVLW 0x85
+04F4  1803     BTFSC STATUS, 0x0
+04F5  3E01     ADDLW 0x1
+04F6  0085     MOVWF FSR0H
+04F7  0800     MOVF INDF0, W
+04F8  00F4     MOVWF i
+04F9  0874     MOVF i, W
+04FA  00AB     MOVWF crc8
+04FB  2CFC     GOTO 0x4FC
+176:               return crc8;
+177:           }
+04FC  0008     RETURN
+178:           
+179:           /* enumerate the devices */
+180:           bool OW_search()
+181:           {
+182:               char id_bit_number = 1;
+0F0C  0020     MOVLB 0x0
+0F0D  01BE     CLRF id_bit_number
+0F0E  0ABE     INCF id_bit_number, F
+183:               char last_zero = 0;
+0F0F  01BC     CLRF last_zero
+184:               char rom_byte_number = 0;
+0F10  01C0     CLRF rom_byte_number
+185:               char search_result = 0;
+0F11  01BA     CLRF search_result
+186:               unsigned char rom_byte_mask = 1;
+0F12  01BF     CLRF rom_byte_mask
+0F13  0ABF     INCF rom_byte_mask, F
+187:               unsigned char search_direction;
+188:           
+189:               crc8 = 0;
+0F14  01AB     CLRF crc8
+190:           
+191:               // do not interrupt us
+192:               int_disable();
+0F15  318B     MOVLP 0xB
+0F16  2322     CALL 0x322
+0F17  318F     MOVLP 0xF
+193:           
+194:               // if the last call was not the last one
+195:               if (!LastDeviceFlag) {
+0F18  0020     MOVLB 0x0
+0F19  08A8     MOVF LastDeviceFlag, F
+0F1A  1D03     BTFSS STATUS, 0x2
+0F1B  2F1D     GOTO 0x71D
+0F1C  2F1E     GOTO 0x71E
+0F1D  2FD2     GOTO 0x7D2
+196:                   if (!OW_reset())
+0F1E  318C     MOVLP 0xC
+0F1F  2437     CALL 0x437
+0F20  318F     MOVLP 0xF
+0F21  3800     IORLW 0x0
+0F22  1D03     BTFSS STATUS, 0x2
+0F23  2F25     GOTO 0x725
+0F24  2F26     GOTO 0x726
+0F25  2F37     GOTO 0x737
+197:                   {
+198:                       msg_write("Reset said nothing there.\r\n");
+0F26  3048     MOVLW 0x48
+0F27  00F4     MOVWF i
+0F28  3087     MOVLW 0x87
+0F29  00F5     MOVWF presence
+0F2A  318E     MOVLP 0xE
+0F2B  2613     CALL 0x613
+0F2C  318F     MOVLP 0xF
+199:                       // reset the search
+200:                       LastDiscrepancy = 0;
+0F2D  0020     MOVLB 0x0
+0F2E  01A9     CLRF LastDiscrepancy
+201:                       LastDeviceFlag = 0;
+0F2F  01A8     CLRF LastDeviceFlag
+202:                       LastFamilyDiscrepancy = 0;
+0F30  01AA     CLRF LastFamilyDiscrepancy
+203:                       int_enable();
+0F31  318B     MOVLP 0xB
+0F32  2320     CALL 0x320
+0F33  318F     MOVLP 0xF
+204:                       return 0;
+0F34  3000     MOVLW 0x0
+0F35  2FFF     GOTO 0x7FF
+0F36  2FFF     GOTO 0x7FF
+205:                   }
+206:           
+207:                   // issue the search command
+208:                   OW_write_byte(0xF0);
+0F37  30F0     MOVLW 0xF0
+0F38  318B     MOVLP 0xB
+0F39  2390     CALL 0x390
+0F3A  318F     MOVLP 0xF
+209:           
+210:                   // loop to do the search
+211:                   do {
+212:                       // read a bit and its complement
+213:                       bool id_bit = OW_read_bit();
+0F3B  318B     MOVLP 0xB
+0F3C  2374     CALL 0x374
+0F3D  318F     MOVLP 0xF
+0F3E  0020     MOVLB 0x0
+0F3F  00B8     MOVWF bt
+0F40  0838     MOVF bt, W
+0F41  00BB     MOVWF id_bit
+214:                       DelayUs(6);
+0F42  2F43     GOTO 0x743
+0F43  2F44     GOTO 0x744
+0F44  2F45     GOTO 0x745
+215:                       bool cmp_id_bit = OW_read_bit();
+0F45  318B     MOVLP 0xB
+0F46  2374     CALL 0x374
+0F47  318F     MOVLP 0xF
+0F48  0020     MOVLB 0x0
+0F49  00B8     MOVWF bt
+0F4A  0838     MOVF bt, W
+0F4B  00B9     MOVWF cmp_id_bit
+216:           
+217:                       // check for no devices on bus
+218:                       if (id_bit && cmp_id_bit) {
+0F4C  083B     MOVF id_bit, W
+0F4D  1D03     BTFSS STATUS, 0x2
+0F4E  2F50     GOTO 0x750
+0F4F  2F56     GOTO 0x756
+0F50  0839     MOVF cmp_id_bit, W
+0F51  1D03     BTFSS STATUS, 0x2
+0F52  2F54     GOTO 0x754
+0F53  2F56     GOTO 0x756
+0F54  2FD2     GOTO 0x7D2
+219:                           break;
+0F55  2FD2     GOTO 0x7D2
+220:                       }
+221:           
+222:                       if (id_bit != cmp_id_bit) {
+0F56  083B     MOVF id_bit, W
+0F57  0639     XORWF cmp_id_bit, W
+0F58  1903     BTFSC STATUS, 0x2
+0F59  2F5B     GOTO 0x75B
+0F5A  2F5C     GOTO 0x75C
+0F5B  2F61     GOTO 0x761
+223:                           // all devices have a 0 here, or they all have a 1
+224:                           search_direction = id_bit;
+0F5C  083B     MOVF id_bit, W
+0F5D  00B8     MOVWF bt
+0F5E  0838     MOVF bt, W
+0F5F  00BD     MOVWF search_direction
+225:                       } else {
+0F60  2F92     GOTO 0x792
+226:                           // both bits zero, so both 0 and 1 exist
+227:           
+228:                           // if this discrepancy is before the Last Discrepancy
+229:                           // on a previous next then pick the same as last time
+230:                           if (id_bit_number < LastDiscrepancy) {
+0F61  0829     MOVF LastDiscrepancy, W
+0F62  023E     SUBWF id_bit_number, W
+0F63  1803     BTFSC STATUS, 0x0
+0F64  2F66     GOTO 0x766
+0F65  2F67     GOTO 0x767
+0F66  2F74     GOTO 0x774
+231:                               search_direction = ((romid[rom_byte_number] & rom_byte_mask) > 0);
+0F67  0840     MOVF rom_byte_number, W
+0F68  3E20     ADDLW 0x20
+0F69  0086     MOVWF FSR1L
+0F6A  0187     CLRF FSR1H
+0F6B  0801     MOVF INDF1, W
+0F6C  053F     ANDWF rom_byte_mask, W
+0F6D  3000     MOVLW 0x0
+0F6E  1D03     BTFSS STATUS, 0x2
+0F6F  3001     MOVLW 0x1
+0F70  00B8     MOVWF bt
+0F71  0838     MOVF bt, W
+0F72  00BD     MOVWF search_direction
+232:                           } else {
+0F73  2F7D     GOTO 0x77D
+233:                               // if equal to last pick 1, if not then pick 0
+234:                               search_direction = (id_bit_number == LastDiscrepancy);
+0F74  083E     MOVF id_bit_number, W
+0F75  0629     XORWF LastDiscrepancy, W
+0F76  3000     MOVLW 0x0
+0F77  1903     BTFSC STATUS, 0x2
+0F78  3001     MOVLW 0x1
+0F79  00B8     MOVWF bt
+0F7A  0838     MOVF bt, W
+0F7B  00BD     MOVWF search_direction
+0F7C  2F7D     GOTO 0x77D
+235:                           }
+236:           
+237:                           // if 0 was picked then record its position in LastZero
+238:                           if (search_direction == 0)
+0F7D  08BD     MOVF search_direction, F
+0F7E  1D03     BTFSS STATUS, 0x2
+0F7F  2F81     GOTO 0x781
+0F80  2F82     GOTO 0x782
+0F81  2F92     GOTO 0x792
+239:                           {
+240:                               last_zero = id_bit_number;
+0F82  083E     MOVF id_bit_number, W
+0F83  00B8     MOVWF bt
+0F84  0838     MOVF bt, W
+0F85  00BC     MOVWF last_zero
+241:                               // check for last discrepancy in family
+242:                               if (last_zero < 9)
+0F86  3009     MOVLW 0x9
+0F87  023C     SUBWF last_zero, W
+0F88  1803     BTFSC STATUS, 0x0
+0F89  2F8B     GOTO 0x78B
+0F8A  2F8C     GOTO 0x78C
+0F8B  2F92     GOTO 0x792
+243:                                   LastFamilyDiscrepancy = last_zero;
+0F8C  083C     MOVF last_zero, W
+0F8D  00B8     MOVWF bt
+0F8E  0838     MOVF bt, W
+0F8F  00AA     MOVWF LastFamilyDiscrepancy
+0F90  2F92     GOTO 0x792
+0F91  2F92     GOTO 0x792
+244:                           }
+245:                       }
+246:           
+247:                       // set or clear the bit in the ROM byte rom_byte_number
+248:                       // with mask rom_byte_mask
+249:                       if (search_direction == 1)
+0F92  083D     MOVF search_direction, W
+0F93  3A01     XORLW 0x1
+0F94  1D03     BTFSS STATUS, 0x2
+0F95  2F97     GOTO 0x797
+0F96  2F98     GOTO 0x798
+0F97  2FA1     GOTO 0x7A1
+250:                           romid[rom_byte_number] |= rom_byte_mask;
+0F98  083F     MOVF rom_byte_mask, W
+0F99  00B8     MOVWF bt
+0F9A  0840     MOVF rom_byte_number, W
+0F9B  3E20     ADDLW 0x20
+0F9C  0086     MOVWF FSR1L
+0F9D  0187     CLRF FSR1H
+0F9E  0838     MOVF bt, W
+0F9F  0481     IORWF INDF1, F
+0FA0  2FAA     GOTO 0x7AA
+251:                       else
+252:                           romid[rom_byte_number] &= ~rom_byte_mask;
+0FA1  093F     COMF rom_byte_mask, W
+0FA2  00B8     MOVWF bt
+0FA3  0840     MOVF rom_byte_number, W
+0FA4  3E20     ADDLW 0x20
+0FA5  0086     MOVWF FSR1L
+0FA6  0187     CLRF FSR1H
+0FA7  0838     MOVF bt, W
+0FA8  0581     ANDWF INDF1, F
+0FA9  2FAA     GOTO 0x7AA
+253:           
+254:                       // serial number search direction write bit
+255:                       OW_write_bit(search_direction);
+0FAA  083D     MOVF search_direction, W
+0FAB  318B     MOVLP 0xB
+0FAC  235C     CALL 0x35C
+0FAD  318F     MOVLP 0xF
+256:           
+257:                       // increment the byte counter id_bit_number
+258:                       // and shift the mask rom_byte_mask
+259:                       id_bit_number++;
+0FAE  3001     MOVLW 0x1
+0FAF  0020     MOVLB 0x0
+0FB0  00B8     MOVWF bt
+0FB1  0838     MOVF bt, W
+0FB2  07BE     ADDWF id_bit_number, F
+260:                       rom_byte_mask <<= 1;
+0FB3  1003     BCF STATUS, 0x0
+0FB4  0DBF     RLF rom_byte_mask, F
+261:           
+262:                       // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask
+263:                       if (rom_byte_mask == 0)
+0FB5  08BF     MOVF rom_byte_mask, F
+0FB6  1D03     BTFSS STATUS, 0x2
+0FB7  2FB9     GOTO 0x7B9
+0FB8  2FBA     GOTO 0x7BA
+0FB9  2FCA     GOTO 0x7CA
+264:                       {
+265:                           docrc8(romid[rom_byte_number]); // accumulate the CRC
+0FBA  0840     MOVF rom_byte_number, W
+0FBB  3E20     ADDLW 0x20
+0FBC  0086     MOVWF FSR1L
+0FBD  0187     CLRF FSR1H
+0FBE  0801     MOVF INDF1, W
+0FBF  3184     MOVLP 0x4
+0FC0  24ED     CALL 0x4ED
+0FC1  318F     MOVLP 0xF
+266:                           rom_byte_number++;
+0FC2  3001     MOVLW 0x1
+0FC3  0020     MOVLB 0x0
+0FC4  00B8     MOVWF bt
+0FC5  0838     MOVF bt, W
+0FC6  07C0     ADDWF rom_byte_number, F
+267:                           rom_byte_mask = 1;
+0FC7  01BF     CLRF rom_byte_mask
+0FC8  0ABF     INCF rom_byte_mask, F
+0FC9  2FCA     GOTO 0x7CA
+268:                       }
+269:                   } while (rom_byte_number < 8); // loop until all rom bytes 0-7
+0FCA  3008     MOVLW 0x8
+0FCB  0240     SUBWF rom_byte_number, W
+0FCC  1C03     BTFSS STATUS, 0x0
+0FCD  2FCF     GOTO 0x7CF
+0FCE  2FD0     GOTO 0x7D0
+0FCF  2F3B     GOTO 0x73B
+0FD0  2FD2     GOTO 0x7D2
+0FD1  2FD2     GOTO 0x7D2
+270:               } // end of not-last-device
+271:           
+272:               // if the search was succesful then
+273:               if (!(id_bit_number < 65 || crc8 != 0))
+0FD2  3041     MOVLW 0x41
+0FD3  023E     SUBWF id_bit_number, W
+0FD4  1C03     BTFSS STATUS, 0x0
+0FD5  2FD7     GOTO 0x7D7
+0FD6  2FD8     GOTO 0x7D8
+0FD7  2FEB     GOTO 0x7EB
+0FD8  08AB     MOVF crc8, F
+0FD9  1D03     BTFSS STATUS, 0x2
+0FDA  2FDC     GOTO 0x7DC
+0FDB  2FDD     GOTO 0x7DD
+0FDC  2FEB     GOTO 0x7EB
+274:               {
+275:                   // search successful
+276:                   LastDiscrepancy = last_zero;
+0FDD  083C     MOVF last_zero, W
+0FDE  00B8     MOVWF bt
+0FDF  0838     MOVF bt, W
+0FE0  00A9     MOVWF LastDiscrepancy
+277:           
+278:                   // check for last device
+279:                   if (LastDiscrepancy == 0)
+0FE1  08A9     MOVF LastDiscrepancy, F
+0FE2  1D03     BTFSS STATUS, 0x2
+0FE3  2FE5     GOTO 0x7E5
+0FE4  2FE6     GOTO 0x7E6
+0FE5  2FE8     GOTO 0x7E8
+280:                       LastDeviceFlag = true;
+0FE6  01A8     CLRF LastDeviceFlag
+0FE7  0AA8     INCF LastDeviceFlag, F
+281:           
+282:                   search_result = true;
+0FE8  01BA     CLRF search_result
+0FE9  0ABA     INCF search_result, F
+0FEA  2FEB     GOTO 0x7EB
+283:               }
+284:           
+285:               if (!search_result || !romid[0])
+0FEB  083A     MOVF search_result, W
+0FEC  1D03     BTFSS STATUS, 0x2
+0FED  2FEF     GOTO 0x7EF
+0FEE  2FF4     GOTO 0x7F4
+0FEF  08A0     MOVF romid, F
+0FF0  1D03     BTFSS STATUS, 0x2
+0FF1  2FF3     GOTO 0x7F3
+0FF2  2FF4     GOTO 0x7F4
+0FF3  2FF9     GOTO 0x7F9
+286:               {
+287:                   LastDiscrepancy = 0;
+0FF4  01A9     CLRF LastDiscrepancy
+288:                   LastDeviceFlag = false;
+0FF5  01A8     CLRF LastDeviceFlag
+289:                   LastFamilyDiscrepancy = 0;
+0FF6  01AA     CLRF LastFamilyDiscrepancy
+290:                   search_result = false;
+0FF7  01BA     CLRF search_result
+0FF8  2FF9     GOTO 0x7F9
+291:               }
+292:           
+293:               int_enable();
+0FF9  318B     MOVLP 0xB
+0FFA  2320     CALL 0x320
+0FFB  318F     MOVLP 0xF
+294:               return search_result;
+0FFC  0020     MOVLB 0x0
+0FFD  083A     MOVF search_result, W
+0FFE  2FFF     GOTO 0x7FF
+295:           }
+296:           
+297:           
+298:           void OW_search_init()
+299:           {
+300:               LastDiscrepancy = 0;
+0C8C  0020     MOVLB 0x0
+0C8D  01A9     CLRF LastDiscrepancy
+301:               LastDeviceFlag = false;
+0C8E  01A8     CLRF LastDeviceFlag
+302:               LastFamilyDiscrepancy = 0;
+0C8F  01AA     CLRF LastFamilyDiscrepancy
+303:           
+304:               for (int j=0; j<8; j++) romid[j]=0;
+0C90  01F4     CLRF i
+0C91  01F5     CLRF presence
+0C92  0875     MOVF presence, W
+0C93  3A80     XORLW 0x80
+0C94  00FF     MOVWF 0x7F
+0C95  3080     MOVLW 0x80
+0C96  027F     SUBWF 0x7F, W
+0C97  1D03     BTFSS STATUS, 0x2
+0C98  2C9B     GOTO 0x49B
+0C99  3008     MOVLW 0x8
+0C9A  0274     SUBWF i, W
+0C9B  1C03     BTFSS STATUS, 0x0
+0C9C  2C9E     GOTO 0x49E
+0C9D  2C9F     GOTO 0x49F
+0C9E  2CA1     GOTO 0x4A1
+0C9F  2CB8     GOTO 0x4B8
+0CA0  2CB8     GOTO 0x4B8
+0CA1  0874     MOVF i, W
+0CA2  3E20     ADDLW 0x20
+0CA3  0086     MOVWF FSR1L
+0CA4  0187     CLRF FSR1H
+0CA5  0181     CLRF INDF1
+0CA6  3001     MOVLW 0x1
+0CA7  07F4     ADDWF i, F
+0CA8  3000     MOVLW 0x0
+0CA9  3DF5     ADDWFC presence, F
+0CAA  0875     MOVF presence, W
+0CAB  3A80     XORLW 0x80
+0CAC  00FF     MOVWF 0x7F
+0CAD  3080     MOVLW 0x80
+0CAE  027F     SUBWF 0x7F, W
+0CAF  1D03     BTFSS STATUS, 0x2
+0CB0  2CB3     GOTO 0x4B3
+0CB1  3008     MOVLW 0x8
+0CB2  0274     SUBWF i, W
+0CB3  1C03     BTFSS STATUS, 0x0
+0CB4  2CB6     GOTO 0x4B6
+0CB5  2CB7     GOTO 0x4B7
+0CB6  2CA1     GOTO 0x4A1
+0CB7  2CB8     GOTO 0x4B8
+305:           }
+0CB8  0008     RETURN
+306:           
+307:           
+308:           /* ask the (lone) device for its Serial number */
+309:           void OW_identify()
+310:           {
+311:               int_disable();
+0D92  318B     MOVLP 0xB
+0D93  2322     CALL 0x322
+0D94  318D     MOVLP 0xD
+312:               OW_reset();
+0D95  318C     MOVLP 0xC
+0D96  2437     CALL 0x437
+0D97  318D     MOVLP 0xD
+313:               // read ROM command
+314:               OW_write_byte(0x33);
+0D98  3033     MOVLW 0x33
+0D99  318B     MOVLP 0xB
+0D9A  2390     CALL 0x390
+0D9B  318D     MOVLP 0xD
+315:               for (int j=0; j<8; j++)
+0D9C  0020     MOVLB 0x0
+0D9D  01B9     CLRF cmp_id_bit
+0D9E  01BA     CLRF search_result
+0D9F  083A     MOVF search_result, W
+0DA0  3A80     XORLW 0x80
+0DA1  00FF     MOVWF 0x7F
+0DA2  3080     MOVLW 0x80
+0DA3  027F     SUBWF 0x7F, W
+0DA4  1D03     BTFSS STATUS, 0x2
+0DA5  2DA8     GOTO 0x5A8
+0DA6  3008     MOVLW 0x8
+0DA7  0239     SUBWF cmp_id_bit, W
+0DA8  1C03     BTFSS STATUS, 0x0
+0DA9  2DAB     GOTO 0x5AB
+0DAA  2DAC     GOTO 0x5AC
+0DAB  2DAE     GOTO 0x5AE
+0DAC  2DCB     GOTO 0x5CB
+0DAD  2DCB     GOTO 0x5CB
+0DB9  3001     MOVLW 0x1
+0DBA  07B9     ADDWF cmp_id_bit, F
+0DBB  3000     MOVLW 0x0
+0DBC  3DBA     ADDWFC search_result, F
+0DBD  083A     MOVF search_result, W
+0DBE  3A80     XORLW 0x80
+0DBF  00FF     MOVWF 0x7F
+0DC0  3080     MOVLW 0x80
+0DC1  027F     SUBWF 0x7F, W
+0DC2  1D03     BTFSS STATUS, 0x2
+0DC3  2DC6     GOTO 0x5C6
+0DC4  3008     MOVLW 0x8
+0DC5  0239     SUBWF cmp_id_bit, W
+0DC6  1C03     BTFSS STATUS, 0x0
+0DC7  2DC9     GOTO 0x5C9
+0DC8  2DCA     GOTO 0x5CA
+0DC9  2DAE     GOTO 0x5AE
+0DCA  2DCB     GOTO 0x5CB
+316:                   romid[j] = OW_read_byte();
+0DAE  318C     MOVLP 0xC
+0DAF  2411     CALL 0x411
+0DB0  318D     MOVLP 0xD
+0DB1  0020     MOVLB 0x0
+0DB2  00B8     MOVWF bt
+0DB3  0839     MOVF cmp_id_bit, W
+0DB4  3E20     ADDLW 0x20
+0DB5  0086     MOVWF FSR1L
+0DB6  0187     CLRF FSR1H
+0DB7  0838     MOVF bt, W
+0DB8  0081     MOVWF INDF1
+317:               int_enable();
+0DCB  318B     MOVLP 0xB
+0DCC  2320     CALL 0x320
+0DCD  318D     MOVLP 0xD
+318:           }
+0DCE  0008     RETURN
+319:           
+320:           /* is anyone parasite powered ? */
+321:           bool OW_parasite(void)
+322:           {
+323:               int_disable();
+0BAE  318B     MOVLP 0xB
+0BAF  2322     CALL 0x322
+0BB0  318B     MOVLP 0xB
+324:               OW_reset();
+0BB1  318C     MOVLP 0xC
+0BB2  2437     CALL 0x437
+0BB3  318B     MOVLP 0xB
+325:               OW_write_byte(0xCC); // skip the rom command
+0BB4  30CC     MOVLW 0xCC
+0BB5  318B     MOVLP 0xB
+0BB6  2390     CALL 0x390
+0BB7  318B     MOVLP 0xB
+326:               OW_write_byte(0xB4); // are you parasite powered ?
+0BB8  30B4     MOVLW 0xB4
+0BB9  318B     MOVLP 0xB
+0BBA  2390     CALL 0x390
+0BBB  318B     MOVLP 0xB
+327:               bool no = OW_read_bit();
+0BBC  318B     MOVLP 0xB
+0BBD  2374     CALL 0x374
+0BBE  318B     MOVLP 0xB
+0BBF  0020     MOVLB 0x0
+0BC0  00B8     MOVWF bt
+0BC1  0838     MOVF bt, W
+0BC2  00B9     MOVWF cmp_id_bit
+328:               int_enable();
+0BC3  318B     MOVLP 0xB
+0BC4  2320     CALL 0x320
+0BC5  318B     MOVLP 0xB
+329:               return !no;
+0BC6  0020     MOVLB 0x0
+0BC7  0839     MOVF cmp_id_bit, W
+0BC8  3A00     XORLW 0x0
+0BC9  3000     MOVLW 0x0
+0BCA  1903     BTFSC STATUS, 0x2
+0BCB  3001     MOVLW 0x1
+0BCC  2BCD     GOTO 0x3CD
+330:           }
+0BCD  0008     RETURN
+331:           
+332:           /* select a specific device,
+333:            * if family==0 select all devices (skip rom)
+334:            */
+335:           static void OW_select_id(void)
+336:           {
+337:               if (romid[0] == 0) {
+0CE9  0020     MOVLB 0x0
+0CEA  08A0     MOVF romid, F
+0CEB  1D03     BTFSS STATUS, 0x2
+0CEC  2CEE     GOTO 0x4EE
+0CED  2CEF     GOTO 0x4EF
+0CEE  2CF4     GOTO 0x4F4
+338:                   OW_write_byte(0xCC); // all devices for now
+0CEF  30CC     MOVLW 0xCC
+0CF0  318B     MOVLP 0xB
+0CF1  2390     CALL 0x390
+0CF2  318C     MOVLP 0xC
+339:               } else {
+0CF3  2D19     GOTO 0x519
+340:                   OW_write_byte(0x55); // match rom
+0CF4  3055     MOVLW 0x55
+0CF5  318B     MOVLP 0xB
+0CF6  2390     CALL 0x390
+0CF7  318C     MOVLP 0xC
+341:                   for (int8_t j=0; j<8; j++) {
+0CF8  0020     MOVLB 0x0
+0CF9  01B9     CLRF cmp_id_bit
+0CFA  0839     MOVF cmp_id_bit, W
+0CFB  3A80     XORLW 0x80
+0CFC  3E78     ADDLW 0x78
+0CFD  1C03     BTFSS STATUS, 0x0
+0CFE  2D00     GOTO 0x500
+0CFF  2D01     GOTO 0x501
+0D00  2D03     GOTO 0x503
+0D01  2D19     GOTO 0x519
+0D02  2D19     GOTO 0x519
+0D0B  3001     MOVLW 0x1
+0D0C  0020     MOVLB 0x0
+0D0D  00B8     MOVWF bt
+0D0E  0838     MOVF bt, W
+0D0F  07B9     ADDWF cmp_id_bit, F
+0D10  0839     MOVF cmp_id_bit, W
+0D11  3A80     XORLW 0x80
+0D12  3E78     ADDLW 0x78
+0D13  1C03     BTFSS STATUS, 0x0
+0D14  2D16     GOTO 0x516
+0D15  2D17     GOTO 0x517
+0D16  2D03     GOTO 0x503
+0D17  2D19     GOTO 0x519
+0D18  2D19     GOTO 0x519
+342:                       OW_write_byte(romid[j]);
+0D03  0839     MOVF cmp_id_bit, W
+0D04  3E20     ADDLW 0x20
+0D05  0086     MOVWF FSR1L
+0D06  0187     CLRF FSR1H
+0D07  0801     MOVF INDF1, W
+0D08  318B     MOVLP 0xB
+0D09  2390     CALL 0x390
+0D0A  318C     MOVLP 0xC
+343:                   }
+344:               }
+345:           }
+0D19  0008     RETURN
+346:           
+347:           
+348:           /* read a memory block eg scratchpad 0xBE */
+349:           void OW_read_block(uint8_t code, uint8_t * data, uint8_t len)
+350:           {
+0D1A  0020     MOVLB 0x0
+0D1B  00BF     MOVWF rom_byte_mask
+351:               int_disable();
+0D1C  318B     MOVLP 0xB
+0D1D  2322     CALL 0x322
+0D1E  318D     MOVLP 0xD
+352:               OW_reset();
+0D1F  318C     MOVLP 0xC
+0D20  2437     CALL 0x437
+0D21  318D     MOVLP 0xD
+353:               OW_select_id();
+0D22  318C     MOVLP 0xC
+0D23  24E9     CALL 0x4E9
+0D24  318D     MOVLP 0xD
+354:               OW_write_byte(code);
+0D25  0020     MOVLB 0x0
+0D26  083F     MOVF rom_byte_mask, W
+0D27  318B     MOVLP 0xB
+0D28  2390     CALL 0x390
+0D29  318D     MOVLP 0xD
+355:               for (int8_t j=0; j<len; j++)
+0D2A  0020     MOVLB 0x0
+0D2B  01C0     CLRF rom_byte_number
+0D2C  2D3F     GOTO 0x53F
+0D3A  3001     MOVLW 0x1
+0D3B  00BC     MOVWF last_zero
+0D3C  083C     MOVF last_zero, W
+0D3D  07C0     ADDWF rom_byte_number, F
+0D3E  2D3F     GOTO 0x53F
+0D3F  0840     MOVF rom_byte_number, W
+0D40  00BC     MOVWF last_zero
+0D41  01BD     CLRF search_direction
+0D42  1BBC     BTFSC last_zero, 0x7
+0D43  03BD     DECF search_direction, F
+0D44  083D     MOVF search_direction, W
+0D45  3A80     XORLW 0x80
+0D46  00BE     MOVWF id_bit_number
+0D47  3080     MOVLW 0x80
+0D48  023E     SUBWF id_bit_number, W
+0D49  1D03     BTFSS STATUS, 0x2
+0D4A  2D4D     GOTO 0x54D
+0D4B  083B     MOVF id_bit, W
+0D4C  023C     SUBWF last_zero, W
+0D4D  1C03     BTFSS STATUS, 0x0
+0D4E  2D50     GOTO 0x550
+0D4F  2D51     GOTO 0x551
+0D50  2D2D     GOTO 0x52D
+0D51  2D52     GOTO 0x552
+356:                   data[j] = OW_read_byte();
+0D2D  318C     MOVLP 0xC
+0D2E  2411     CALL 0x411
+0D2F  318D     MOVLP 0xD
+0D30  0020     MOVLB 0x0
+0D31  00BC     MOVWF last_zero
+0D32  0840     MOVF rom_byte_number, W
+0D33  073A     ADDWF search_result, W
+0D34  00BD     MOVWF search_direction
+0D35  083D     MOVF search_direction, W
+0D36  0086     MOVWF FSR1L
+0D37  0187     CLRF FSR1H
+0D38  083C     MOVF last_zero, W
+0D39  0081     MOVWF INDF1
+357:               int_enable();
+0D52  318B     MOVLP 0xB
+0D53  2320     CALL 0x320
+0D54  318D     MOVLP 0xD
+358:           }
+0D55  0008     RETURN
+359:           
+360:           /* write a memory block to device, eg scratchpad 0x4E */
+361:           void OW_write_block(uint8_t code, uint8_t * data, uint8_t len)
+362:           {
+363:               int_disable();
+364:               OW_reset();
+365:               OW_select_id();
+366:               OW_write_byte(code);
+367:               for (int8_t j=0; j<len; j++) {
+368:                   OW_write_byte(data[j]);
+369:               }
+370:               int_enable();
+371:           }
+372:           
+373:           
+374:           // perform temperature conversion
+375:           void OW_convert()
+376:           {
+377:               // first see if anyone is parasitic
+378:               bool para = OW_parasite();
+0EA0  318B     MOVLP 0xB
+0EA1  23AE     CALL 0x3AE
+0EA2  318E     MOVLP 0xE
+0EA3  0020     MOVLB 0x0
+0EA4  00BA     MOVWF search_result
+0EA5  083A     MOVF search_result, W
+0EA6  00BD     MOVWF search_direction
+379:           
+380:               int_disable();
+0EA7  318B     MOVLP 0xB
+0EA8  2322     CALL 0x322
+0EA9  318E     MOVLP 0xE
+381:               OW_reset(); // all command start with reset
+0EAA  318C     MOVLP 0xC
+0EAB  2437     CALL 0x437
+0EAC  318E     MOVLP 0xE
+382:               OW_select_id();
+0EAD  318C     MOVLP 0xC
+0EAE  24E9     CALL 0x4E9
+0EAF  318E     MOVLP 0xE
+383:               //OW_write_byte(0xCC); // all devices
+384:               OW_write_byte(0x44); // convert
+0EB0  3044     MOVLW 0x44
+0EB1  318B     MOVLP 0xB
+0EB2  2390     CALL 0x390
+0EB3  318E     MOVLP 0xE
+385:               if (para) {
+0EB4  0020     MOVLB 0x0
+0EB5  083D     MOVF search_direction, W
+0EB6  1D03     BTFSS STATUS, 0x2
+0EB7  2EB9     GOTO 0x6B9
+0EB8  2EF6     GOTO 0x6F6
+386:                   // hard high for 750mS
+387:                   OWHIGH;
+0EB9  150C     BSF PORTA, 0x2
+0EBA  0021     MOVLB 0x1
+0EBB  110C     BCF PORTA, 0x2
+388:                   DelayUs(250000);
+0EBC  3002     MOVLW 0x2
+0EBD  0020     MOVLB 0x0
+0EBE  00BC     MOVWF last_zero
+0EBF  3045     MOVLW 0x45
+0EC0  00BB     MOVWF id_bit
+0EC1  30A9     MOVLW 0xA9
+0EC2  00BA     MOVWF search_result
+0EC3  0BBA     DECFSZ search_result, F
+0EC4  2EC3     GOTO 0x6C3
+0EC5  0BBB     DECFSZ id_bit, F
+0EC6  2EC3     GOTO 0x6C3
+0EC7  0BBC     DECFSZ last_zero, F
+0EC8  2EC3     GOTO 0x6C3
+0EC9  2ECA     GOTO 0x6CA
+389:                   DelayUs(250000);
+0ECA  3002     MOVLW 0x2
+0ECB  0020     MOVLB 0x0
+0ECC  00BC     MOVWF last_zero
+0ECD  3045     MOVLW 0x45
+0ECE  00BB     MOVWF id_bit
+0ECF  30A9     MOVLW 0xA9
+0ED0  00BA     MOVWF search_result
+0ED1  0BBA     DECFSZ search_result, F
+0ED2  2ED1     GOTO 0x6D1
+0ED3  0BBB     DECFSZ id_bit, F
+0ED4  2ED1     GOTO 0x6D1
+0ED5  0BBC     DECFSZ last_zero, F
+0ED6  2ED1     GOTO 0x6D1
+0ED7  2ED8     GOTO 0x6D8
+390:                   DelayUs(250000);
+0ED8  3002     MOVLW 0x2
+0ED9  0020     MOVLB 0x0
+0EDA  00BC     MOVWF last_zero
+0EDB  3045     MOVLW 0x45
+0EDC  00BB     MOVWF id_bit
+0EDD  30A9     MOVLW 0xA9
+0EDE  00BA     MOVWF search_result
+0EDF  0BBA     DECFSZ search_result, F
+0EE0  2EDF     GOTO 0x6DF
+0EE1  0BBB     DECFSZ id_bit, F
+0EE2  2EDF     GOTO 0x6DF
+0EE3  0BBC     DECFSZ last_zero, F
+0EE4  2EDF     GOTO 0x6DF
+0EE5  2EE6     GOTO 0x6E6
+391:                   DelayUs(250000);
+0EE6  3002     MOVLW 0x2
+0EE7  0020     MOVLB 0x0
+0EE8  00BC     MOVWF last_zero
+0EE9  3045     MOVLW 0x45
+0EEA  00BB     MOVWF id_bit
+0EEB  30A9     MOVLW 0xA9
+0EEC  00BA     MOVWF search_result
+0EED  0BBA     DECFSZ search_result, F
+0EEE  2EED     GOTO 0x6ED
+0EEF  0BBB     DECFSZ id_bit, F
+0EF0  2EED     GOTO 0x6ED
+0EF1  0BBC     DECFSZ last_zero, F
+0EF2  2EED     GOTO 0x6ED
+0EF3  2EF4     GOTO 0x6F4
+392:               } else {
+0EF4  2F08     GOTO 0x708
+0EF5  2EF6     GOTO 0x6F6
+393:                   // keep polling until its done
+394:                   // device will reply with 0 'pull low' whilst convert in progress
+395:                   do {
+396:                       DelayUs(1000);
+0EF6  30F9     MOVLW 0xF9
+0EF7  0020     MOVLB 0x0
+0EF8  00BA     MOVWF search_result
+0EF9  0000     NOP
+0EFA  0BBA     DECFSZ search_result, F
+0EFB  2EF9     GOTO 0x6F9
+0EFC  2EFD     GOTO 0x6FD
+0EFD  0000     NOP
+397:                   } while (!OW_read_bit());
+0EFE  318B     MOVLP 0xB
+0EFF  2374     CALL 0x374
+0F00  318E     MOVLP 0xE
+0F01  3A00     XORLW 0x0
+0F02  1903     BTFSC STATUS, 0x2
+0F03  2F05     GOTO 0x705
+0F04  2F06     GOTO 0x706
+0F05  2EF6     GOTO 0x6F6
+0F06  2F08     GOTO 0x708
+0F07  2F08     GOTO 0x708
+398:               }
+399:               int_enable();
+0F08  318B     MOVLP 0xB
+0F09  2320     CALL 0x320
+0F0A  318E     MOVLP 0xE
+400:           }
+0F0B  0008     RETURN
+401:           
+402:           /* Available commands :-
+403:            * 33h - read rom  (sends 8 bytes)
+404:            * 55h - match rom (reads 8 bytes)
+405:            * F0h - search rom (enumeration mode)
+406:            * ECh - alarm search
+407:            * CC  - skip rom command
+408:            *
+409:            * followed by....
+410:            * 44h - convert temperature
+411:            * 48h - copy scratchpad -> eeprom
+412:            * 4Eh - write scratchpad (send 3 bytes )
+413:            * BEh - read scratchpad ( 8 bytes + crc)
+414:            * B8h - recall EEPROM -> scratchpad
+415:            * B4h - read power supply (read 1 bit)
+416:            */
+---  /home/justin/MPLABXProjects/uart test.X/main.c  ----------------------------------------------------
+1:             /******************************************************************************/
+2:             /* Files to Include                                                           */
+3:             /******************************************************************************/
+4:             
+5:             #if defined(__XC)
+6:                 #include <xc.h>         /* XC8 General Include File */
+7:             #elif defined(HI_TECH_C)
+8:                 #include <htc.h>        /* HiTech General Include File */
+9:             #endif
+10:            
+11:            #include <stdio.h>
+12:            
+13:            #include <stdint.h>        /* For uint8_t definition */
+14:            #include <stdbool.h>       /* For true/false definition */
+15:            
+16:            #include "system.h"        /* System funct/params, like osc/peripheral config */
+17:            #include "user.h"          /* User funct/params, such as InitApp */
+18:            
+19:            #include "onewire.h"        /* 1-wire bus functions */
+20:            
+21:            /******************************************************************************/
+22:            /* User Global Variable Declaration                                           */
+23:            /******************************************************************************/
+24:            
+25:            /* i.e. uint8_t <variable_name>; */
+26:            
+27:            char outbuff[100];
+28:            char * outp = 0;
+29:            uint8_t outlen = 0;
+30:            
+31:            char inbuff[10];
+32:            uint8_t inlen = 0;
+33:            
+34:            /******************************************************************************/
+35:            /* Main Program                                                               */
+36:            /******************************************************************************/
+37:            
+38:            char prompt[9];
+39:            
+40:            const char * banner = "\r\n\n\nPIC 1-Wire Bridge system.  Press 'H' for help.\r\n";
+41:            
+42:            void main(void)
+43:            {
+44:                prompt[0] = 'c';
+002A  3063     MOVLW 0x63
+002B  0020     MOVLB 0x0
+002C  00C1     MOVWF 0x41
+002D  0841     MOVF 0x41, W
+002E  00AC     MOVWF prompt
+45:                prompt[1] = 'm';
+002F  306D     MOVLW 0x6D
+0030  00C1     MOVWF 0x41
+0031  0841     MOVF 0x41, W
+0032  00AD     MOVWF 0x2D
+46:                prompt[2] = 'd';
+0033  3064     MOVLW 0x64
+0034  00C1     MOVWF 0x41
+0035  0841     MOVF 0x41, W
+0036  00AE     MOVWF 0x2E
+47:                prompt[3] = ' ';
+0037  3020     MOVLW 0x20
+0038  00C1     MOVWF 0x41
+0039  0841     MOVF 0x41, W
+003A  00AF     MOVWF 0x2F
+48:                prompt[4] = '?';
+003B  303F     MOVLW 0x3F
+003C  00C1     MOVWF 0x41
+003D  0841     MOVF 0x41, W
+003E  00B0     MOVWF 0x30
+49:                prompt[5] = '?';
+003F  303F     MOVLW 0x3F
+0040  00C1     MOVWF 0x41
+0041  0841     MOVF 0x41, W
+0042  00B1     MOVWF 0x31
+50:                prompt[6] = '>';
+0043  303E     MOVLW 0x3E
+0044  00C1     MOVWF 0x41
+0045  0841     MOVF 0x41, W
+0046  00B2     MOVWF 0x32
+51:                prompt[7] = ' ';
+0047  3020     MOVLW 0x20
+0048  00C1     MOVWF 0x41
+0049  0841     MOVF 0x41, W
+004A  00B3     MOVWF 0x33
+52:                prompt[8] = 0;
+004B  01B4     CLRF 0x34
+53:            
+54:                bool usermode = false;
+004C  0021     MOVLB 0x1
+004D  01CC     CLRF 0x4C
+55:            
+56:                /* Configure the oscillator for the device */
+57:                ConfigureOscillator();
+004E  318B     MOVLP 0xB
+004F  231F     CALL 0x31F
+0050  3180     MOVLP 0x0
+58:            
+59:                /* Initialize I/O and Peripherals for application */
+60:                InitApp();
+0051  318B     MOVLP 0xB
+0052  23CE     CALL 0x3CE
+0053  3180     MOVLP 0x0
+61:            
+62:                OW_start();
+0054  318B     MOVLP 0xB
+0055  2324     CALL 0x324
+0056  3180     MOVLP 0x0
+63:                msg_write(banner);
+0057  0020     MOVLB 0x0
+0058  0844     MOVF 0x44, W
+0059  01F5     CLRF presence
+005A  07F5     ADDWF presence, F
+005B  0843     MOVF banner, W
+005C  01F4     CLRF i
+005D  07F4     ADDWF i, F
+005E  318E     MOVLP 0xE
+005F  2613     CALL 0x613
+0060  3180     MOVLP 0x0
+0061  2862     GOTO 0x62
+64:                //msg_write(prompt);
+65:            
+66:                while(1)
+04EA  2862     GOTO 0x62
+67:                {
+68:                    if (TRISAbits.TRISA2 == 1) {
+0062  0021     MOVLB 0x1
+0063  1D0C     BTFSS PORTA, 0x2
+0064  2866     GOTO 0x66
+0065  2867     GOTO 0x67
+0066  2881     GOTO 0x81
+69:                        prompt[4] = 'i';
+0067  3069     MOVLW 0x69
+0068  0020     MOVLB 0x0
+0069  00C1     MOVWF 0x41
+006A  0841     MOVF 0x41, W
+006B  00B0     MOVWF 0x30
+70:                        prompt[5] = PORTAbits.RA2 ? '1':'0';
+006C  190C     BTFSC PORTA, 0x2
+006D  286F     GOTO 0x6F
+006E  2870     GOTO 0x70
+006F  2876     GOTO 0x76
+0070  3030     MOVLW 0x30
+0071  0021     MOVLB 0x1
+0072  00B4     MOVWF 0x34
+0073  3000     MOVLW 0x0
+0074  00B5     MOVWF in
+0075  287B     GOTO 0x7B
+0076  3031     MOVLW 0x31
+0077  0021     MOVLB 0x1
+0078  00B4     MOVWF 0x34
+0079  3000     MOVLW 0x0
+007A  00B5     MOVWF in
+007B  0834     MOVF 0x34, W
+007C  0020     MOVLB 0x0
+007D  00C1     MOVWF 0x41
+007E  0841     MOVF 0x41, W
+007F  00B1     MOVWF 0x31
+71:                    } else {
+0080  289B     GOTO 0x9B
+72:                        prompt[4] = 'o';
+0081  306F     MOVLW 0x6F
+0082  0020     MOVLB 0x0
+0083  00C1     MOVWF 0x41
+0084  0841     MOVF 0x41, W
+0085  00B0     MOVWF 0x30
+73:                        prompt[5] = PORTAbits.RA2 ? '1':'0';
+0086  190C     BTFSC PORTA, 0x2
+0087  2889     GOTO 0x89
+0088  288A     GOTO 0x8A
+0089  2890     GOTO 0x90
+008A  3030     MOVLW 0x30
+008B  0021     MOVLB 0x1
+008C  00B6     MOVWF p
+008D  3000     MOVLW 0x0
+008E  00B7     MOVWF i
+008F  2895     GOTO 0x95
+0090  3031     MOVLW 0x31
+0091  0021     MOVLB 0x1
+0092  00B6     MOVWF p
+0093  3000     MOVLW 0x0
+0094  00B7     MOVWF i
+0095  0836     MOVF p, W
+0096  0020     MOVLB 0x0
+0097  00C1     MOVWF 0x41
+0098  0841     MOVF 0x41, W
+0099  00B1     MOVWF 0x31
+009A  289B     GOTO 0x9B
+74:                    }
+75:            
+76:                    if (!msg_empty()) continue;
+009B  318B     MOVLP 0xB
+009C  2344     CALL 0x344
+009D  3180     MOVLP 0x0
+009E  3800     IORLW 0x0
+009F  1D03     BTFSS STATUS, 0x2
+00A0  28A2     GOTO 0xA2
+00A1  28A3     GOTO 0xA3
+00A2  28A5     GOTO 0xA5
+00A3  2862     GOTO 0x62
+00A4  2862     GOTO 0x62
+77:            
+78:                    if (!msg_recvready()) continue;
+00A5  318B     MOVLP 0xB
+00A6  233A     CALL 0x33A
+00A7  3180     MOVLP 0x0
+00A8  3800     IORLW 0x0
+00A9  1D03     BTFSS STATUS, 0x2
+00AA  28AC     GOTO 0xAC
+00AB  28AD     GOTO 0xAD
+00AC  28AF     GOTO 0xAF
+00AD  2862     GOTO 0x62
+00AE  2862     GOTO 0x62
+79:            
+80:                    char cmd = msg_recv();
+00AF  318D     MOVLP 0xD
+00B0  2556     CALL 0x556
+00B1  3180     MOVLP 0x0
+00B2  0020     MOVLB 0x0
+00B3  00C1     MOVWF 0x41
+00B4  0841     MOVF 0x41, W
+00B5  0021     MOVLB 0x1
+00B6  00CB     MOVWF 0x4B
+81:                    
+82:                    if (cmd == '\r' || cmd == '\n') {
+00B7  084B     MOVF 0x4B, W
+00B8  3A0D     XORLW 0xD
+00B9  1903     BTFSC STATUS, 0x2
+00BA  28BC     GOTO 0xBC
+00BB  28BD     GOTO 0xBD
+00BC  28C4     GOTO 0xC4
+00BD  084B     MOVF 0x4B, W
+00BE  3A0A     XORLW 0xA
+00BF  1D03     BTFSS STATUS, 0x2
+00C0  28C2     GOTO 0xC2
+00C1  28C3     GOTO 0xC3
+00C2  28D1     GOTO 0xD1
+00C3  28C4     GOTO 0xC4
+83:                        if (usermode) msg_write("\r\n");
+00C4  084C     MOVF 0x4C, W
+00C5  1D03     BTFSS STATUS, 0x2
+00C6  28C8     GOTO 0xC8
+00C7  2CDC     GOTO 0x4DC
+00C8  3059     MOVLW 0x59
+00C9  00F4     MOVWF i
+00CA  3086     MOVLW 0x86
+00CB  00F5     MOVWF presence
+00CC  318E     MOVLP 0xE
+00CD  2613     CALL 0x613
+00CE  3180     MOVLP 0x0
+00CF  2CDC     GOTO 0x4DC
+84:                    }else
+00D0  2CDC     GOTO 0x4DC
+85:                    if (cmd == 'h' || cmd == 'H') {
+00D1  0021     MOVLB 0x1
+00D2  084B     MOVF 0x4B, W
+00D3  3A68     XORLW 0x68
+00D4  1903     BTFSC STATUS, 0x2
+00D5  28D7     GOTO 0xD7
+00D6  28D8     GOTO 0xD8
+00D7  28DF     GOTO 0xDF
+00D8  084B     MOVF 0x4B, W
+00D9  3A48     XORLW 0x48
+00DA  1D03     BTFSS STATUS, 0x2
+00DB  28DD     GOTO 0xDD
+00DC  28DE     GOTO 0xDE
+00DD  2951     GOTO 0x151
+00DE  28DF     GOTO 0xDF
+86:                        msg_write(banner);
+00DF  0020     MOVLB 0x0
+00E0  0844     MOVF 0x44, W
+00E1  01F5     CLRF presence
+00E2  07F5     ADDWF presence, F
+00E3  0843     MOVF banner, W
+00E4  01F4     CLRF i
+00E5  07F4     ADDWF i, F
+00E6  318E     MOVLP 0xE
+00E7  2613     CALL 0x613
+00E8  3180     MOVLP 0x0
+87:                        msg_write("\nHelp:\r\n");
+00E9  3070     MOVLW 0x70
+00EA  00F4     MOVWF i
+00EB  3088     MOVLW 0x88
+00EC  00F5     MOVWF presence
+00ED  318E     MOVLP 0xE
+00EE  2613     CALL 0x613
+00EF  3180     MOVLP 0x0
+88:                        while (!msg_empty());
+00F0  28F2     GOTO 0xF2
+00F1  28F2     GOTO 0xF2
+00F2  318B     MOVLP 0xB
+00F3  2344     CALL 0x344
+00F4  3180     MOVLP 0x0
+00F5  3A00     XORLW 0x0
+00F6  1903     BTFSC STATUS, 0x2
+00F7  28F9     GOTO 0xF9
+00F8  28FA     GOTO 0xFA
+00F9  28F2     GOTO 0xF2
+00FA  28FB     GOTO 0xFB
+89:                        msg_write("E - Enumerate the Bus\r\n");
+00FB  30E2     MOVLW 0xE2
+00FC  00F4     MOVWF i
+00FD  3087     MOVLW 0x87
+00FE  00F5     MOVWF presence
+00FF  318E     MOVLP 0xE
+0100  2613     CALL 0x613
+0101  3180     MOVLP 0x0
+90:                        msg_write("R - Reset Bus\r\n");
+0102  303F     MOVLW 0x3F
+0103  00F4     MOVWF i
+0104  3088     MOVLW 0x88
+0105  00F5     MOVWF presence
+0106  318E     MOVLP 0xE
+0107  2613     CALL 0x613
+0108  3180     MOVLP 0x0
+91:                        while (!msg_empty());
+0109  290B     GOTO 0x10B
+010A  290B     GOTO 0x10B
+010B  318B     MOVLP 0xB
+010C  2344     CALL 0x344
+010D  3180     MOVLP 0x0
+010E  3A00     XORLW 0x0
+010F  1903     BTFSC STATUS, 0x2
+0110  2912     GOTO 0x112
+0111  2913     GOTO 0x113
+0112  290B     GOTO 0x10B
+0113  2914     GOTO 0x114
+92:                        msg_write("0,1,3 - bus to Low, High, Tristate\r\n");
+0114  3082     MOVLW 0x82
+0115  00F4     MOVWF i
+0116  3086     MOVLW 0x86
+0117  00F5     MOVWF presence
+0118  318E     MOVLP 0xE
+0119  2613     CALL 0x613
+011A  3180     MOVLP 0x0
+93:                        msg_write("I - Read (one) Device ID\r\n");
+011B  3064     MOVLW 0x64
+011C  00F4     MOVWF i
+011D  3087     MOVLW 0x87
+011E  00F5     MOVWF presence
+011F  318E     MOVLP 0xE
+0120  2613     CALL 0x613
+0121  3180     MOVLP 0x0
+94:                        while (!msg_empty());
+0122  2924     GOTO 0x124
+0123  2924     GOTO 0x124
+0124  318B     MOVLP 0xB
+0125  2344     CALL 0x344
+0126  3180     MOVLP 0x0
+0127  3A00     XORLW 0x0
+0128  1903     BTFSC STATUS, 0x2
+0129  292B     GOTO 0x12B
+012A  292C     GOTO 0x12C
+012B  2924     GOTO 0x124
+012C  292D     GOTO 0x12D
+95:                        msg_write("P - Any device parasitic powered?\r\n");
+012D  30A7     MOVLW 0xA7
+012E  00F4     MOVWF i
+012F  3086     MOVLW 0x86
+0130  00F5     MOVWF presence
+0131  318E     MOVLP 0xE
+0132  2613     CALL 0x613
+0133  3180     MOVLP 0x0
+96:                        msg_write("S - Read scratchpad memory\r\n");
+0134  302B     MOVLW 0x2B
+0135  00F4     MOVWF i
+0136  3087     MOVLW 0x87
+0137  00F5     MOVWF presence
+0138  318E     MOVLP 0xE
+0139  2613     CALL 0x613
+013A  3180     MOVLP 0x0
+97:                        while (!msg_empty());
+013B  293D     GOTO 0x13D
+013C  293D     GOTO 0x13D
+013D  318B     MOVLP 0xB
+013E  2344     CALL 0x344
+013F  3180     MOVLP 0x0
+0140  3A00     XORLW 0x0
+0141  1903     BTFSC STATUS, 0x2
+0142  2944     GOTO 0x144
+0143  2945     GOTO 0x145
+0144  293D     GOTO 0x13D
+0145  2946     GOTO 0x146
+98:                        msg_write("T - read temperature of all devices\r\n");
+0146  305C     MOVLW 0x5C
+0147  00F4     MOVWF i
+0148  3086     MOVLW 0x86
+0149  00F5     MOVWF presence
+014A  318E     MOVLP 0xE
+014B  2613     CALL 0x613
+014C  3180     MOVLP 0x0
+99:                        usermode = true;
+014D  0021     MOVLB 0x1
+014E  01CC     CLRF 0x4C
+014F  0ACC     INCF 0x4C, F
+100:                   } else
+0150  2CDC     GOTO 0x4DC
+101:                   if (cmd == 'r' || cmd == 'R') {
+0151  084B     MOVF 0x4B, W
+0152  3A72     XORLW 0x72
+0153  1903     BTFSC STATUS, 0x2
+0154  2956     GOTO 0x156
+0155  2957     GOTO 0x157
+0156  295E     GOTO 0x15E
+0157  084B     MOVF 0x4B, W
+0158  3A52     XORLW 0x52
+0159  1D03     BTFSS STATUS, 0x2
+015A  295C     GOTO 0x15C
+015B  295D     GOTO 0x15D
+015C  298F     GOTO 0x18F
+015D  295E     GOTO 0x15E
+102:                       int_disable();
+015E  318B     MOVLP 0xB
+015F  2322     CALL 0x322
+0160  3180     MOVLP 0x0
+103:                       bool present = OW_reset();
+0161  318C     MOVLP 0xC
+0162  2437     CALL 0x437
+0163  3180     MOVLP 0x0
+0164  0020     MOVLB 0x0
+0165  00C1     MOVWF 0x41
+0166  0841     MOVF 0x41, W
+0167  0021     MOVLB 0x1
+0168  00B2     MOVWF 0x32
+104:                       int_enable();
+0169  318B     MOVLP 0xB
+016A  2320     CALL 0x320
+016B  3180     MOVLP 0x0
+105:                       if (usermode) msg_write("\r");
+016C  0021     MOVLB 0x1
+016D  084C     MOVF 0x4C, W
+016E  1D03     BTFSS STATUS, 0x2
+016F  2971     GOTO 0x171
+0170  2979     GOTO 0x179
+0171  30B2     MOVLW 0xB2
+0172  00F4     MOVWF i
+0173  3088     MOVLW 0x88
+0174  00F5     MOVWF presence
+0175  318E     MOVLP 0xE
+0176  2613     CALL 0x613
+0177  3180     MOVLP 0x0
+0178  2979     GOTO 0x179
+106:                       if (present)
+0179  0021     MOVLB 0x1
+017A  0832     MOVF 0x32, W
+017B  1D03     BTFSS STATUS, 0x2
+017C  297E     GOTO 0x17E
+017D  2986     GOTO 0x186
+107:                           msg_write("RESET Device detected.\r\n");
+017E  307F     MOVLW 0x7F
+017F  00F4     MOVWF i
+0180  3087     MOVLW 0x87
+0181  00F5     MOVWF presence
+0182  318E     MOVLP 0xE
+0183  2613     CALL 0x613
+0184  3180     MOVLP 0x0
+0185  2CDC     GOTO 0x4DC
+108:                       else
+109:                           msg_write("RESET No Devices detected.\r\n");
+0186  300E     MOVLW 0xE
+0187  00F4     MOVWF i
+0188  3087     MOVLW 0x87
+0189  00F5     MOVWF presence
+018A  318E     MOVLP 0xE
+018B  2613     CALL 0x613
+018C  3180     MOVLP 0x0
+018D  2CDC     GOTO 0x4DC
+110:                   } else
+018E  2CDC     GOTO 0x4DC
+111:                   if (cmd == 'e' || cmd == 'E')
+018F  0021     MOVLB 0x1
+0190  084B     MOVF 0x4B, W
+0191  3A65     XORLW 0x65
+0192  1903     BTFSC STATUS, 0x2
+0193  2995     GOTO 0x195
+0194  2996     GOTO 0x196
+0195  299C     GOTO 0x19C
+0196  084B     MOVF 0x4B, W
+0197  3A45     XORLW 0x45
+0198  1D03     BTFSS STATUS, 0x2
+0199  299B     GOTO 0x19B
+019A  299C     GOTO 0x19C
+019B  2A25     GOTO 0x225
+112:                   {
+113:                       char count = 0;
+019C  01C1     CLRF 0x41
+114:                       if (usermode) msg_write("\r");
+019D  084C     MOVF 0x4C, W
+019E  1D03     BTFSS STATUS, 0x2
+019F  29A1     GOTO 0x1A1
+01A0  29A9     GOTO 0x1A9
+01A1  30B2     MOVLW 0xB2
+01A2  00F4     MOVWF i
+01A3  3088     MOVLW 0x88
+01A4  00F5     MOVWF presence
+01A5  318E     MOVLP 0xE
+01A6  2613     CALL 0x613
+01A7  3180     MOVLP 0x0
+01A8  29A9     GOTO 0x1A9
+115:                       OW_search_init();
+01A9  318C     MOVLP 0xC
+01AA  248C     CALL 0x48C
+01AB  3180     MOVLP 0x0
+116:                       while (OW_search())
+01AC  2A00     GOTO 0x200
+0200  318F     MOVLP 0xF
+0201  270C     CALL 0x70C
+0202  3180     MOVLP 0x0
+0203  3800     IORLW 0x0
+0204  1D03     BTFSS STATUS, 0x2
+0205  2A07     GOTO 0x207
+0206  2A08     GOTO 0x208
+0207  29AD     GOTO 0x1AD
+0208  2A09     GOTO 0x209
+117:                       {
+118:                           char val[3];
+119:                           if (usermode) msg_write("ENUM ");
+01AD  0021     MOVLB 0x1
+01AE  084C     MOVF 0x4C, W
+01AF  1D03     BTFSS STATUS, 0x2
+01B0  29B2     GOTO 0x1B2
+01B1  29BA     GOTO 0x1BA
+01B2  309D     MOVLW 0x9D
+01B3  00F4     MOVWF i
+01B4  3088     MOVLW 0x88
+01B5  00F5     MOVWF presence
+01B6  318E     MOVLP 0xE
+01B7  2613     CALL 0x613
+01B8  3180     MOVLP 0x0
+01B9  29BA     GOTO 0x1BA
+120:                           for (char j=0; j<8; j++) {
+01BA  0021     MOVLB 0x1
+01BB  01C6     CLRF 0x46
+01BC  3008     MOVLW 0x8
+01BD  0246     SUBWF 0x46, W
+01BE  1C03     BTFSS STATUS, 0x0
+01BF  29C1     GOTO 0x1C1
+01C0  29C2     GOTO 0x1C2
+01C1  29C4     GOTO 0x1C4
+01C2  29E5     GOTO 0x1E5
+01C3  29E5     GOTO 0x1E5
+01D8  3001     MOVLW 0x1
+01D9  0020     MOVLB 0x0
+01DA  00C1     MOVWF 0x41
+01DB  0841     MOVF 0x41, W
+01DC  0021     MOVLB 0x1
+01DD  07C6     ADDWF 0x46, F
+01DE  3008     MOVLW 0x8
+01DF  0246     SUBWF 0x46, W
+01E0  1C03     BTFSS STATUS, 0x0
+01E1  29E3     GOTO 0x1E3
+01E2  29E4     GOTO 0x1E4
+01E3  29C4     GOTO 0x1C4
+01E4  29E5     GOTO 0x1E5
+121:                               tohex(val, romid[j]);
+01C4  0846     MOVF 0x46, W
+01C5  3E20     ADDLW 0x20
+01C6  0086     MOVWF FSR1L
+01C7  0187     CLRF FSR1H
+01C8  0801     MOVF INDF1, W
+01C9  0020     MOVLB 0x0
+01CA  00C1     MOVWF 0x41
+01CB  0841     MOVF 0x41, W
+01CC  00F4     MOVWF i
+01CD  30B8     MOVLW 0xB8
+01CE  318E     MOVLP 0xE
+01CF  2659     CALL 0x659
+01D0  3180     MOVLP 0x0
+122:                               msg_write(val);
+01D1  30B8     MOVLW 0xB8
+01D2  00F4     MOVWF i
+01D3  3000     MOVLW 0x0
+01D4  00F5     MOVWF presence
+01D5  318E     MOVLP 0xE
+01D6  2613     CALL 0x613
+01D7  3180     MOVLP 0x0
+123:                           }
+124:                           if (usermode) msg_write("\r\n"); else msg_write("\n");
+01E5  084C     MOVF 0x4C, W
+01E6  1D03     BTFSS STATUS, 0x2
+01E7  29E9     GOTO 0x1E9
+01E8  29F1     GOTO 0x1F1
+01E9  3059     MOVLW 0x59
+01EA  00F4     MOVWF i
+01EB  3086     MOVLW 0x86
+01EC  00F5     MOVWF presence
+01ED  318E     MOVLP 0xE
+01EE  2613     CALL 0x613
+01EF  3180     MOVLP 0x0
+01F0  29F9     GOTO 0x1F9
+01F1  305A     MOVLW 0x5A
+01F2  00F4     MOVWF i
+01F3  3086     MOVLW 0x86
+01F4  00F5     MOVWF presence
+01F5  318E     MOVLP 0xE
+01F6  2613     CALL 0x613
+01F7  3180     MOVLP 0x0
+01F8  29F9     GOTO 0x1F9
+125:                           count++;
+01F9  3001     MOVLW 0x1
+01FA  0020     MOVLB 0x0
+01FB  00C1     MOVWF 0x41
+01FC  0841     MOVF 0x41, W
+01FD  0021     MOVLB 0x1
+01FE  07C1     ADDWF 0x41, F
+01FF  2A00     GOTO 0x200
+126:                       }
+127:                       if (usermode) {
+0209  0021     MOVLB 0x1
+020A  084C     MOVF 0x4C, W
+020B  1D03     BTFSS STATUS, 0x2
+020C  2A0E     GOTO 0x20E
+020D  2A1C     GOTO 0x21C
+128:                           if (count==0) msg_write("ERROR No devices found\r\n");
+020E  08C1     MOVF 0x41, F
+020F  1D03     BTFSS STATUS, 0x2
+0210  2A12     GOTO 0x212
+0211  2A13     GOTO 0x213
+0212  2CDC     GOTO 0x4DC
+0213  3098     MOVLW 0x98
+0214  00F4     MOVWF i
+0215  3087     MOVLW 0x87
+0216  00F5     MOVWF presence
+0217  318E     MOVLP 0xE
+0218  2613     CALL 0x613
+0219  3180     MOVLP 0x0
+021A  2CDC     GOTO 0x4DC
+129:                       } else {
+021B  2CDC     GOTO 0x4DC
+130:                           msg_write("END\n");
+021C  30A3     MOVLW 0xA3
+021D  00F4     MOVWF i
+021E  3088     MOVLW 0x88
+021F  00F5     MOVWF presence
+0220  318E     MOVLP 0xE
+0221  2613     CALL 0x613
+0222  3180     MOVLP 0x0
+0223  2CDC     GOTO 0x4DC
+131:                       }
+132:                   }else
+0224  2CDC     GOTO 0x4DC
+133:                   if (cmd == 'i' || cmd == 'I') {
+0225  0021     MOVLB 0x1
+0226  084B     MOVF 0x4B, W
+0227  3A69     XORLW 0x69
+0228  1903     BTFSC STATUS, 0x2
+0229  2A2B     GOTO 0x22B
+022A  2A2C     GOTO 0x22C
+022B  2A33     GOTO 0x233
+022C  084B     MOVF 0x4B, W
+022D  3A49     XORLW 0x49
+022E  1D03     BTFSS STATUS, 0x2
+022F  2A31     GOTO 0x231
+0230  2A32     GOTO 0x232
+0231  2A83     GOTO 0x283
+0232  2A33     GOTO 0x233
+134:                       OW_identify();
+0233  318D     MOVLP 0xD
+0234  2592     CALL 0x592
+0235  3180     MOVLP 0x0
+135:                       char val[3];
+136:                       if (usermode) msg_write("\rID ");
+0236  0021     MOVLB 0x1
+0237  084C     MOVF 0x4C, W
+0238  1D03     BTFSS STATUS, 0x2
+0239  2A3B     GOTO 0x23B
+023A  2A43     GOTO 0x243
+023B  30AD     MOVLW 0xAD
+023C  00F4     MOVWF i
+023D  3088     MOVLW 0x88
+023E  00F5     MOVWF presence
+023F  318E     MOVLP 0xE
+0240  2613     CALL 0x613
+0241  3180     MOVLP 0x0
+0242  2A43     GOTO 0x243
+137:                       for (char j=0; j<8; j++) {
+0243  0021     MOVLB 0x1
+0244  01C7     CLRF 0x47
+0245  3008     MOVLW 0x8
+0246  0247     SUBWF 0x47, W
+0247  1C03     BTFSS STATUS, 0x0
+0248  2A4A     GOTO 0x24A
+0249  2A4B     GOTO 0x24B
+024A  2A4D     GOTO 0x24D
+024B  2A6E     GOTO 0x26E
+024C  2A6E     GOTO 0x26E
+0261  3001     MOVLW 0x1
+0262  0020     MOVLB 0x0
+0263  00C1     MOVWF 0x41
+0264  0841     MOVF 0x41, W
+0265  0021     MOVLB 0x1
+0266  07C7     ADDWF 0x47, F
+0267  3008     MOVLW 0x8
+0268  0247     SUBWF 0x47, W
+0269  1C03     BTFSS STATUS, 0x0
+026A  2A6C     GOTO 0x26C
+026B  2A6D     GOTO 0x26D
+026C  2A4D     GOTO 0x24D
+026D  2A6E     GOTO 0x26E
+138:                           tohex(val, romid[j]);
+024D  0847     MOVF 0x47, W
+024E  3E20     ADDLW 0x20
+024F  0086     MOVWF FSR1L
+0250  0187     CLRF FSR1H
+0251  0801     MOVF INDF1, W
+0252  0020     MOVLB 0x0
+0253  00C1     MOVWF 0x41
+0254  0841     MOVF 0x41, W
+0255  00F4     MOVWF i
+0256  30BB     MOVLW 0xBB
+0257  318E     MOVLP 0xE
+0258  2659     CALL 0x659
+0259  3180     MOVLP 0x0
+139:                           msg_write(val);
+025A  30BB     MOVLW 0xBB
+025B  00F4     MOVWF i
+025C  3000     MOVLW 0x0
+025D  00F5     MOVWF presence
+025E  318E     MOVLP 0xE
+025F  2613     CALL 0x613
+0260  3180     MOVLP 0x0
+140:                       }
+141:                       if (usermode) msg_write("\r\n"); else msg_write("\n");
+026E  084C     MOVF 0x4C, W
+026F  1D03     BTFSS STATUS, 0x2
+0270  2A72     GOTO 0x272
+0271  2A7A     GOTO 0x27A
+0272  3059     MOVLW 0x59
+0273  00F4     MOVWF i
+0274  3086     MOVLW 0x86
+0275  00F5     MOVWF presence
+0276  318E     MOVLP 0xE
+0277  2613     CALL 0x613
+0278  3180     MOVLP 0x0
+0279  2CDC     GOTO 0x4DC
+027A  305A     MOVLW 0x5A
+027B  00F4     MOVWF i
+027C  3086     MOVLW 0x86
+027D  00F5     MOVWF presence
+027E  318E     MOVLP 0xE
+027F  2613     CALL 0x613
+0280  3180     MOVLP 0x0
+0281  2CDC     GOTO 0x4DC
+142:                   }else
+0282  2CDC     GOTO 0x4DC
+143:                   if (cmd == 'p' || cmd == 'P') {
+0283  0021     MOVLB 0x1
+0284  084B     MOVF 0x4B, W
+0285  3A70     XORLW 0x70
+0286  1903     BTFSC STATUS, 0x2
+0287  2A89     GOTO 0x289
+0288  2A8A     GOTO 0x28A
+0289  2A91     GOTO 0x291
+028A  084B     MOVF 0x4B, W
+028B  3A50     XORLW 0x50
+028C  1D03     BTFSS STATUS, 0x2
+028D  2A8F     GOTO 0x28F
+028E  2A90     GOTO 0x290
+028F  2AD5     GOTO 0x2D5
+0290  2A91     GOTO 0x291
+144:                       if (usermode) msg_write("\r");
+0291  084C     MOVF 0x4C, W
+0292  1D03     BTFSS STATUS, 0x2
+0293  2A95     GOTO 0x295
+0294  2A9D     GOTO 0x29D
+0295  30B2     MOVLW 0xB2
+0296  00F4     MOVWF i
+0297  3088     MOVLW 0x88
+0298  00F5     MOVWF presence
+0299  318E     MOVLP 0xE
+029A  2613     CALL 0x613
+029B  3180     MOVLP 0x0
+029C  2A9D     GOTO 0x29D
+145:                       bool para = OW_parasite();
+029D  318B     MOVLP 0xB
+029E  23AE     CALL 0x3AE
+029F  3180     MOVLP 0x0
+02A0  0020     MOVLB 0x0
+02A1  00C1     MOVWF 0x41
+02A2  0841     MOVF 0x41, W
+02A3  0021     MOVLB 0x1
+02A4  00C2     MOVWF 0x42
+146:                       if (usermode) {
+02A5  084C     MOVF 0x4C, W
+02A6  1D03     BTFSS STATUS, 0x2
+02A7  2AA9     GOTO 0x2A9
+02A8  2ABE     GOTO 0x2BE
+147:                           if (para)
+02A9  0842     MOVF 0x42, W
+02AA  1D03     BTFSS STATUS, 0x2
+02AB  2AAD     GOTO 0x2AD
+02AC  2AB5     GOTO 0x2B5
+148:                               msg_write("PARA A Device is parasite powered\r\n");
+02AD  30CB     MOVLW 0xCB
+02AE  00F4     MOVWF i
+02AF  3086     MOVLW 0x86
+02B0  00F5     MOVWF presence
+02B1  318E     MOVLP 0xE
+02B2  2613     CALL 0x613
+02B3  3180     MOVLP 0x0
+02B4  2CDC     GOTO 0x4DC
+149:                           else
+150:                               msg_write("PARA No Device is parasite powered.\r\n");
+02B5  3036     MOVLW 0x36
+02B6  00F4     MOVWF i
+02B7  3086     MOVLW 0x86
+02B8  00F5     MOVWF presence
+02B9  318E     MOVLP 0xE
+02BA  2613     CALL 0x613
+02BB  3180     MOVLP 0x0
+02BC  2CDC     GOTO 0x4DC
+151:                       } else {
+02BD  2CDC     GOTO 0x4DC
+152:                           if (para) msg_write("PARA\n"); else msg_write("DIRECT\n");
+02BE  0021     MOVLB 0x1
+02BF  0842     MOVF 0x42, W
+02C0  1D03     BTFSS STATUS, 0x2
+02C1  2AC3     GOTO 0x2C3
+02C2  2ACB     GOTO 0x2CB
+02C3  3091     MOVLW 0x91
+02C4  00F4     MOVWF i
+02C5  3088     MOVLW 0x88
+02C6  00F5     MOVWF presence
+02C7  318E     MOVLP 0xE
+02C8  2613     CALL 0x613
+02C9  3180     MOVLP 0x0
+02CA  2CDC     GOTO 0x4DC
+02CB  3082     MOVLW 0x82
+02CC  00F4     MOVWF i
+02CD  3088     MOVLW 0x88
+02CE  00F5     MOVWF presence
+02CF  318E     MOVLP 0xE
+02D0  2613     CALL 0x613
+02D1  3180     MOVLP 0x0
+02D2  2CDC     GOTO 0x4DC
+02D3  2CDC     GOTO 0x4DC
+153:                       }
+154:                   }else
+02D4  2CDC     GOTO 0x4DC
+155:                   if (cmd == 's' || cmd =='S') {
+02D5  0021     MOVLB 0x1
+02D6  084B     MOVF 0x4B, W
+02D7  3A73     XORLW 0x73
+02D8  1903     BTFSC STATUS, 0x2
+02D9  2ADB     GOTO 0x2DB
+02DA  2ADC     GOTO 0x2DC
+02DB  2AE2     GOTO 0x2E2
+02DC  084B     MOVF 0x4B, W
+02DD  3A53     XORLW 0x53
+02DE  1D03     BTFSS STATUS, 0x2
+02DF  2AE1     GOTO 0x2E1
+02E0  2AE2     GOTO 0x2E2
+02E1  2B44     GOTO 0x344
+156:                       uint8_t scratch[9];
+157:                       romid[0] = 0; // select all devices
+02E2  0020     MOVLB 0x0
+02E3  01A0     CLRF romid
+158:                       OW_read_block(0xBE, scratch, 9);
+02E4  30A0     MOVLW 0xA0
+02E5  00C1     MOVWF 0x41
+02E6  0841     MOVF 0x41, W
+02E7  00BA     MOVWF search_result
+02E8  3009     MOVLW 0x9
+02E9  00C2     MOVWF 0x42
+02EA  0842     MOVF 0x42, W
+02EB  00BB     MOVWF id_bit
+02EC  30BE     MOVLW 0xBE
+02ED  318D     MOVLP 0xD
+02EE  251A     CALL 0x51A
+02EF  3180     MOVLP 0x0
+159:                       if (usermode) msg_write("\rSCRATCH");
+02F0  0021     MOVLB 0x1
+02F1  084C     MOVF 0x4C, W
+02F2  1D03     BTFSS STATUS, 0x2
+02F3  2AF5     GOTO 0x2F5
+02F4  2AFD     GOTO 0x2FD
+02F5  3079     MOVLW 0x79
+02F6  00F4     MOVWF i
+02F7  3088     MOVLW 0x88
+02F8  00F5     MOVWF presence
+02F9  318E     MOVLP 0xE
+02FA  2613     CALL 0x613
+02FB  3180     MOVLP 0x0
+02FC  2AFD     GOTO 0x2FD
+160:                       for (char j=0; j<9; j++) {
+02FD  0021     MOVLB 0x1
+02FE  01C8     CLRF 0x48
+02FF  3009     MOVLW 0x9
+0300  0248     SUBWF 0x48, W
+0301  1C03     BTFSS STATUS, 0x0
+0302  2B04     GOTO 0x304
+0303  2B05     GOTO 0x305
+0304  2B07     GOTO 0x307
+0305  2B2F     GOTO 0x32F
+0306  2B2F     GOTO 0x32F
+0322  3001     MOVLW 0x1
+0323  0020     MOVLB 0x0
+0324  00C1     MOVWF 0x41
+0325  0841     MOVF 0x41, W
+0326  0021     MOVLB 0x1
+0327  07C8     ADDWF 0x48, F
+0328  3009     MOVLW 0x9
+0329  0248     SUBWF 0x48, W
+032A  1C03     BTFSS STATUS, 0x0
+032B  2B2D     GOTO 0x32D
+032C  2B2E     GOTO 0x32E
+032D  2B07     GOTO 0x307
+032E  2B2F     GOTO 0x32F
+161:                           char val[3];
+162:                           tohex(val, scratch[j]);
+0307  0848     MOVF 0x48, W
+0308  3EA0     ADDLW 0xA0
+0309  0086     MOVWF FSR1L
+030A  0187     CLRF FSR1H
+030B  0801     MOVF INDF1, W
+030C  0020     MOVLB 0x0
+030D  00C1     MOVWF 0x41
+030E  0841     MOVF 0x41, W
+030F  00F4     MOVWF i
+0310  30BE     MOVLW 0xBE
+0311  318E     MOVLP 0xE
+0312  2659     CALL 0x659
+0313  3180     MOVLP 0x0
+163:                           msg_write(" ");
+0314  30B0     MOVLW 0xB0
+0315  00F4     MOVWF i
+0316  3088     MOVLW 0x88
+0317  00F5     MOVWF presence
+0318  318E     MOVLP 0xE
+0319  2613     CALL 0x613
+031A  3180     MOVLP 0x0
+164:                           msg_write(val);
+031B  30BE     MOVLW 0xBE
+031C  00F4     MOVWF i
+031D  3000     MOVLW 0x0
+031E  00F5     MOVWF presence
+031F  318E     MOVLP 0xE
+0320  2613     CALL 0x613
+0321  3180     MOVLP 0x0
+165:                       }
+166:                       if (usermode) msg_write("\r\n"); else msg_write("\n");
+032F  084C     MOVF 0x4C, W
+0330  1D03     BTFSS STATUS, 0x2
+0331  2B33     GOTO 0x333
+0332  2B3B     GOTO 0x33B
+0333  3059     MOVLW 0x59
+0334  00F4     MOVWF i
+0335  3086     MOVLW 0x86
+0336  00F5     MOVWF presence
+0337  318E     MOVLP 0xE
+0338  2613     CALL 0x613
+0339  3180     MOVLP 0x0
+033A  2CDC     GOTO 0x4DC
+033B  305A     MOVLW 0x5A
+033C  00F4     MOVWF i
+033D  3086     MOVLW 0x86
+033E  00F5     MOVWF presence
+033F  318E     MOVLP 0xE
+0340  2613     CALL 0x613
+0341  3180     MOVLP 0x0
+0342  2CDC     GOTO 0x4DC
+167:                   }else
+0343  2CDC     GOTO 0x4DC
+168:                   if (cmd == 't' || cmd == 'T') {
+0344  0021     MOVLB 0x1
+0345  084B     MOVF 0x4B, W
+0346  3A74     XORLW 0x74
+0347  1903     BTFSC STATUS, 0x2
+0348  2B4A     GOTO 0x34A
+0349  2B4B     GOTO 0x34B
+034A  2B52     GOTO 0x352
+034B  084B     MOVF 0x4B, W
+034C  3A54     XORLW 0x54
+034D  1D03     BTFSS STATUS, 0x2
+034E  2B50     GOTO 0x350
+034F  2B51     GOTO 0x351
+0350  2C10     GOTO 0x410
+0351  2B52     GOTO 0x352
+169:                       char val[3];
+170:                       uint8_t scratch[9];
+171:           
+172:                       // oddly, cant do a mass-convert with parasitic
+173:                       // they seem to all reset when you try
+174:                       
+175:                       // now step through every unit and read the value
+176:                       OW_search_init();
+0352  318C     MOVLP 0xC
+0353  248C     CALL 0x48C
+0354  3180     MOVLP 0x0
+177:                       while (OW_search())
+0355  2BF8     GOTO 0x3F8
+03F8  318F     MOVLP 0xF
+03F9  270C     CALL 0x70C
+03FA  3180     MOVLP 0x0
+03FB  3800     IORLW 0x0
+03FC  1D03     BTFSS STATUS, 0x2
+03FD  2BFF     GOTO 0x3FF
+03FE  2C00     GOTO 0x400
+03FF  2B56     GOTO 0x356
+0400  2C01     GOTO 0x401
+178:                       {
+179:                           // ask device to do conversion
+180:                           OW_convert();
+0356  318E     MOVLP 0xE
+0357  26A0     CALL 0x6A0
+0358  3180     MOVLP 0x0
+181:           
+182:                           // empty the scratch pad
+183:                           for (char j=0; j<9; j++) scratch[j]=0;
+0359  0021     MOVLB 0x1
+035A  01C9     CLRF 0x49
+035B  3009     MOVLW 0x9
+035C  0249     SUBWF 0x49, W
+035D  1C03     BTFSS STATUS, 0x0
+035E  2B60     GOTO 0x360
+035F  2B61     GOTO 0x361
+0360  2B63     GOTO 0x363
+0361  2B75     GOTO 0x375
+0362  2B75     GOTO 0x375
+0363  0849     MOVF 0x49, W
+0364  3EA9     ADDLW 0xA9
+0365  0086     MOVWF FSR1L
+0366  0187     CLRF FSR1H
+0367  0181     CLRF INDF1
+0368  3001     MOVLW 0x1
+0369  0020     MOVLB 0x0
+036A  00C1     MOVWF 0x41
+036B  0841     MOVF 0x41, W
+036C  0021     MOVLB 0x1
+036D  07C9     ADDWF 0x49, F
+036E  3009     MOVLW 0x9
+036F  0249     SUBWF 0x49, W
+0370  1C03     BTFSS STATUS, 0x0
+0371  2B73     GOTO 0x373
+0372  2B74     GOTO 0x374
+0373  2B63     GOTO 0x363
+0374  2B75     GOTO 0x375
+184:           
+185:                           // read this devices scratch pad
+186:                           OW_read_block(0xBE, scratch, 9);
+0375  30A9     MOVLW 0xA9
+0376  0020     MOVLB 0x0
+0377  00C1     MOVWF 0x41
+0378  0841     MOVF 0x41, W
+0379  00BA     MOVWF search_result
+037A  3009     MOVLW 0x9
+037B  00C2     MOVWF 0x42
+037C  0842     MOVF 0x42, W
+037D  00BB     MOVWF id_bit
+037E  30BE     MOVLW 0xBE
+037F  318D     MOVLP 0xD
+0380  251A     CALL 0x51A
+0381  3180     MOVLP 0x0
+187:           
+188:                           // print rom id and temperature
+189:                           if (usermode) msg_write("\rTEMP ");
+0382  0021     MOVLB 0x1
+0383  084C     MOVF 0x4C, W
+0384  1D03     BTFSS STATUS, 0x2
+0385  2B87     GOTO 0x387
+0386  2B8F     GOTO 0x38F
+0387  308A     MOVLW 0x8A
+0388  00F4     MOVWF i
+0389  3088     MOVLW 0x88
+038A  00F5     MOVWF presence
+038B  318E     MOVLP 0xE
+038C  2613     CALL 0x613
+038D  3180     MOVLP 0x0
+038E  2B8F     GOTO 0x38F
+190:                           for (char j=0;j<8;j++) {
+038F  0021     MOVLB 0x1
+0390  01CA     CLRF 0x4A
+0391  3008     MOVLW 0x8
+0392  024A     SUBWF 0x4A, W
+0393  1C03     BTFSS STATUS, 0x0
+0394  2B96     GOTO 0x396
+0395  2B97     GOTO 0x397
+0396  2B99     GOTO 0x399
+0397  2BBA     GOTO 0x3BA
+0398  2BBA     GOTO 0x3BA
+03AD  3001     MOVLW 0x1
+03AE  0020     MOVLB 0x0
+03AF  00C1     MOVWF 0x41
+03B0  0841     MOVF 0x41, W
+03B1  0021     MOVLB 0x1
+03B2  07CA     ADDWF 0x4A, F
+03B3  3008     MOVLW 0x8
+03B4  024A     SUBWF 0x4A, W
+03B5  1C03     BTFSS STATUS, 0x0
+03B6  2BB8     GOTO 0x3B8
+03B7  2BB9     GOTO 0x3B9
+03B8  2B99     GOTO 0x399
+03B9  2BBA     GOTO 0x3BA
+191:                               tohex(val, romid[j]);
+0399  084A     MOVF 0x4A, W
+039A  3E20     ADDLW 0x20
+039B  0086     MOVWF FSR1L
+039C  0187     CLRF FSR1H
+039D  0801     MOVF INDF1, W
+039E  0020     MOVLB 0x0
+039F  00C1     MOVWF 0x41
+03A0  0841     MOVF 0x41, W
+03A1  00F4     MOVWF i
+03A2  30C3     MOVLW 0xC3
+03A3  318E     MOVLP 0xE
+03A4  2659     CALL 0x659
+03A5  3180     MOVLP 0x0
+192:                               msg_write(val);
+03A6  30C3     MOVLW 0xC3
+03A7  00F4     MOVWF i
+03A8  3000     MOVLW 0x0
+03A9  00F5     MOVWF presence
+03AA  318E     MOVLP 0xE
+03AB  2613     CALL 0x613
+03AC  3180     MOVLP 0x0
+193:                           }
+194:                           msg_write(" ");
+03BA  30B0     MOVLW 0xB0
+03BB  00F4     MOVWF i
+03BC  3088     MOVLW 0x88
+03BD  00F5     MOVWF presence
+03BE  318E     MOVLP 0xE
+03BF  2613     CALL 0x613
+03C0  3180     MOVLP 0x0
+195:                           tohex(val, scratch[1]);
+03C1  0021     MOVLB 0x1
+03C2  082A     MOVF LastFamilyDiscrepancy, W
+03C3  0020     MOVLB 0x0
+03C4  00C1     MOVWF 0x41
+03C5  0841     MOVF 0x41, W
+03C6  00F4     MOVWF i
+03C7  30C3     MOVLW 0xC3
+03C8  318E     MOVLP 0xE
+03C9  2659     CALL 0x659
+03CA  3180     MOVLP 0x0
+196:                           msg_write(val);
+03CB  30C3     MOVLW 0xC3
+03CC  00F4     MOVWF i
+03CD  3000     MOVLW 0x0
+03CE  00F5     MOVWF presence
+03CF  318E     MOVLP 0xE
+03D0  2613     CALL 0x613
+03D1  3180     MOVLP 0x0
+197:                           tohex(val, scratch[0]);
+03D2  0021     MOVLB 0x1
+03D3  0829     MOVF LastDiscrepancy, W
+03D4  0020     MOVLB 0x0
+03D5  00C1     MOVWF 0x41
+03D6  0841     MOVF 0x41, W
+03D7  00F4     MOVWF i
+03D8  30C3     MOVLW 0xC3
+03D9  318E     MOVLP 0xE
+03DA  2659     CALL 0x659
+03DB  3180     MOVLP 0x0
+198:                           msg_write(val);
+03DC  30C3     MOVLW 0xC3
+03DD  00F4     MOVWF i
+03DE  3000     MOVLW 0x0
+03DF  00F5     MOVWF presence
+03E0  318E     MOVLP 0xE
+03E1  2613     CALL 0x613
+03E2  3180     MOVLP 0x0
+199:                           if (usermode) msg_write("\r\n"); else msg_write("\n");
+03E3  0021     MOVLB 0x1
+03E4  084C     MOVF 0x4C, W
+03E5  1D03     BTFSS STATUS, 0x2
+03E6  2BE8     GOTO 0x3E8
+03E7  2BF0     GOTO 0x3F0
+03E8  3059     MOVLW 0x59
+03E9  00F4     MOVWF i
+03EA  3086     MOVLW 0x86
+03EB  00F5     MOVWF presence
+03EC  318E     MOVLP 0xE
+03ED  2613     CALL 0x613
+03EE  3180     MOVLP 0x0
+03EF  2BF8     GOTO 0x3F8
+03F0  305A     MOVLW 0x5A
+03F1  00F4     MOVWF i
+03F2  3086     MOVLW 0x86
+03F3  00F5     MOVWF presence
+03F4  318E     MOVLP 0xE
+03F5  2613     CALL 0x613
+03F6  3180     MOVLP 0x0
+03F7  2BF8     GOTO 0x3F8
+200:                       }
+201:           
+202:                       if (!usermode) msg_write("END\n");
+0401  0021     MOVLB 0x1
+0402  08CC     MOVF 0x4C, F
+0403  1D03     BTFSS STATUS, 0x2
+0404  2C06     GOTO 0x406
+0405  2C07     GOTO 0x407
+0406  2CDC     GOTO 0x4DC
+0407  30A3     MOVLW 0xA3
+0408  00F4     MOVWF i
+0409  3088     MOVLW 0x88
+040A  00F5     MOVWF presence
+040B  318E     MOVLP 0xE
+040C  2613     CALL 0x613
+040D  3180     MOVLP 0x0
+040E  2CDC     GOTO 0x4DC
+203:           
+204:                   }else
+040F  2CDC     GOTO 0x4DC
+205:                   if (cmd == '0')
+0410  0021     MOVLB 0x1
+0411  084B     MOVF 0x4B, W
+0412  3A30     XORLW 0x30
+0413  1D03     BTFSS STATUS, 0x2
+0414  2C16     GOTO 0x416
+0415  2C17     GOTO 0x417
+0416  2C30     GOTO 0x430
+206:                   {
+207:                       drive_OW_low();
+0417  318B     MOVLP 0xB
+0418  232D     CALL 0x32D
+0419  3180     MOVLP 0x0
+208:                       if (usermode)
+041A  0021     MOVLB 0x1
+041B  084C     MOVF 0x4C, W
+041C  1D03     BTFSS STATUS, 0x2
+041D  2C1F     GOTO 0x41F
+041E  2C27     GOTO 0x427
+209:                           msg_write("\rBUS 1-Wire set low\r\n");
+041F  3029     MOVLW 0x29
+0420  00F4     MOVWF i
+0421  3088     MOVLW 0x88
+0422  00F5     MOVWF presence
+0423  318E     MOVLP 0xE
+0424  2613     CALL 0x613
+0425  3180     MOVLP 0x0
+0426  2CDC     GOTO 0x4DC
+210:                       else
+211:                           msg_write("LOW\n");
+0427  30A8     MOVLW 0xA8
+0428  00F4     MOVWF i
+0429  3088     MOVLW 0x88
+042A  00F5     MOVWF presence
+042B  318E     MOVLP 0xE
+042C  2613     CALL 0x613
+042D  3180     MOVLP 0x0
+042E  2CDC     GOTO 0x4DC
+212:                   }else
+042F  2CDC     GOTO 0x4DC
+213:                   if (cmd == '1')
+0430  0021     MOVLB 0x1
+0431  084B     MOVF 0x4B, W
+0432  3A31     XORLW 0x31
+0433  1D03     BTFSS STATUS, 0x2
+0434  2C36     GOTO 0x436
+0435  2C37     GOTO 0x437
+0436  2C50     GOTO 0x450
+214:                   {
+215:                       drive_OW_high();
+0437  318B     MOVLP 0xB
+0438  2328     CALL 0x328
+0439  3180     MOVLP 0x0
+216:                       if (usermode) 
+043A  0021     MOVLB 0x1
+043B  084C     MOVF 0x4C, W
+043C  1D03     BTFSS STATUS, 0x2
+043D  2C3F     GOTO 0x43F
+043E  2C47     GOTO 0x447
+217:                           msg_write("\rBUS 1-wire set high\r\n");
+043F  3012     MOVLW 0x12
+0440  00F4     MOVWF i
+0441  3088     MOVLW 0x88
+0442  00F5     MOVWF presence
+0443  318E     MOVLP 0xE
+0444  2613     CALL 0x613
+0445  3180     MOVLP 0x0
+0446  2CDC     GOTO 0x4DC
+218:                       else
+219:                           msg_write("HIGH\n");
+0447  3097     MOVLW 0x97
+0448  00F4     MOVWF i
+0449  3088     MOVLW 0x88
+044A  00F5     MOVWF presence
+044B  318E     MOVLP 0xE
+044C  2613     CALL 0x613
+044D  3180     MOVLP 0x0
+044E  2CDC     GOTO 0x4DC
+220:                   }else
+044F  2CDC     GOTO 0x4DC
+221:                   if (cmd == '3')
+0450  0021     MOVLB 0x1
+0451  084B     MOVF 0x4B, W
+0452  3A33     XORLW 0x33
+0453  1D03     BTFSS STATUS, 0x2
+0454  2C56     GOTO 0x456
+0455  2C57     GOTO 0x457
+0456  2C70     GOTO 0x470
+222:                   {
+223:                       float_OW();
+0457  3184     MOVLP 0x4
+0458  24FD     CALL 0x4FD
+0459  3180     MOVLP 0x0
+224:                       if (usermode)
+045A  0021     MOVLB 0x1
+045B  084C     MOVF 0x4C, W
+045C  1D03     BTFSS STATUS, 0x2
+045D  2C5F     GOTO 0x45F
+045E  2C67     GOTO 0x467
+225:                           msg_write("\rBUS 1-wire set to tri-state\r\n");
+045F  30EF     MOVLW 0xEF
+0460  00F4     MOVWF i
+0461  3086     MOVLW 0x86
+0462  00F5     MOVWF presence
+0463  318E     MOVLP 0xE
+0464  2613     CALL 0x613
+0465  3180     MOVLP 0x0
+0466  2CDC     GOTO 0x4DC
+226:                       else
+227:                           msg_write("TRISTATE\n");
+0467  3066     MOVLW 0x66
+0468  00F4     MOVWF i
+0469  3088     MOVLW 0x88
+046A  00F5     MOVWF presence
+046B  318E     MOVLP 0xE
+046C  2613     CALL 0x613
+046D  3180     MOVLP 0x0
+046E  2CDC     GOTO 0x4DC
+228:                   }else
+046F  2CDC     GOTO 0x4DC
+229:                   if (cmd == '?')
+0470  0021     MOVLB 0x1
+0471  084B     MOVF 0x4B, W
+0472  3A3F     XORLW 0x3F
+0473  1D03     BTFSS STATUS, 0x2
+0474  2C76     GOTO 0x476
+0475  2C77     GOTO 0x477
+0476  2CAF     GOTO 0x4AF
+230:                   {
+231:                       bool line = read_OW();
+0477  318B     MOVLP 0xB
+0478  2332     CALL 0x332
+0479  3180     MOVLP 0x0
+047A  0020     MOVLB 0x0
+047B  00C1     MOVWF 0x41
+047C  0841     MOVF 0x41, W
+047D  0021     MOVLB 0x1
+047E  00B3     MOVWF 0x33
+232:                       if (line) {
+047F  0833     MOVF 0x33, W
+0480  1D03     BTFSS STATUS, 0x2
+0481  2C83     GOTO 0x483
+0482  2C98     GOTO 0x498
+233:                           if (usermode) msg_write("\rBUS HIGH\r\n");
+0483  084C     MOVF 0x4C, W
+0484  1D03     BTFSS STATUS, 0x2
+0485  2C87     GOTO 0x487
+0486  2C8F     GOTO 0x48F
+0487  304F     MOVLW 0x4F
+0488  00F4     MOVWF i
+0489  3088     MOVLW 0x88
+048A  00F5     MOVWF presence
+048B  318E     MOVLP 0xE
+048C  2613     CALL 0x613
+048D  3180     MOVLP 0x0
+048E  2CDC     GOTO 0x4DC
+234:                           else
+235:                               msg_write("HIGH\n");
+048F  3097     MOVLW 0x97
+0490  00F4     MOVWF i
+0491  3088     MOVLW 0x88
+0492  00F5     MOVWF presence
+0493  318E     MOVLP 0xE
+0494  2613     CALL 0x613
+0495  3180     MOVLP 0x0
+0496  2CDC     GOTO 0x4DC
+236:                       } else {
+0497  2CDC     GOTO 0x4DC
+237:                           if (usermode) msg_write("\rBUS LOW\r\n");
+0498  0021     MOVLB 0x1
+0499  084C     MOVF 0x4C, W
+049A  1D03     BTFSS STATUS, 0x2
+049B  2C9D     GOTO 0x49D
+049C  2CA5     GOTO 0x4A5
+049D  305B     MOVLW 0x5B
+049E  00F4     MOVWF i
+049F  3088     MOVLW 0x88
+04A0  00F5     MOVWF presence
+04A1  318E     MOVLP 0xE
+04A2  2613     CALL 0x613
+04A3  3180     MOVLP 0x0
+04A4  2CDC     GOTO 0x4DC
+238:                           else msg_write("LOW\n");
+04A5  30A8     MOVLW 0xA8
+04A6  00F4     MOVWF i
+04A7  3088     MOVLW 0x88
+04A8  00F5     MOVWF presence
+04A9  318E     MOVLP 0xE
+04AA  2613     CALL 0x613
+04AB  3180     MOVLP 0x0
+04AC  2CDC     GOTO 0x4DC
+04AD  2CDC     GOTO 0x4DC
+239:                       }
+240:                   }else
+04AE  2CDC     GOTO 0x4DC
+241:                   {
+242:                       if (usermode) {
+04AF  0021     MOVLB 0x1
+04B0  084C     MOVF 0x4C, W
+04B1  1D03     BTFSS STATUS, 0x2
+04B2  2CB4     GOTO 0x4B4
+04B3  2CBC     GOTO 0x4BC
+243:                           msg_write("ERROR Press H for Help\n");
+04B4  30FA     MOVLW 0xFA
+04B5  00F4     MOVWF i
+04B6  3087     MOVLW 0x87
+04B7  00F5     MOVWF presence
+04B8  318E     MOVLP 0xE
+04B9  2613     CALL 0x613
+04BA  3180     MOVLP 0x0
+244:                       } else {
+04BB  2CDC     GOTO 0x4DC
+245:                           msg_write("\rERROR Unknown command '");
+04BC  30B1     MOVLW 0xB1
+04BD  00F4     MOVWF i
+04BE  3087     MOVLW 0x87
+04BF  00F5     MOVWF presence
+04C0  318E     MOVLP 0xE
+04C1  2613     CALL 0x613
+04C2  3180     MOVLP 0x0
+246:                           msg_writebyte(cmd);
+04C3  0021     MOVLB 0x1
+04C4  084B     MOVF 0x4B, W
+04C5  318D     MOVLP 0xD
+04C6  25CF     CALL 0x5CF
+04C7  3180     MOVLP 0x0
+247:                           msg_write("' Press 'H' for help.\r\n");
+04C8  30CA     MOVLW 0xCA
+04C9  00F4     MOVWF i
+04CA  3087     MOVLW 0x87
+04CB  00F5     MOVWF presence
+04CC  318E     MOVLP 0xE
+04CD  2613     CALL 0x613
+04CE  3180     MOVLP 0x0
+04CF  2CDC     GOTO 0x4DC
+248:                       }
+04D0  2CDC     GOTO 0x4DC
+249:                   }
+04D1  2CDC     GOTO 0x4DC
+04D2  2CDC     GOTO 0x4DC
+04D3  2CDC     GOTO 0x4DC
+04D4  2CDC     GOTO 0x4DC
+04D5  2CDC     GOTO 0x4DC
+04D6  2CDC     GOTO 0x4DC
+04D7  2CDC     GOTO 0x4DC
+04D8  2CDC     GOTO 0x4DC
+04D9  2CDC     GOTO 0x4DC
+04DA  2CDC     GOTO 0x4DC
+04DB  2CDC     GOTO 0x4DC
+250:           
+251:                   if (usermode) msg_write(prompt);
+04DC  0021     MOVLB 0x1
+04DD  084C     MOVF 0x4C, W
+04DE  1D03     BTFSS STATUS, 0x2
+04DF  2CE1     GOTO 0x4E1
+04E0  2862     GOTO 0x62
+04E1  302C     MOVLW 0x2C
+04E2  00F4     MOVWF i
+04E3  3000     MOVLW 0x0
+04E4  00F5     MOVWF presence
+04E5  318E     MOVLP 0xE
+04E6  2613     CALL 0x613
+04E7  3180     MOVLP 0x0
+04E8  2862     GOTO 0x62
+04E9  2862     GOTO 0x62
+252:               }
+253:           }
+04EB  3180     MOVLP 0x0
+254:           
+255:           /* make a hex string from a value
+256:            * expect 3 char array */
+257:           void tohex(char val[], char i)
+258:           {
+0E59  0020     MOVLB 0x0
+0E5A  00B7     MOVWF i
+259:               char bt = i >> 4;
+0E5B  0874     MOVF i, W
+0E5C  00B5     MOVWF in
+0E5D  3004     MOVLW 0x4
+0E5E  36B5     LSRF in, F
+0E5F  0B89     DECFSZ WREG, F
+0E60  2E5E     GOTO 0x65E
+0E61  0835     MOVF in, W
+0E62  00B6     MOVWF p
+0E63  0836     MOVF p, W
+0E64  00B8     MOVWF bt
+260:               if (bt > 9)
+0E65  300A     MOVLW 0xA
+0E66  0238     SUBWF bt, W
+0E67  1C03     BTFSS STATUS, 0x0
+0E68  2E6A     GOTO 0x66A
+0E69  2E6B     GOTO 0x66B
+0E6A  2E74     GOTO 0x674
+261:                   val[0] = 'A' + (bt - 10);
+0E6B  0838     MOVF bt, W
+0E6C  3E37     ADDLW 0x37
+0E6D  00B5     MOVWF in
+0E6E  0837     MOVF i, W
+0E6F  0086     MOVWF FSR1L
+0E70  0187     CLRF FSR1H
+0E71  0835     MOVF in, W
+0E72  0081     MOVWF INDF1
+0E73  2E7D     GOTO 0x67D
+262:               else
+263:                   val[0] = '0' + bt;
+0E74  0838     MOVF bt, W
+0E75  3E30     ADDLW 0x30
+0E76  00B5     MOVWF in
+0E77  0837     MOVF i, W
+0E78  0086     MOVWF FSR1L
+0E79  0187     CLRF FSR1H
+0E7A  0835     MOVF in, W
+0E7B  0081     MOVWF INDF1
+0E7C  2E7D     GOTO 0x67D
+264:               bt = i & 0x0F;
+0E7D  0874     MOVF i, W
+0E7E  390F     ANDLW 0xF
+0E7F  00B5     MOVWF in
+0E80  0835     MOVF in, W
+0E81  00B8     MOVWF bt
+265:               if (bt > 9)
+0E82  300A     MOVLW 0xA
+0E83  0238     SUBWF bt, W
+0E84  1C03     BTFSS STATUS, 0x0
+0E85  2E87     GOTO 0x687
+0E86  2E88     GOTO 0x688
+0E87  2E91     GOTO 0x691
+266:                   val[1] = 'A' + (bt - 10);
+0E88  0838     MOVF bt, W
+0E89  3E37     ADDLW 0x37
+0E8A  00B5     MOVWF in
+0E8B  0A37     INCF i, W
+0E8C  0086     MOVWF FSR1L
+0E8D  0187     CLRF FSR1H
+0E8E  0835     MOVF in, W
+0E8F  0081     MOVWF INDF1
+0E90  2E9A     GOTO 0x69A
+267:               else
+268:                   val[1] = '0' + bt;
+0E91  0838     MOVF bt, W
+0E92  3E30     ADDLW 0x30
+0E93  00B5     MOVWF in
+0E94  0A37     INCF i, W
+0E95  0086     MOVWF FSR1L
+0E96  0187     CLRF FSR1H
+0E97  0835     MOVF in, W
+0E98  0081     MOVWF INDF1
+0E99  2E9A     GOTO 0x69A
+269:               val[2] = 0;
+0E9A  0837     MOVF i, W
+0E9B  3E02     ADDLW 0x2
+0E9C  0086     MOVWF FSR1L
+0E9D  0187     CLRF FSR1H
+0E9E  0181     CLRF INDF1
+270:           }
+0E9F  0008     RETURN
+271:           
+272:           
+273:           /* is the queue empty yet */
+274:           bool msg_empty(void)
+275:           {
+276:               if (outp == 0) return 1;
+0B44  0877     MOVF 0x77, W
+0B45  0476     IORWF outp, W
+0B46  1D03     BTFSS STATUS, 0x2
+0B47  2B49     GOTO 0x349
+0B48  2B4A     GOTO 0x34A
+0B49  2B4D     GOTO 0x34D
+0B4A  3001     MOVLW 0x1
+0B4B  2B4F     GOTO 0x34F
+0B4C  2B4F     GOTO 0x34F
+277:               return 0;
+0B4D  3000     MOVLW 0x0
+0B4E  2B4F     GOTO 0x34F
+278:           }
+0B4F  0008     RETURN
+279:           
+280:           /* new message in the queue */
+281:           void msg_write(const char *msg)
+282:           {
+283:               char * p = outbuff + outlen;
+0E13  0879     MOVF outlen, W
+0E14  3E8C     ADDLW 0x8C
+0E15  0020     MOVLB 0x0
+0E16  00B6     MOVWF p
+0E17  01B7     CLRF i
+0E18  3020     MOVLW 0x20
+0E19  3DB7     ADDWFC i, F
+284:               while (outlen < sizeof(outbuff) && *msg != 0) {
+0E1A  2E34     GOTO 0x634
+0E34  3064     MOVLW 0x64
+0E35  0279     SUBWF outlen, W
+0E36  1803     BTFSC STATUS, 0x0
+0E37  2E39     GOTO 0x639
+0E38  2E3A     GOTO 0x63A
+0E39  2E46     GOTO 0x646
+0E3A  0874     MOVF i, W
+0E3B  0084     MOVWF FSR0L
+0E3C  0875     MOVF presence, W
+0E3D  0085     MOVWF FSR0H
+0E3E  0800     MOVF INDF0, W
+0E3F  3800     IORLW 0x0
+0E40  1D03     BTFSS STATUS, 0x2
+0E41  2E43     GOTO 0x643
+0E42  2E44     GOTO 0x644
+0E43  2E1B     GOTO 0x61B
+0E44  2E46     GOTO 0x646
+0E45  2E46     GOTO 0x646
+285:                   *(p++) = *(msg++);
+0E1B  0874     MOVF i, W
+0E1C  0084     MOVWF FSR0L
+0E1D  0875     MOVF presence, W
+0E1E  0085     MOVWF FSR0H
+0E1F  0800     MOVF INDF0, W
+0E20  00B5     MOVWF in
+0E21  0836     MOVF p, W
+0E22  0086     MOVWF FSR1L
+0E23  0837     MOVF i, W
+0E24  0087     MOVWF FSR1H
+0E25  0835     MOVF in, W
+0E26  0081     MOVWF INDF1
+0E27  3001     MOVLW 0x1
+0E28  07F4     ADDWF i, F
+0E29  3000     MOVLW 0x0
+0E2A  3DF5     ADDWFC presence, F
+0E2B  3001     MOVLW 0x1
+0E2C  07B6     ADDWF p, F
+0E2D  3000     MOVLW 0x0
+0E2E  3DB7     ADDWFC i, F
+286:                   outlen++;
+0E2F  3001     MOVLW 0x1
+0E30  00B5     MOVWF in
+0E31  0835     MOVF in, W
+0E32  07F9     ADDWF outlen, F
+0E33  2E34     GOTO 0x634
+287:               }
+288:               *p = 0;
+0E46  0836     MOVF p, W
+0E47  0086     MOVWF FSR1L
+0E48  0837     MOVF i, W
+0E49  0087     MOVWF FSR1H
+0E4A  0181     CLRF INDF1
+289:               if (outp == 0) {
+0E4B  0877     MOVF 0x77, W
+0E4C  0476     IORWF outp, W
+0E4D  1D03     BTFSS STATUS, 0x2
+0E4E  2E50     GOTO 0x650
+0E4F  2E51     GOTO 0x651
+0E50  2E58     GOTO 0x658
+290:                   outp = outbuff;
+0E51  308C     MOVLW 0x8C
+0E52  00F6     MOVWF outp
+0E53  3020     MOVLW 0x20
+0E54  00F7     MOVWF 0x77
+291:                   PIE1bits.TXIE = 1;
+0E55  0021     MOVLB 0x1
+0E56  1611     BSF PIR1, 0x4
+0E57  2E58     GOTO 0x658
+292:               }
+293:           }
+0E58  0008     RETURN
+294:           
+295:           void msg_writebyte(const char msg)
+296:           {
+0DCF  00F4     MOVWF i
+297:               if (outlen+1 >= (uint8_t)sizeof(outbuff)) return;
+0DD0  0879     MOVF outlen, W
+0DD1  3E01     ADDLW 0x1
+0DD2  0020     MOVLB 0x0
+0DD3  00B5     MOVWF in
+0DD4  3000     MOVLW 0x0
+0DD5  1803     BTFSC STATUS, 0x0
+0DD6  3001     MOVLW 0x1
+0DD7  00B6     MOVWF p
+0DD8  0836     MOVF p, W
+0DD9  3A80     XORLW 0x80
+0DDA  00FF     MOVWF 0x7F
+0DDB  3080     MOVLW 0x80
+0DDC  027F     SUBWF 0x7F, W
+0DDD  1D03     BTFSS STATUS, 0x2
+0DDE  2DE1     GOTO 0x5E1
+0DDF  3064     MOVLW 0x64
+0DE0  0235     SUBWF in, W
+0DE1  1C03     BTFSS STATUS, 0x0
+0DE2  2DE4     GOTO 0x5E4
+0DE3  2DE5     GOTO 0x5E5
+0DE4  2DE7     GOTO 0x5E7
+0DE5  2E12     GOTO 0x612
+0DE6  2E12     GOTO 0x612
+298:               outbuff[outlen++] = msg;
+0DE7  0874     MOVF i, W
+0DE8  0020     MOVLB 0x0
+0DE9  00B5     MOVWF in
+0DEA  0879     MOVF outlen, W
+0DEB  3E8C     ADDLW 0x8C
+0DEC  00B6     MOVWF p
+0DED  01B7     CLRF i
+0DEE  3020     MOVLW 0x20
+0DEF  3DB7     ADDWFC i, F
+0DF0  0836     MOVF p, W
+0DF1  0086     MOVWF FSR1L
+0DF2  0837     MOVF i, W
+0DF3  0087     MOVWF FSR1H
+0DF4  0835     MOVF in, W
+0DF5  0081     MOVWF INDF1
+0DF6  3001     MOVLW 0x1
+0DF7  00B5     MOVWF in
+0DF8  0835     MOVF in, W
+0DF9  07F9     ADDWF outlen, F
+299:               outbuff[outlen] = 0;
+0DFA  0879     MOVF outlen, W
+0DFB  3E8C     ADDLW 0x8C
+0DFC  00B5     MOVWF in
+0DFD  01B6     CLRF p
+0DFE  3020     MOVLW 0x20
+0DFF  3DB6     ADDWFC p, F
+0E00  0835     MOVF in, W
+0E01  0086     MOVWF FSR1L
+0E02  0836     MOVF p, W
+0E03  0087     MOVWF FSR1H
+0E04  0181     CLRF INDF1
+300:               if (outp == 0) {
+0E05  0877     MOVF 0x77, W
+0E06  0476     IORWF outp, W
+0E07  1D03     BTFSS STATUS, 0x2
+0E08  2E0A     GOTO 0x60A
+0E09  2E0B     GOTO 0x60B
+0E0A  2E12     GOTO 0x612
+301:                   outp = outbuff;
+0E0B  308C     MOVLW 0x8C
+0E0C  00F6     MOVWF outp
+0E0D  3020     MOVLW 0x20
+0E0E  00F7     MOVWF 0x77
+302:                   PIE1bits.TXIE = 1;
+0E0F  0021     MOVLB 0x1
+0E10  1611     BSF PIR1, 0x4
+0E11  2E12     GOTO 0x612
+303:               }
+304:           }
+0E12  0008     RETURN
+305:           
+306:           void putch(char data)
+307:           {
+308:               msg_writebyte(data);
+309:           }
+310:           
+311:           /* called from interrupt routine to send next char */
+312:           void msg_sendnext(void)
+313:           {
+314:               /* we have finished, turn off the iterrupt */
+315:               if (outp == 0 || *outp == 0) {
+0BEF  0877     MOVF 0x77, W
+0BF0  0476     IORWF outp, W
+0BF1  1903     BTFSC STATUS, 0x2
+0BF2  2BF4     GOTO 0x3F4
+0BF3  2BF5     GOTO 0x3F5
+0BF4  2BFE     GOTO 0x3FE
+0BF5  0876     MOVF outp, W
+0BF6  0086     MOVWF FSR1L
+0BF7  0877     MOVF 0x77, W
+0BF8  0087     MOVWF FSR1H
+0BF9  0881     MOVF INDF1, F
+0BFA  1D03     BTFSS STATUS, 0x2
+0BFB  2BFD     GOTO 0x3FD
+0BFC  2BFE     GOTO 0x3FE
+0BFD  2C05     GOTO 0x405
+316:                   PIE1bits.TXIE = 0;
+0BFE  0021     MOVLB 0x1
+0BFF  1211     BCF PIR1, 0x4
+317:                   outp = 0;
+0C00  01F6     CLRF outp
+0C01  01F7     CLRF 0x77
+318:                   outlen = 0;
+0C02  01F9     CLRF outlen
+0C03  2C10     GOTO 0x410
+319:                   return;
+0C04  2C10     GOTO 0x410
+320:               }
+321:               TXREG = *outp;
+0C05  0876     MOVF outp, W
+0C06  0086     MOVWF FSR1L
+0C07  0877     MOVF 0x77, W
+0C08  0087     MOVWF FSR1H
+0C09  0801     MOVF INDF1, W
+0C0A  0023     MOVLB 0x3
+0C0B  009A     MOVWF TMR2
+322:               outp++;
+0C0C  3001     MOVLW 0x1
+0C0D  07F6     ADDWF outp, F
+0C0E  3000     MOVLW 0x0
+0C0F  3DF7     ADDWFC 0x77, F
+323:           }
+0C10  0008     RETURN
+324:           
+325:           /* called from interrupt routine to receive next byte */
+326:           void msg_recvnext(void)
+327:           {
+328:               while (PIR1bits.RCIF) {
+0C60  2C85     GOTO 0x485
+0C85  0020     MOVLB 0x0
+0C86  1A91     BTFSC PIR1, 0x5
+0C87  2C89     GOTO 0x489
+0C88  2C8A     GOTO 0x48A
+0C89  2C61     GOTO 0x461
+0C8A  2C8B     GOTO 0x48B
+329:                   bool err = RCSTAbits.FERR;
+0C61  3000     MOVLW 0x0
+0C62  0023     MOVLB 0x3
+0C63  191D     BTFSC 0x1D, 0x2
+0C64  3001     MOVLW 0x1
+0C65  00F1     MOVWF err
+330:                   char new = RCREG;
+0C66  0819     MOVF T1GCON, W
+0C67  00F0     MOVWF 0x70
+0C68  0870     MOVF 0x70, W
+0C69  00F2     MOVWF new
+331:           
+332:                   /* bad char, skip it */
+333:                   if (err) continue;
+0C6A  0871     MOVF err, W
+0C6B  1D03     BTFSS STATUS, 0x2
+0C6C  2C6E     GOTO 0x46E
+0C6D  2C70     GOTO 0x470
+0C6E  2C85     GOTO 0x485
+0C6F  2C85     GOTO 0x485
+334:           
+335:                   /* our input buffer has overflowed */
+336:                   if (inlen > sizeof(inbuff)) return;
+0C70  300B     MOVLW 0xB
+0C71  0278     SUBWF inlen, W
+0C72  1C03     BTFSS STATUS, 0x0
+0C73  2C75     GOTO 0x475
+0C74  2C76     GOTO 0x476
+0C75  2C78     GOTO 0x478
+0C76  2C8B     GOTO 0x48B
+0C77  2C8B     GOTO 0x48B
+337:           
+338:                   /* keep this one */
+339:                   inbuff[inlen++] = new;
+0C78  0872     MOVF new, W
+0C79  00F0     MOVWF 0x70
+0C7A  0878     MOVF inlen, W
+0C7B  3ECD     ADDLW 0xCD
+0C7C  0086     MOVWF FSR1L
+0C7D  0187     CLRF FSR1H
+0C7E  0870     MOVF 0x70, W
+0C7F  0081     MOVWF INDF1
+0C80  3001     MOVLW 0x1
+0C81  00F0     MOVWF 0x70
+0C82  0870     MOVF 0x70, W
+0C83  07F8     ADDWF inlen, F
+0C84  2C85     GOTO 0x485
+340:               }
+341:           }
+0C8B  0008     RETURN
+342:           
+343:           bool msg_recvready(void)
+344:           {
+345:               if (inlen > 0) return 1;
+0B3A  0878     MOVF inlen, W
+0B3B  1D03     BTFSS STATUS, 0x2
+0B3C  2B3E     GOTO 0x33E
+0B3D  2B41     GOTO 0x341
+0B3E  3001     MOVLW 0x1
+0B3F  2B43     GOTO 0x343
+0B40  2B43     GOTO 0x343
+346:               return 0;
+0B41  3000     MOVLW 0x0
+0B42  2B43     GOTO 0x343
+347:           }
+0B43  0008     RETURN
+348:           
+349:           char msg_recv(void)
+350:           {
+351:               if (inlen == 0) return 0;
+0D56  08F8     MOVF inlen, F
+0D57  1D03     BTFSS STATUS, 0x2
+0D58  2D5A     GOTO 0x55A
+0D59  2D5B     GOTO 0x55B
+0D5A  2D5E     GOTO 0x55E
+0D5B  3000     MOVLW 0x0
+0D5C  2D91     GOTO 0x591
+0D5D  2D91     GOTO 0x591
+352:           
+353:               /* record and disable the interupt */
+354:               bool in = PIE1bits.RCIE;
+0D5E  3000     MOVLW 0x0
+0D5F  0021     MOVLB 0x1
+0D60  1A91     BTFSC PIR1, 0x5
+0D61  3001     MOVLW 0x1
+0D62  0020     MOVLB 0x0
+0D63  00B5     MOVWF in
+355:               PIE1bits.RCIE = 0;
+0D64  0021     MOVLB 0x1
+0D65  1291     BCF PIR1, 0x5
+356:           
+357:               char new = inbuff[0];
+0D66  084D     MOVF 0x4D, W
+0D67  00F4     MOVWF i
+0D68  0874     MOVF i, W
+0D69  0020     MOVLB 0x0
+0D6A  00B6     MOVWF p
+358:               inlen--;
+0D6B  3001     MOVLW 0x1
+0D6C  02F8     SUBWF inlen, F
+359:           
+360:               /* shuffle them down one */
+361:               for (char i=0;i<inlen;i++)
+0D6D  01B7     CLRF i
+0D6E  2D81     GOTO 0x581
+0D7C  3001     MOVLW 0x1
+0D7D  00F4     MOVWF i
+0D7E  0874     MOVF i, W
+0D7F  07B7     ADDWF i, F
+0D80  2D81     GOTO 0x581
+0D81  0878     MOVF inlen, W
+0D82  0237     SUBWF i, W
+0D83  1C03     BTFSS STATUS, 0x0
+0D84  2D86     GOTO 0x586
+0D85  2D87     GOTO 0x587
+0D86  2D6F     GOTO 0x56F
+0D87  2D88     GOTO 0x588
+362:                   inbuff[i] = inbuff[i+1];
+0D6F  0837     MOVF i, W
+0D70  3E01     ADDLW 0x1
+0D71  3ECD     ADDLW 0xCD
+0D72  0086     MOVWF FSR1L
+0D73  0187     CLRF FSR1H
+0D74  0801     MOVF INDF1, W
+0D75  00F4     MOVWF i
+0D76  0837     MOVF i, W
+0D77  3ECD     ADDLW 0xCD
+0D78  0086     MOVWF FSR1L
+0D79  0187     CLRF FSR1H
+0D7A  0874     MOVF i, W
+0D7B  0081     MOVWF INDF1
+363:           
+364:               /* restore the interupt */
+365:               PIE1bits.RCIE = in;
+0D88  0835     MOVF in, W
+0D89  0021     MOVLB 0x1
+0D8A  1D03     BTFSS STATUS, 0x2
+0D8B  1691     BSF PIR1, 0x5
+0D8C  1903     BTFSC STATUS, 0x2
+0D8D  1291     BCF PIR1, 0x5
+366:               return new;
+0D8E  0020     MOVLB 0x0
+0D8F  0836     MOVF p, W
+0D90  2D91     GOTO 0x591
+367:           }
+0D91  0008     RETURN
+368:           
+369:           
+370:           void int_disable(void)
+371:           {
+372:               INTCONbits.GIE = 0;
+0B22  138B     BCF INTCON, 0x7
+373:           }
+0B23  0008     RETURN
+374:           
+375:           void int_enable(void)
+376:           {
+377:               INTCONbits.GIE = 1;
+0B20  178B     BSF INTCON, 0x7
+378:           }
+0B21  0008     RETURN
+---  /home/justin/MPLABXProjects/uart test.X/interrupts.c  ----------------------------------------------
+1:             /******************************************************************************/
+2:             /*Files to Include                                                            */
+3:             /******************************************************************************/
+4:             
+5:             #if defined(__XC)
+6:                 #include <xc.h>         /* XC8 General Include File */
+7:             #elif defined(HI_TECH_C)
+8:                 #include <htc.h>        /* HiTech General Include File */
+9:             #endif
+10:            
+11:            #include <stdint.h>         /* For uint8_t definition */
+12:            #include <stdbool.h>        /* For true/false definition */
+13:            #include "user.h"
+14:            
+15:            /******************************************************************************/
+16:            /* Interrupt Routines                                                         */
+17:            /******************************************************************************/
+18:            
+19:            /* Baseline devices don't have interrupts. Unfortunately the baseline detection 
+20:             * macro is named _PIC12 */
+21:            
+22:            #ifndef _PIC12
+23:            
+24:            void interrupt isr(void)
+25:            {
+0004  3180     MOVLP 0x0
+0005  0020     MOVLB 0x0
+0006  087F     MOVF 0x7F, W
+0007  00F3     MOVWF 0x73
+26:                /* This code stub shows general interrupt handling.  Note that these
+27:                conditional statements are not handled within 3 seperate if blocks.
+28:                Do not use a seperate if block for each interrupt flag to avoid run
+29:                time errors. */
+30:            
+31:                if (PIE1bits.TXIE && PIR1bits.TXIF)
+0008  0021     MOVLB 0x1
+0009  1E11     BTFSS PIR1, 0x4
+000A  280C     GOTO 0xC
+000B  280D     GOTO 0xD
+000C  2816     GOTO 0x16
+000D  0020     MOVLB 0x0
+000E  1E11     BTFSS PIR1, 0x4
+000F  2811     GOTO 0x11
+0010  2812     GOTO 0x12
+0011  2816     GOTO 0x16
+32:                    msg_sendnext();
+0012  318B     MOVLP 0xB
+0013  23EF     CALL 0x3EF
+0014  3180     MOVLP 0x0
+0015  2816     GOTO 0x16
+33:            
+34:                if (PIE1bits.RCIE && PIR1bits.RCIF)
+0016  0021     MOVLB 0x1
+0017  1E91     BTFSS PIR1, 0x5
+0018  281A     GOTO 0x1A
+0019  281B     GOTO 0x1B
+001A  2824     GOTO 0x24
+001B  0020     MOVLB 0x0
+001C  1E91     BTFSS PIR1, 0x5
+001D  281F     GOTO 0x1F
+001E  2820     GOTO 0x20
+001F  2824     GOTO 0x24
+35:                    msg_recvnext();
+0020  318C     MOVLP 0xC
+0021  2460     CALL 0x460
+0022  3180     MOVLP 0x0
+0023  2824     GOTO 0x24
+36:                
+37:            #if 0
+38:            
+39:                /* TODO Add interrupt routine code here. */
+40:            
+41:                /* Determine which flag generated the interrupt */
+42:                if(<Interrupt Flag 1>)
+43:                {
+44:                    <Interrupt Flag 1=0>; /* Clear Interrupt Flag 1 */
+45:                }
+46:                else if (<Interrupt Flag 2>)
+47:                {
+48:                    <Interrupt Flag 2=0>; /* Clear Interrupt Flag 2 */
+49:                }
+50:                else
+51:                {
+52:                    /* Unhandled interrupts */
+53:                }
+54:            
+55:            #endif
+56:            
+57:            }
+0024  0873     MOVF 0x73, W
+58:            #endif
+59:            
+60:            

diff --git a/dist/XC8_12F1822/production/uart_test.X.production.sdb b/dist/XC8_12F1822/production/uart_test.X.production.sdb
new file mode 100644 (file)
index 0000000..9525e09
--- /dev/null
+++ b/dist/XC8_12F1822/production/uart_test.X.production.sdb
@@ -0,0 +1,368 @@
+[p LITE_MODE AUTOSTATIC PIC14 PIC14E ]
+[d version 1.1 ]
+[d edition pro ]
+[d chip 12F1822 ]
+"53 configuration_bits.c
+[s S19 . 1 `uc 1 TMR1IE 1 0 :1:0 
+`uc 1 TMR2IE 1 0 :1:1 
+`uc 1 CCP1IE 1 0 :1:2 
+`uc 1 SSP1IE 1 0 :1:3 
+`uc 1 TXIE 1 0 :1:4 
+`uc 1 RCIE 1 0 :1:5 
+`uc 1 ADIE 1 0 :1:6 
+`uc 1 TMR1GIE 1 0 :1:7 
+]
+[u S28 . 1 `S19 1 . 1 0 ]
+"1274 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[s S40 . 1 `uc 1 TMR1IF 1 0 :1:0 
+`uc 1 TMR2IF 1 0 :1:1 
+`uc 1 CCP1IF 1 0 :1:2 
+`uc 1 SSP1IF 1 0 :1:3 
+`uc 1 TXIF 1 0 :1:4 
+`uc 1 RCIF 1 0 :1:5 
+`uc 1 ADIF 1 0 :1:6 
+`uc 1 TMR1GIF 1 0 :1:7 
+]
+[u S49 . 1 `S40 1 . 1 0 ]
+"25 interrupts.c
+[v F2213 `(v  1 t 0 ]
+"15 user.h
+[s S104 . 1 `uc 1 TRISA0 1 0 :1:0 
+`uc 1 TRISA1 1 0 :1:1 
+`uc 1 TRISA2 1 0 :1:2 
+`uc 1 TRISA3 1 0 :1:3 
+`uc 1 TRISA4 1 0 :1:4 
+`uc 1 TRISA5 1 0 :1:5 
+]
+[u S111 . 1 `S104 1 . 1 0 ]
+"1223 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[s S121 . 1 `uc 1 RA0 1 0 :1:0 
+`uc 1 RA1 1 0 :1:1 
+`uc 1 RA2 1 0 :1:2 
+`uc 1 RA3 1 0 :1:3 
+`uc 1 RA4 1 0 :1:4 
+`uc 1 RA5 1 0 :1:5 
+]
+[s S128 . 1 `uc 1 AN0 1 0 :1:0 
+`uc 1 AN1 1 0 :1:1 
+`uc 1 AN2 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 AN3 1 0 :1:4 
+]
+[s S134 . 1 `uc 1 CPS0 1 0 :1:0 
+`uc 1 CPS1 1 0 :1:1 
+`uc 1 CPS2 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 CPS3 1 0 :1:4 
+]
+[s S140 . 1 `uc 1 C1INP 1 0 :1:0 
+`uc 1 C1IN0N 1 0 :1:1 
+`uc 1 C1OUT 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 C1IN1N 1 0 :1:4 
+]
+[s S146 . 1 `uc 1 DACOUT 1 0 :1:0 
+`uc 1 SRI 1 0 :1:1 
+`uc 1 SRQ 1 0 :1:2 
+`uc 1 . 1 0 :2:3 
+`uc 1 SRNQ 1 0 :1:5 
+]
+[s S152 . 1 `uc 1 . 1 0 :1:0 
+`uc 1 SCK 1 0 :1:1 
+`uc 1 T0CKI 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 T1OSO 1 0 :1:4 
+`uc 1 T1CKI 1 0 :1:5 
+]
+[s S159 . 1 `uc 1 . 1 0 :1:0 
+`uc 1 SCL 1 0 :1:1 
+`uc 1 SDA 1 0 :1:2 
+`uc 1 nMCLR 1 0 :1:3 
+`uc 1 CLKR 1 0 :1:4 
+`uc 1 T1OSI 1 0 :1:5 
+]
+[s S166 . 1 `uc 1 MDOUT 1 0 :1:0 
+`uc 1 MDMIN 1 0 :1:1 
+`uc 1 MDCIN1 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 MDCIN2 1 0 :1:4 
+]
+[s S172 . 1 `uc 1 . 1 0 :2:0 
+`uc 1 SDI 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 OSC2 1 0 :1:4 
+`uc 1 OSC1 1 0 :1:5 
+]
+[s S178 . 1 `uc 1 . 1 0 :2:0 
+`uc 1 FLT0 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 CLKOUT 1 0 :1:4 
+`uc 1 CLKIN 1 0 :1:5 
+]
+[u S184 . 1 `S121 1 . 1 0 `S128 1 . 1 0 `S134 1 . 1 0 `S140 1 . 1 0 `S146 1 . 1 0 `S152 1 . 1 0 `S159 1 . 1 0 `S166 1 . 1 0 `S172 1 . 1 0 `S178 1 . 1 0 ]
+"27 onewire.h
+[v F3636 `(v  1 t 0 ]
+"28
+[v F3639 `(v  1 t 0 ]
+"29
+[v F3642 `(v  1 t 0 ]
+"30
+[v F3645 `(uc  1 t 1 ]
+"16 user.h
+[s S346 . 1 `uc 1 TMR1IE 1 0 :1:0 
+`uc 1 TMR2IE 1 0 :1:1 
+`uc 1 CCP1IE 1 0 :1:2 
+`uc 1 SSP1IE 1 0 :1:3 
+`uc 1 TXIE 1 0 :1:4 
+`uc 1 RCIE 1 0 :1:5 
+`uc 1 ADIE 1 0 :1:6 
+`uc 1 TMR1GIE 1 0 :1:7 
+]
+[u S355 . 1 `S19 1 . 1 0 ]
+"2824 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[s S359 . 1 `uc 1 RX9D 1 0 :1:0 
+`uc 1 OERR 1 0 :1:1 
+`uc 1 FERR 1 0 :1:2 
+`uc 1 ADDEN 1 0 :1:3 
+`uc 1 CREN 1 0 :1:4 
+`uc 1 SREN 1 0 :1:5 
+`uc 1 RX9 1 0 :1:6 
+`uc 1 SPEN 1 0 :1:7 
+]
+[u S368 . 1 `S359 1 . 1 0 ]
+"2805
+[s S381 . 1 `uc 1 TMR1IF 1 0 :1:0 
+`uc 1 TMR2IF 1 0 :1:1 
+`uc 1 CCP1IF 1 0 :1:2 
+`uc 1 SSP1IF 1 0 :1:3 
+`uc 1 TXIF 1 0 :1:4 
+`uc 1 RCIF 1 0 :1:5 
+`uc 1 ADIF 1 0 :1:6 
+`uc 1 TMR1GIF 1 0 :1:7 
+]
+[u S390 . 1 `S40 1 . 1 0 ]
+"715
+[s S393 . 1 `uc 1 IOCIF 1 0 :1:0 
+`uc 1 INTF 1 0 :1:1 
+`uc 1 TMR0IF 1 0 :1:2 
+`uc 1 IOCIE 1 0 :1:3 
+`uc 1 INTE 1 0 :1:4 
+`uc 1 TMR0IE 1 0 :1:5 
+`uc 1 PEIE 1 0 :1:6 
+`uc 1 GIE 1 0 :1:7 
+]
+[s S402 . 1 `uc 1 . 1 0 :2:0 
+`uc 1 T0IF 1 0 :1:2 
+`uc 1 . 1 0 :2:3 
+`uc 1 T0IE 1 0 :1:5 
+]
+[u S407 . 1 `S393 1 . 1 0 `S402 1 . 1 0 ]
+"390 main.c
+[s S555 . 1 `uc 1 SCS0 1 0 :1:0 
+`uc 1 SCS1 1 0 :1:1 
+`uc 1 . 1 0 :1:2 
+`uc 1 IRCF0 1 0 :1:3 
+`uc 1 IRCF1 1 0 :1:4 
+`uc 1 IRCF2 1 0 :1:5 
+`uc 1 IRCF3 1 0 :1:6 
+`uc 1 SPLLEN 1 0 :1:7 
+]
+[s S564 . 1 `uc 1 SCS 1 0 :2:0 
+`uc 1 . 1 0 :1:2 
+`uc 1 IRCF 1 0 :4:3 
+]
+[u S568 . 1 `S555 1 . 1 0 `S564 1 . 1 0 ]
+"26 system.c
+[s S597 . 1 `uc 1 SWDTEN 1 0 :1:0 
+`uc 1 WDTPS0 1 0 :1:1 
+`uc 1 WDTPS1 1 0 :1:2 
+`uc 1 WDTPS2 1 0 :1:3 
+`uc 1 WDTPS3 1 0 :1:4 
+`uc 1 WDTPS4 1 0 :1:5 
+]
+[s S604 . 1 `uc 1 . 1 0 :1:0 
+`uc 1 WDTPS 1 0 :5:1 
+]
+[u S607 . 1 `S597 1 . 1 0 `S604 1 . 1 0 ]
+"1508 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[s S621 . 1 `uc 1 CCP1SEL 1 0 :1:0 
+`uc 1 P1BSEL 1 0 :1:1 
+`uc 1 TXCKSEL 1 0 :1:2 
+`uc 1 T1GSEL 1 0 :1:3 
+`uc 1 . 1 0 :1:4 
+`uc 1 SSSEL 1 0 :1:5 
+`uc 1 SDOSEL 1 0 :1:6 
+`uc 1 RXDTSEL 1 0 :1:7 
+]
+[s S630 . 1 `uc 1 . 1 0 :5:0 
+`uc 1 SS1SEL 1 0 :1:5 
+`uc 1 SDO1SEL 1 0 :1:6 
+]
+[u S634 . 1 `S621 1 . 1 0 `S630 1 . 1 0 ]
+"2459
+[s S651 . 1 `uc 1 TRISA0 1 0 :1:0 
+`uc 1 TRISA1 1 0 :1:1 
+`uc 1 TRISA2 1 0 :1:2 
+`uc 1 TRISA3 1 0 :1:3 
+`uc 1 TRISA4 1 0 :1:4 
+`uc 1 TRISA5 1 0 :1:5 
+]
+[u S658 . 1 `S104 1 . 1 0 ]
+"3072
+[s S663 . 1 `uc 1 PS0 1 0 :1:0 
+`uc 1 PS1 1 0 :1:1 
+`uc 1 PS2 1 0 :1:2 
+`uc 1 PSA 1 0 :1:3 
+`uc 1 TMR0SE 1 0 :1:4 
+`uc 1 TMR0CS 1 0 :1:5 
+`uc 1 INTEDG 1 0 :1:6 
+`uc 1 nWPUEN 1 0 :1:7 
+]
+[s S672 . 1 `uc 1 PS 1 0 :3:0 
+`uc 1 . 1 0 :1:3 
+`uc 1 T0SE 1 0 :1:4 
+`uc 1 T0CS 1 0 :1:5 
+]
+[u S677 . 1 `S663 1 . 1 0 `S672 1 . 1 0 ]
+"1380
+[s S695 . 1 `uc 1 TX9D 1 0 :1:0 
+`uc 1 TRMT 1 0 :1:1 
+`uc 1 BRGH 1 0 :1:2 
+`uc 1 SENDB 1 0 :1:3 
+`uc 1 SYNC 1 0 :1:4 
+`uc 1 TXEN 1 0 :1:5 
+`uc 1 TX9 1 0 :1:6 
+`uc 1 CSRC 1 0 :1:7 
+]
+[u S704 . 1 `S695 1 . 1 0 ]
+"2977
+[s S716 . 1 `uc 1 RX9D 1 0 :1:0 
+`uc 1 OERR 1 0 :1:1 
+`uc 1 FERR 1 0 :1:2 
+`uc 1 ADDEN 1 0 :1:3 
+`uc 1 CREN 1 0 :1:4 
+`uc 1 SREN 1 0 :1:5 
+`uc 1 RX9 1 0 :1:6 
+`uc 1 SPEN 1 0 :1:7 
+]
+[u S725 . 1 `S359 1 . 1 0 ]
+"2916
+[s S728 . 1 `uc 1 ABDEN 1 0 :1:0 
+`uc 1 WUE 1 0 :1:1 
+`uc 1 . 1 0 :1:2 
+`uc 1 BRG16 1 0 :1:3 
+`uc 1 SCKP 1 0 :1:4 
+`uc 1 . 1 0 :1:5 
+`uc 1 RCIDL 1 0 :1:6 
+`uc 1 ABDOVF 1 0 :1:7 
+]
+[u S737 . 1 `S728 1 . 1 0 ]
+"2848
+[s S750 . 1 `uc 1 IOCIF 1 0 :1:0 
+`uc 1 INTF 1 0 :1:1 
+`uc 1 TMR0IF 1 0 :1:2 
+`uc 1 IOCIE 1 0 :1:3 
+`uc 1 INTE 1 0 :1:4 
+`uc 1 TMR0IE 1 0 :1:5 
+`uc 1 PEIE 1 0 :1:6 
+`uc 1 GIE 1 0 :1:7 
+]
+[s S759 . 1 `uc 1 . 1 0 :2:0 
+`uc 1 T0IF 1 0 :1:2 
+`uc 1 . 1 0 :2:3 
+`uc 1 T0IE 1 0 :1:5 
+]
+[u S764 . 1 `S393 1 . 1 0 `S402 1 . 1 0 ]
+"355
+[s S768 . 1 `uc 1 TMR1IE 1 0 :1:0 
+`uc 1 TMR2IE 1 0 :1:1 
+`uc 1 CCP1IE 1 0 :1:2 
+`uc 1 SSP1IE 1 0 :1:3 
+`uc 1 TXIE 1 0 :1:4 
+`uc 1 RCIE 1 0 :1:5 
+`uc 1 ADIE 1 0 :1:6 
+`uc 1 TMR1GIE 1 0 :1:7 
+]
+[u S777 . 1 `S19 1 . 1 0 ]
+"63 user.c
+[s S821 . 1 `uc 1 RA0 1 0 :1:0 
+`uc 1 RA1 1 0 :1:1 
+`uc 1 RA2 1 0 :1:2 
+`uc 1 RA3 1 0 :1:3 
+`uc 1 RA4 1 0 :1:4 
+`uc 1 RA5 1 0 :1:5 
+]
+[s S828 . 1 `uc 1 AN0 1 0 :1:0 
+`uc 1 AN1 1 0 :1:1 
+`uc 1 AN2 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 AN3 1 0 :1:4 
+]
+[s S834 . 1 `uc 1 CPS0 1 0 :1:0 
+`uc 1 CPS1 1 0 :1:1 
+`uc 1 CPS2 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 CPS3 1 0 :1:4 
+]
+[s S840 . 1 `uc 1 C1INP 1 0 :1:0 
+`uc 1 C1IN0N 1 0 :1:1 
+`uc 1 C1OUT 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 C1IN1N 1 0 :1:4 
+]
+[s S846 . 1 `uc 1 DACOUT 1 0 :1:0 
+`uc 1 SRI 1 0 :1:1 
+`uc 1 SRQ 1 0 :1:2 
+`uc 1 . 1 0 :2:3 
+`uc 1 SRNQ 1 0 :1:5 
+]
+[s S852 . 1 `uc 1 . 1 0 :1:0 
+`uc 1 SCK 1 0 :1:1 
+`uc 1 T0CKI 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 T1OSO 1 0 :1:4 
+`uc 1 T1CKI 1 0 :1:5 
+]
+[s S859 . 1 `uc 1 . 1 0 :1:0 
+`uc 1 SCL 1 0 :1:1 
+`uc 1 SDA 1 0 :1:2 
+`uc 1 nMCLR 1 0 :1:3 
+`uc 1 CLKR 1 0 :1:4 
+`uc 1 T1OSI 1 0 :1:5 
+]
+[s S866 . 1 `uc 1 MDOUT 1 0 :1:0 
+`uc 1 MDMIN 1 0 :1:1 
+`uc 1 MDCIN1 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 MDCIN2 1 0 :1:4 
+]
+[s S872 . 1 `uc 1 . 1 0 :2:0 
+`uc 1 SDI 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 OSC2 1 0 :1:4 
+`uc 1 OSC1 1 0 :1:5 
+]
+[s S878 . 1 `uc 1 . 1 0 :2:0 
+`uc 1 FLT0 1 0 :1:2 
+`uc 1 . 1 0 :1:3 
+`uc 1 CLKOUT 1 0 :1:4 
+`uc 1 CLKIN 1 0 :1:5 
+]
+[u S884 . 1 `S121 1 . 1 0 `S128 1 . 1 0 `S134 1 . 1 0 `S140 1 . 1 0 `S146 1 . 1 0 `S152 1 . 1 0 `S159 1 . 1 0 `S166 1 . 1 0 `S172 1 . 1 0 `S178 1 . 1 0 ]
+"489 /opt/microchip/xc8/v1.12/include/pic12f1822.h
+[s S896 . 1 `uc 1 TRISA0 1 0 :1:0 
+`uc 1 TRISA1 1 0 :1:1 
+`uc 1 TRISA2 1 0 :1:2 
+`uc 1 TRISA3 1 0 :1:3 
+`uc 1 TRISA4 1 0 :1:4 
+`uc 1 TRISA5 1 0 :1:5 
+]
+[u S903 . 1 `S104 1 . 1 0 ]
+"27 onewire.h
+[v F3573 `(v  1 t 0 ]
+"28
+[v F3576 `(v  1 t 0 ]
+"29
+[v F3579 `(v  1 t 0 ]
+"30
+[v F3582 `(uc  1 t 1 ]

diff --git a/funclist b/funclist
new file mode 100644 (file)
index 0000000..8088ab4
--- /dev/null
+++ b/funclist
@@ -0,0 +1,41 @@
+_OW_reset: CODE, 3190 0 41
+__stringtab: STRCODE, 1792 0 1
+__stringdata: STRCODE, 2049 0 788
+_timer_disable: CODE, 2914 0 4
+_OW_parasite: CODE, 3086 0 32
+_int_disable: CODE, 2905 0 2
+_dscrc_table: STRCODE, 1793 0 256
+_OW_search_init: CODE, 3320 0 45
+_msg_write: CODE, 3782 0 70
+_msg_empty: CODE, 2964 0 12
+_OW_read_bit: CODE, 3028 0 28
+_OW_read_byte: CODE, 3152 0 38
+_ConfigureOscillator: CODE, 2943 0 9
+_main: CODE, 55 0 1547
+_OW_read_block: CODE, 3462 0 60
+_msg_writebyte: CODE, 3644 0 68
+_InitApp: CODE, 3231 0 44
+_tohex: CODE, 1710 0 71
+__initialization: CODE, 3365 0 45
+___lwdiv: CODE, 3712 0 70
+_OW_start: CODE, 2910 0 4
+_OW_convert: CODE, 1602 0 108
+_OW_identify: CODE, 3522 0 61
+_isr: CODE, 4 0 49
+_float_OW: CODE, 2907 0 3
+_msg_sendnext: CODE, 3118 0 34
+_read_OW: CODE, 2935 0 8
+_int_enable: CODE, 2903 0 2
+_OW_write_bit: CODE, 3004 0 24
+_drive_OW_low: CODE, 2923 0 5
+_msg_recv: CODE, 3583 0 61
+_OW_write_byte: CODE, 3056 0 30
+_timer_enable: CODE, 2928 0 7
+_drive_OW_high: CODE, 2918 0 5
+_OW_select_id: CODE, 3413 0 49
+_msg_recvnext: CODE, 3275 0 45
+_docrc8: CODE, 2988 0 16
+_msg_recvready: CODE, 1781 0 11
+_OW_search: CODE, 3852 0 244
+_timer_rollover: CODE, 2952 0 12
+Total: 4009
\ No newline at end of file

diff --git a/getting_started.txt b/getting_started.txt
new file mode 100644 (file)
index 0000000..afe34a4
--- /dev/null
+++ b/getting_started.txt
@@ -0,0 +1,86 @@
+This project is a general template file for the PIC12 Family of
+microcontrollers.  It's purpose is to provide a project shell for users to
+get started designing their own applications.  Final qualification and testing
+of this project is left to the user.
+
+ADVANCED USER TIP
+
+From the main menu, refer to the Task list by going to Window > Tasks (Ctrl+6).
+As long as the task window is not configured to filter out any tasks,
+the getting started TODO list embedded in this project will be displayed.
+
+Make sure the 'Show tasks for the main project and for the open projects which
+depend on it' option is selected on the left hand side of the Tasks window so
+that tasks related to other projects are not active.
+
+HOW TO ADD YOUR OWN CODE TO A TEMPLATE
+
+STEP 1
+
+First install the appropriate C compiler if you have not done so already.
+
+See www.microchip.com/compilers
+
+Next, build this project by clicking the Clean and Build Icon (the hammer and
+broom symbol) in the MPLAB X IDE Toolbar.  If this project builds, then you are
+ready to make changes for your own application.  If the project does not build,
+you need to troubleshoot why the project does not build before moving on.
+
+STEP 2
+
+Embed your device's configuration bits into the code.  Instructions for this
+are commented in configuration_bits.c
+
+STEP 3
+
+Unless interrupts are not used in your application, fill in the interrupt
+vector code.  Code stubs are provided in interrupts.c.  Check the device
+datasheet to confirm that you are servicing all the relevant enabled
+interrupts in your application within the ISR.  Note that it is important
+to check interrupt flags in sequence within one conditional statement to
+avoid interrupt contention which could result in corrupting the interrupt
+context.
+
+STEP 4
+
+Define system parameters such as the system operating frequency in system.h.
+
+If your device stores an oscillator calibration value at the end of program
+memory, incorporate the _READ_OSCCAL_DATA() function in system.c.  The device
+datasheet will tell you if calibration data is stored at the end of the
+device memory.
+
+Add system level functions to system.h and system.c.  For example, if
+you want a function to determine the reset source of the device to know if you
+need to backup data, do an oscillator switch, enter a low power mode, etc...
+these types of functions may be added to system.c and prototypes can go in
+system.h.
+
+STEP 5
+
+Add user level functions to user.h and user.c.  User level functions are
+functions that initialize I/O, initialize user peripherals like the ADC,
+compute user algorithms, perform calculations on sampled user data, and so on.
+User function prototypes and macros may be placed in user.h, and user
+functions themselves may go in user.c
+
+STEP 6
+
+Add code to main.c on the line that says <INSERT USER APPLICATION CODE HERE>.
+For example, here you would call functions in user.c or system.c, or possibly
+setup your own state machine or primary code loop.
+
+Global variables may be added to main.c as well.  As a general practice, macros
+and prototypes may go in header files, but variable declarations should not
+go in .h files.  Variable declarations should be placed in .c files.
+
+STEP 7
+
+Design the rest of your application.  Add new files to the application, and
+test the finished product.
+
+STEP 8
+
+Document what the project does and include other project information in
+project_information.txt.
+

diff --git a/interrupts.c b/interrupts.c
new file mode 100644 (file)
index 0000000..073e317
--- /dev/null
+++ b/interrupts.c
@@ -0,0 +1,64 @@
+/******************************************************************************/
+/*Files to Include                                                            */
+/******************************************************************************/
+
+#if defined(__XC)
+    #include <xc.h>         /* XC8 General Include File */
+#elif defined(HI_TECH_C)
+    #include <htc.h>        /* HiTech General Include File */
+#endif
+
+#include <stdint.h>         /* For uint8_t definition */
+#include <stdbool.h>        /* For true/false definition */
+#include "user.h"
+
+/******************************************************************************/
+/* Interrupt Routines                                                         */
+/******************************************************************************/
+
+/* Baseline devices don't have interrupts. Unfortunately the baseline detection 
+ * macro is named _PIC12 */
+
+#ifndef _PIC12
+
+void interrupt isr(void)
+{
+    /* This code stub shows general interrupt handling.  Note that these
+    conditional statements are not handled within 3 seperate if blocks.
+    Do not use a seperate if block for each interrupt flag to avoid run
+    time errors. */
+
+    if (PIE1bits.TXIE && PIR1bits.TXIF)
+        msg_sendnext();
+
+    if (PIE1bits.RCIE && PIR1bits.RCIF)
+        msg_recvnext();
+
+    if (T1CONbits.TMR1ON && PIR1bits.TMR1IF) {
+        timer_rollover();
+    }
+    
+#if 0
+
+    /* TODO Add interrupt routine code here. */
+
+    /* Determine which flag generated the interrupt */
+    if(<Interrupt Flag 1>)
+    {
+        <Interrupt Flag 1=0>; /* Clear Interrupt Flag 1 */
+    }
+    else if (<Interrupt Flag 2>)
+    {
+        <Interrupt Flag 2=0>; /* Clear Interrupt Flag 2 */
+    }
+    else
+    {
+        /* Unhandled interrupts */
+    }
+
+#endif
+
+}
+#endif
+
+

diff --git a/legal_disclaimer.txt b/legal_disclaimer.txt
new file mode 100644 (file)
index 0000000..51ce0bb
--- /dev/null
+++ b/legal_disclaimer.txt
@@ -0,0 +1,24 @@
+Microchip licenses this software to you solely for use with Microchip products.
+The software is owned by Microchip and/or its licensors, and is protected under
+applicable copyright laws.  All rights reserved.
+
+This software and any accompanying information is for suggestion only.  It shall
+not be deemed to modify Microchip?s standard warranty for its products.  It is
+your responsibility to ensure that this software meets your requirements.
+
+SOFTWARE IS PROVIDED "AS IS".  MICROCHIP AND ITS LICENSORS EXPRESSLY DISCLAIM
+ANY WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+OR NON-INFRINGEMENT. IN NO EVENT SHALL MICROCHIP OR ITS LICENSORS BE LIABLE FOR
+ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES, LOST PROFITS OR
+LOST DATA, HARM TO YOUR EQUIPMENT, COST OF PROCUREMENT OF SUBSTITUTE GOODS,
+TECHNOLOGY OR SERVICES, ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT LIMITED
+TO ANY DEFENSE THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
+SIMILAR COSTS.
+
+To the fullest extend allowed by law, Microchip and its licensors liability
+shall not exceed the amount of fee, if any, that you have paid directly to
+Microchip to use this software.
+
+MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE
+TERMS.

diff --git a/main.c b/main.c
new file mode 100644 (file)
index 0000000..9141321
--- /dev/null
+++ b/main.c
@@ -0,0 +1,474 @@
+/******************************************************************************/
+/* Files to Include                                                           */
+/******************************************************************************/
+
+#if defined(__XC)
+    #include <xc.h>         /* XC8 General Include File */
+#elif defined(HI_TECH_C)
+    #include <htc.h>        /* HiTech General Include File */
+#endif
+
+#include <stdio.h>
+
+#include <stdint.h>        /* For uint8_t definition */
+#include <stdbool.h>       /* For true/false definition */
+
+#include "system.h"        /* System funct/params, like osc/peripheral config */
+#include "user.h"          /* User funct/params, such as InitApp */
+
+#include "onewire.h"        /* 1-wire bus functions */
+
+/******************************************************************************/
+/* User Global Variable Declaration                                           */
+/******************************************************************************/
+
+#define LED1 PORTAbits.RA4
+
+/* i.e. uint8_t <variable_name>; */
+
+char outbuff[100];
+char * outp = 0;
+uint8_t outlen = 0;
+
+char inbuff[10];
+uint8_t inlen = 0;
+
+/******************************************************************************/
+/* Main Program                                                               */
+/******************************************************************************/
+
+char prompt[9];
+
+// long time period counter, 572 steps is 5 minutes
+char automode = 0;
+uint16_t auto_counter = 0;
+
+void timer_rollover()
+{
+    if (automode) auto_counter++;
+    PIR1bits.TMR1IF = 0;
+}
+void timer_enable() {
+    auto_counter = 0;
+    automode = 1;
+    T1CONbits.TMR1ON = 1;
+}
+
+void timer_disable() {
+    automode = 0;
+    T1CONbits.TMR1ON = 0;
+}
+
+const char * banner = "\r\n\n\nPIC 1-Wire Bridge system.  Press 'H' for help.\r\n";
+
+void main(void)
+{
+    prompt[0] = 'c';
+    prompt[1] = 'm';
+    prompt[2] = 'd';
+    prompt[3] = ' ';
+    prompt[4] = '?';
+    prompt[5] = '?';
+    prompt[6] = '>';
+    prompt[7] = ' ';
+    prompt[8] = 0;
+
+    bool usermode = false;
+
+    /* Configure the oscillator for the device */
+    ConfigureOscillator();
+
+    /* Initialize I/O and Peripherals for application */
+    InitApp();
+
+    OW_start();
+    msg_write(banner);
+    //msg_write(prompt);
+    
+    LED1 = 0;
+
+    while(1)
+    {
+        CLRWDT();
+
+        if (TRISAbits.TRISA5 == 1) {
+            prompt[4] = 'i';
+            prompt[5] = PORTAbits.RA5 ? '1':'0';
+        } else {
+            prompt[4] = 'o';
+            prompt[5] = PORTAbits.RA5 ? '1':'0';
+        }
+
+
+        if (!msg_empty()) continue;
+
+        if (automode) {
+            if (auto_counter >= 572) {
+                inbuff[inlen++] = 't';
+                auto_counter = 0;
+            }
+        }
+        
+        if (!msg_recvready()) continue;
+
+        char cmd = msg_recv();
+        
+        if (cmd == '\r' || cmd == '\n') {
+            if (usermode) msg_write("\r\n");
+        }else
+        if (cmd == 'h' || cmd == 'H') {
+            msg_write(banner);
+            msg_write("\nHelp:\r\n");
+            while (!msg_empty());
+            msg_write("E - Enumerate the Bus\r\n");
+            msg_write("R - Reset Bus\r\n");
+            while (!msg_empty());
+            msg_write("0,1,3 - bus to Low, High, Tristate\r\n");
+            msg_write("I - Read (one) Device ID\r\n");
+            while (!msg_empty());
+            msg_write("P - Any device parasitic powered?\r\n");
+            msg_write("S - Read scratchpad memory\r\n");
+            while (!msg_empty());
+            msg_write("T - read temperature of all devices\r\n");
+            msg_write("A - Auto-mode. read every 5 mins.\r\n");
+            while (!msg_empty());
+            msg_write("M - Manual mode.\r\n");
+            msg_write("B - Test battery voltage\r\n");
+            while (!msg_empty());
+            usermode = true;
+        } else
+            if (cmd == 'a' || cmd == 'A') {
+            if (usermode)
+                msg_write("\rAUTO mode enabled. 5 minute timer.\r\n");
+            else
+                msg_write("AUTO ON\n");
+            timer_enable();
+        } else
+        if (cmd == 'm' || cmd == 'M') {
+            if (usermode)
+                msg_write("\rAUTO mode disabled.\r\n");
+            else
+                msg_write("AUTO OFF\n");
+            timer_disable();
+        }else
+        if (cmd == 'r' || cmd == 'R') {
+            int_disable();
+            bool present = OW_reset();
+            int_enable();
+            if (usermode) msg_write("\r");
+            if (present)
+                msg_write("RESET Device detected.\r\n");
+            else
+                msg_write("RESET No Devices detected.\r\n");
+        } else
+        if (cmd == 'e' || cmd == 'E')
+        {
+            char count = 0;
+            if (usermode) msg_write("\r");
+            OW_search_init();
+            while (OW_search())
+            {
+                char val[3];
+                if (usermode) msg_write("ENUM ");
+                for (char j=0; j<8; j++) {
+                    tohex(val, romid[j]);
+                    msg_write(val);
+                }
+                if (usermode) msg_write("\r\n"); else msg_write("\n");
+                count++;
+            }
+            if (usermode) {
+                if (count==0) msg_write("ERROR No devices found\r\n");
+            } else {
+                msg_write("END\n");
+            }
+        }else
+        if (cmd == 'i' || cmd == 'I') {
+            OW_identify();
+            char val[3];
+            if (usermode) msg_write("\rID ");
+            for (char j=0; j<8; j++) {
+                tohex(val, romid[j]);
+                msg_write(val);
+            }
+            if (usermode) msg_write("\r\n"); else msg_write("\n");
+        }else
+        if (cmd == 'p' || cmd == 'P') {
+            if (usermode) msg_write("\r");
+            bool para = OW_parasite();
+            if (usermode) {
+                if (para)
+                    msg_write("PARA Yes\r\n");
+                else
+                    msg_write("PARA No\r\n");
+            } else {
+                if (para) msg_write("PARA\n"); else msg_write("DIRECT\n");
+            }
+        }else
+        if (cmd == 's' || cmd =='S') {
+            uint8_t scratch[9];
+            romid[0] = 0; // select all devices
+            OW_read_block(0xBE, scratch, 9);
+            if (usermode) msg_write("\rSCRATCH");
+            for (char j=0; j<9; j++) {
+                char val[3];
+                tohex(val, scratch[j]);
+                msg_write(" ");
+                msg_write(val);
+            }
+            if (usermode) msg_write("\r\n"); else msg_write("\n");
+        }else
+        if (cmd == 't' || cmd == 'T') {
+            char val[3];
+            uint8_t scratch[9];
+
+            // oddly, cant do a mass-convert with parasitic
+            // they seem to all reset when you try
+
+            LED1 = 1;
+
+            // now step through every unit and read the value
+            OW_search_init();
+            while (OW_search())
+            {
+                // convert takes along time, dont trip watchdog
+                CLRWDT();
+                // ask device to do conversion
+                OW_convert();
+                CLRWDT();
+
+                // empty the scratch pad
+                for (char j=0; j<9; j++) scratch[j]=0;
+
+                // read this devices scratch pad
+                OW_read_block(0xBE, scratch, 9);
+
+                // print rom id and temperature
+                if (usermode) msg_write("\r");
+                msg_write("TEMP ");
+                for (char j=0;j<8;j++) {
+                    tohex(val, romid[j]);
+                    msg_write(val);
+                }
+                msg_write(" ");
+                tohex(val, scratch[1]);
+                msg_write(val);
+                tohex(val, scratch[0]);
+                msg_write(val);
+                if (usermode) msg_write("\r\n"); else msg_write("\n");
+            }
+
+            LED1 = 0;
+            if (!usermode) msg_write("END\n");
+
+        }else
+        if (cmd == '0')
+        {
+            drive_OW_low();
+            if (usermode)
+                msg_write("\rBUS low\r\n");
+            else
+                msg_write("LOW\n");
+        }else
+        if (cmd == '1')
+        {
+            drive_OW_high();
+            if (usermode) 
+                msg_write("\rBUS high\r\n");
+            else
+                msg_write("HIGH\n");
+        }else
+        if (cmd == '3')
+        {
+            float_OW();
+            if (usermode)
+                msg_write("\rBUS to tri-state\r\n");
+            else
+                msg_write("TRISTATE\n");
+        }else
+        if (cmd == '!')
+        {
+            // this is to test that the watchdog actually works
+            msg_write("Play dead.\r\n");
+            while (1) { NOP(); }
+        }else
+        if (cmd == '?')
+        {
+            bool line = read_OW();
+            if (line) {
+                if (usermode) msg_write("\rBUS HIGH\r\n");
+                else
+                    msg_write("HIGH\n");
+            } else {
+                if (usermode) msg_write("\rBUS LOW\r\n");
+                else msg_write("LOW\n");
+            }
+        }else
+        if (cmd == 'b' || cmd == 'B')
+        {
+            // Read Vdd by sampling FVR
+            FVRCONbits.ADFVR = 0b10;    // 2.048v // 1.024v
+            FVRCONbits.FVREN = 1;       // enable
+            while (!FVRCONbits.FVRRDY) {};
+            ADCON1bits.ADFM = 1;        // right justify
+            ADCON0bits.CHS = 0b11111;   // FVR input
+            ADCON1bits.ADPREF = 0b00;   // +ve ref Vdd
+            ADCON0bits.ADON = 1;        // enable ADC
+
+            ADCON0bits.GO = 1;          // start conversion
+            while (ADCON0bits.GO) {};   // wait til finished
+
+            uint16_t volt = 0;
+            volt = (ADRESH << 8) | ADRESL;
+            uint16_t mv = (8192 / volt) * 1024;
+            mv /= 8;
+
+            msg_write("VOLTAGE ");
+            char val[3];
+            tohex(val, ADRESH);
+            msg_write(val);
+            tohex(val, ADRESL);
+            msg_write(val);
+            msg_write("\n");
+            
+            ADCON0bits.ADON = 0;        // turn off ADC
+            FVRCONbits.FVREN = 0;       // turn of FVR
+        }else
+        {
+            if (usermode) {
+                msg_write("ERROR Press H for Help\n");
+            } else {
+                msg_write("\rERROR Unknown command '");
+                msg_writebyte(cmd);
+                msg_write("' Press 'H' for help.\r\n");
+            }
+        }
+
+        if (usermode) msg_write(prompt);
+    }
+}
+
+/* make a hex string from a value
+ * expect 3 char array */
+void tohex(char val[], uint8_t i)
+{
+    char bt = i >> 4;
+    if (bt > 9)
+        val[0] = 'A' + (bt - 10);
+    else
+        val[0] = '0' + bt;
+    bt = i & 0x0F;
+    if (bt > 9)
+        val[1] = 'A' + (bt - 10);
+    else
+        val[1] = '0' + bt;
+    val[2] = 0;
+}
+
+
+/* is the queue empty yet */
+bool msg_empty(void)
+{
+    if (outp == 0) return 1;
+    return 0;
+}
+
+/* new message in the queue */
+void msg_write(const char *msg)
+{
+    char * p = outbuff + outlen;
+    while (outlen < sizeof(outbuff) && *msg != 0) {
+        *(p++) = *(msg++);
+        outlen++;
+    }
+    *p = 0;
+    if (outp == 0) {
+        outp = outbuff;
+        PIE1bits.TXIE = 1;
+    }
+}
+
+void msg_writebyte(const char msg)
+{
+    if (outlen+1 >= (uint8_t)sizeof(outbuff)) return;
+    outbuff[outlen++] = msg;
+    outbuff[outlen] = 0;
+    if (outp == 0) {
+        outp = outbuff;
+        PIE1bits.TXIE = 1;
+    }
+}
+
+void putch(char data)
+{
+    msg_writebyte(data);
+}
+
+/* called from interrupt routine to send next char */
+void msg_sendnext(void)
+{
+    /* we have finished, turn off the iterrupt */
+    if (outp == 0 || *outp == 0) {
+        PIE1bits.TXIE = 0;
+        outp = 0;
+        outlen = 0;
+        return;
+    }
+    TXREG = *outp;
+    outp++;
+}
+
+/* called from interrupt routine to receive next byte */
+void msg_recvnext(void)
+{
+    while (PIR1bits.RCIF) {
+        bool err = RCSTAbits.FERR;
+        char new = RCREG;
+
+        /* bad char, skip it */
+        if (err) continue;
+
+        /* our input buffer has overflowed */
+        if (inlen > sizeof(inbuff)) return;
+
+        /* keep this one */
+        inbuff[inlen++] = new;
+    }
+}
+
+bool msg_recvready(void)
+{
+    if (inlen > 0) return 1;
+    return 0;
+}
+
+char msg_recv(void)
+{
+    if (inlen == 0) return 0;
+
+    /* record and disable the interupt */
+    bool in = PIE1bits.RCIE;
+    PIE1bits.RCIE = 0;
+
+    char new = inbuff[0];
+    inlen--;
+
+    /* shuffle them down one */
+    for (char i=0;i<inlen;i++)
+        inbuff[i] = inbuff[i+1];
+
+    /* restore the interupt */
+    PIE1bits.RCIE = in;
+    return new;
+}
+
+
+void int_disable(void)
+{
+    INTCONbits.GIE = 0;
+}
+
+void int_enable(void)
+{
+    INTCONbits.GIE = 1;
+}

diff --git a/nbproject/.cvsignore b/nbproject/.cvsignore
new file mode 100644 (file)
index 0000000..3e18ebf
--- /dev/null
+++ b/nbproject/.cvsignore
@@ -0,0 +1 @@
+private

diff --git a/nbproject/Makefile-XC8_12F1822.mk b/nbproject/Makefile-XC8_12F1822.mk
new file mode 100644 (file)
index 0000000..e09dbd3
--- /dev/null
+++ b/nbproject/Makefile-XC8_12F1822.mk
@@ -0,0 +1,202 @@
+#
+# Generated Makefile - do not edit!
+#
+# Edit the Makefile in the project folder instead (../Makefile). Each target
+# has a -pre and a -post target defined where you can add customized code.
+#
+# This makefile implements configuration specific macros and targets.
+
+
+# Include project Makefile
+ifeq "${IGNORE_LOCAL}" "TRUE"
+# do not include local makefile. User is passing all local related variables already
+else
+include Makefile
+# Include makefile containing local settings
+ifeq "$(wildcard nbproject/Makefile-local-XC8_12F1822.mk)" "nbproject/Makefile-local-XC8_12F1822.mk"
+include nbproject/Makefile-local-XC8_12F1822.mk
+endif
+endif
+
+# Environment
+MKDIR=mkdir -p
+RM=rm -f 
+MV=mv 
+CP=cp 
+
+# Macros
+CND_CONF=XC8_12F1822
+ifeq ($(TYPE_IMAGE), DEBUG_RUN)
+IMAGE_TYPE=debug
+OUTPUT_SUFFIX=cof
+DEBUGGABLE_SUFFIX=cof
+FINAL_IMAGE=dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+else
+IMAGE_TYPE=production
+OUTPUT_SUFFIX=hex
+DEBUGGABLE_SUFFIX=cof
+FINAL_IMAGE=dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+endif
+
+# Object Directory
+OBJECTDIR=build/${CND_CONF}/${IMAGE_TYPE}
+
+# Distribution Directory
+DISTDIR=dist/${CND_CONF}/${IMAGE_TYPE}
+
+# Object Files Quoted if spaced
+OBJECTFILES_QUOTED_IF_SPACED=${OBJECTDIR}/configuration_bits.p1 ${OBJECTDIR}/interrupts.p1 ${OBJECTDIR}/main.p1 ${OBJECTDIR}/system.p1 ${OBJECTDIR}/user.p1 ${OBJECTDIR}/onewire.p1
+POSSIBLE_DEPFILES=${OBJECTDIR}/configuration_bits.p1.d ${OBJECTDIR}/interrupts.p1.d ${OBJECTDIR}/main.p1.d ${OBJECTDIR}/system.p1.d ${OBJECTDIR}/user.p1.d ${OBJECTDIR}/onewire.p1.d
+
+# Object Files
+OBJECTFILES=${OBJECTDIR}/configuration_bits.p1 ${OBJECTDIR}/interrupts.p1 ${OBJECTDIR}/main.p1 ${OBJECTDIR}/system.p1 ${OBJECTDIR}/user.p1 ${OBJECTDIR}/onewire.p1
+
+
+CFLAGS=
+ASFLAGS=
+LDLIBSOPTIONS=
+
+############# Tool locations ##########################################
+# If you copy a project from one host to another, the path where the  #
+# compiler is installed may be different.                             #
+# If you open this project with MPLAB X in the new host, this         #
+# makefile will be regenerated and the paths will be corrected.       #
+#######################################################################
+# fixDeps replaces a bunch of sed/cat/printf statements that slow down the build
+FIXDEPS=fixDeps
+
+.build-conf:  ${BUILD_SUBPROJECTS}
+       ${MAKE}  -f nbproject/Makefile-XC8_12F1822.mk dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+
+MP_PROCESSOR_OPTION=12F1822
+# ------------------------------------------------------------------------------------
+# Rules for buildStep: compile
+ifeq ($(TYPE_IMAGE), DEBUG_RUN)
+${OBJECTDIR}/configuration_bits.p1: configuration_bits.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/configuration_bits.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/configuration_bits.p1  configuration_bits.c 
+       @-${MV} ${OBJECTDIR}/configuration_bits.d ${OBJECTDIR}/configuration_bits.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/configuration_bits.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/interrupts.p1: interrupts.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/interrupts.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/interrupts.p1  interrupts.c 
+       @-${MV} ${OBJECTDIR}/interrupts.d ${OBJECTDIR}/interrupts.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/interrupts.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/main.p1: main.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/main.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/main.p1  main.c 
+       @-${MV} ${OBJECTDIR}/main.d ${OBJECTDIR}/main.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/main.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/system.p1: system.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/system.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/system.p1  system.c 
+       @-${MV} ${OBJECTDIR}/system.d ${OBJECTDIR}/system.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/system.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/user.p1: user.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/user.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/user.p1  user.c 
+       @-${MV} ${OBJECTDIR}/user.d ${OBJECTDIR}/user.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/user.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/onewire.p1: onewire.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/onewire.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/onewire.p1  onewire.c 
+       @-${MV} ${OBJECTDIR}/onewire.d ${OBJECTDIR}/onewire.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/onewire.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+else
+${OBJECTDIR}/configuration_bits.p1: configuration_bits.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/configuration_bits.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/configuration_bits.p1  configuration_bits.c 
+       @-${MV} ${OBJECTDIR}/configuration_bits.d ${OBJECTDIR}/configuration_bits.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/configuration_bits.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/interrupts.p1: interrupts.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/interrupts.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/interrupts.p1  interrupts.c 
+       @-${MV} ${OBJECTDIR}/interrupts.d ${OBJECTDIR}/interrupts.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/interrupts.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/main.p1: main.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/main.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/main.p1  main.c 
+       @-${MV} ${OBJECTDIR}/main.d ${OBJECTDIR}/main.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/main.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/system.p1: system.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/system.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/system.p1  system.c 
+       @-${MV} ${OBJECTDIR}/system.d ${OBJECTDIR}/system.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/system.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/user.p1: user.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/user.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/user.p1  user.c 
+       @-${MV} ${OBJECTDIR}/user.d ${OBJECTDIR}/user.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/user.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/onewire.p1: onewire.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/onewire.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/onewire.p1  onewire.c 
+       @-${MV} ${OBJECTDIR}/onewire.d ${OBJECTDIR}/onewire.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/onewire.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+endif
+
+# ------------------------------------------------------------------------------------
+# Rules for buildStep: assemble
+ifeq ($(TYPE_IMAGE), DEBUG_RUN)
+else
+endif
+
+# ------------------------------------------------------------------------------------
+# Rules for buildStep: link
+ifeq ($(TYPE_IMAGE), DEBUG_RUN)
+dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES}  nbproject/Makefile-${CND_CONF}.mk    
+       @${MKDIR} dist/${CND_CONF}/${IMAGE_TYPE} 
+       ${MP_CC} $(MP_EXTRA_LD_PRE) --chip=$(MP_PROCESSOR_OPTION) -G --asmlist -mdist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.map  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"      -odist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX}  ${OBJECTFILES_QUOTED_IF_SPACED}     
+       @${RM} dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.hex 
+       
+else
+dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES}  nbproject/Makefile-${CND_CONF}.mk   
+       @${MKDIR} dist/${CND_CONF}/${IMAGE_TYPE} 
+       ${MP_CC} $(MP_EXTRA_LD_PRE) --chip=$(MP_PROCESSOR_OPTION) -G --asmlist -mdist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.map  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"   -odist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX}  ${OBJECTFILES_QUOTED_IF_SPACED}     
+       
+endif
+
+
+# Subprojects
+.build-subprojects:
+
+
+# Subprojects
+.clean-subprojects:
+
+# Clean Targets
+.clean-conf: ${CLEAN_SUBPROJECTS}
+       ${RM} -r build/XC8_12F1822
+       ${RM} -r dist/XC8_12F1822
+
+# Enable dependency checking
+.dep.inc: .depcheck-impl
+
+DEPFILES=$(shell "${PATH_TO_IDE_BIN}"mplabwildcard ${POSSIBLE_DEPFILES})
+ifneq (${DEPFILES},)
+include ${DEPFILES}
+endif

diff --git a/nbproject/Makefile-XC8_12F1840.mk b/nbproject/Makefile-XC8_12F1840.mk
new file mode 100644 (file)
index 0000000..cef98f6
--- /dev/null
+++ b/nbproject/Makefile-XC8_12F1840.mk
@@ -0,0 +1,202 @@
+#
+# Generated Makefile - do not edit!
+#
+# Edit the Makefile in the project folder instead (../Makefile). Each target
+# has a -pre and a -post target defined where you can add customized code.
+#
+# This makefile implements configuration specific macros and targets.
+
+
+# Include project Makefile
+ifeq "${IGNORE_LOCAL}" "TRUE"
+# do not include local makefile. User is passing all local related variables already
+else
+include Makefile
+# Include makefile containing local settings
+ifeq "$(wildcard nbproject/Makefile-local-XC8_12F1840.mk)" "nbproject/Makefile-local-XC8_12F1840.mk"
+include nbproject/Makefile-local-XC8_12F1840.mk
+endif
+endif
+
+# Environment
+MKDIR=mkdir -p
+RM=rm -f 
+MV=mv 
+CP=cp 
+
+# Macros
+CND_CONF=XC8_12F1840
+ifeq ($(TYPE_IMAGE), DEBUG_RUN)
+IMAGE_TYPE=debug
+OUTPUT_SUFFIX=cof
+DEBUGGABLE_SUFFIX=cof
+FINAL_IMAGE=dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+else
+IMAGE_TYPE=production
+OUTPUT_SUFFIX=hex
+DEBUGGABLE_SUFFIX=cof
+FINAL_IMAGE=dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+endif
+
+# Object Directory
+OBJECTDIR=build/${CND_CONF}/${IMAGE_TYPE}
+
+# Distribution Directory
+DISTDIR=dist/${CND_CONF}/${IMAGE_TYPE}
+
+# Object Files Quoted if spaced
+OBJECTFILES_QUOTED_IF_SPACED=${OBJECTDIR}/configuration_bits.p1 ${OBJECTDIR}/interrupts.p1 ${OBJECTDIR}/main.p1 ${OBJECTDIR}/system.p1 ${OBJECTDIR}/user.p1 ${OBJECTDIR}/onewire.p1
+POSSIBLE_DEPFILES=${OBJECTDIR}/configuration_bits.p1.d ${OBJECTDIR}/interrupts.p1.d ${OBJECTDIR}/main.p1.d ${OBJECTDIR}/system.p1.d ${OBJECTDIR}/user.p1.d ${OBJECTDIR}/onewire.p1.d
+
+# Object Files
+OBJECTFILES=${OBJECTDIR}/configuration_bits.p1 ${OBJECTDIR}/interrupts.p1 ${OBJECTDIR}/main.p1 ${OBJECTDIR}/system.p1 ${OBJECTDIR}/user.p1 ${OBJECTDIR}/onewire.p1
+
+
+CFLAGS=
+ASFLAGS=
+LDLIBSOPTIONS=
+
+############# Tool locations ##########################################
+# If you copy a project from one host to another, the path where the  #
+# compiler is installed may be different.                             #
+# If you open this project with MPLAB X in the new host, this         #
+# makefile will be regenerated and the paths will be corrected.       #
+#######################################################################
+# fixDeps replaces a bunch of sed/cat/printf statements that slow down the build
+FIXDEPS=fixDeps
+
+.build-conf:  ${BUILD_SUBPROJECTS}
+       ${MAKE}  -f nbproject/Makefile-XC8_12F1840.mk dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+
+MP_PROCESSOR_OPTION=12F1840
+# ------------------------------------------------------------------------------------
+# Rules for buildStep: compile
+ifeq ($(TYPE_IMAGE), DEBUG_RUN)
+${OBJECTDIR}/configuration_bits.p1: configuration_bits.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/configuration_bits.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/configuration_bits.p1  configuration_bits.c 
+       @-${MV} ${OBJECTDIR}/configuration_bits.d ${OBJECTDIR}/configuration_bits.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/configuration_bits.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/interrupts.p1: interrupts.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/interrupts.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/interrupts.p1  interrupts.c 
+       @-${MV} ${OBJECTDIR}/interrupts.d ${OBJECTDIR}/interrupts.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/interrupts.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/main.p1: main.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/main.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/main.p1  main.c 
+       @-${MV} ${OBJECTDIR}/main.d ${OBJECTDIR}/main.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/main.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/system.p1: system.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/system.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/system.p1  system.c 
+       @-${MV} ${OBJECTDIR}/system.d ${OBJECTDIR}/system.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/system.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/user.p1: user.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/user.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/user.p1  user.c 
+       @-${MV} ${OBJECTDIR}/user.d ${OBJECTDIR}/user.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/user.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/onewire.p1: onewire.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/onewire.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/onewire.p1  onewire.c 
+       @-${MV} ${OBJECTDIR}/onewire.d ${OBJECTDIR}/onewire.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/onewire.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+else
+${OBJECTDIR}/configuration_bits.p1: configuration_bits.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/configuration_bits.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/configuration_bits.p1  configuration_bits.c 
+       @-${MV} ${OBJECTDIR}/configuration_bits.d ${OBJECTDIR}/configuration_bits.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/configuration_bits.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/interrupts.p1: interrupts.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/interrupts.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/interrupts.p1  interrupts.c 
+       @-${MV} ${OBJECTDIR}/interrupts.d ${OBJECTDIR}/interrupts.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/interrupts.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/main.p1: main.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/main.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/main.p1  main.c 
+       @-${MV} ${OBJECTDIR}/main.d ${OBJECTDIR}/main.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/main.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/system.p1: system.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/system.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/system.p1  system.c 
+       @-${MV} ${OBJECTDIR}/system.d ${OBJECTDIR}/system.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/system.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/user.p1: user.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/user.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/user.p1  user.c 
+       @-${MV} ${OBJECTDIR}/user.d ${OBJECTDIR}/user.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/user.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+${OBJECTDIR}/onewire.p1: onewire.c  nbproject/Makefile-${CND_CONF}.mk
+       @${MKDIR} ${OBJECTDIR} 
+       @${RM} ${OBJECTDIR}/onewire.p1.d 
+       ${MP_CC} --pass1 $(MP_EXTRA_CC_PRE) --chip=$(MP_PROCESSOR_OPTION) -Q -G --asmlist  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"  -o${OBJECTDIR}/onewire.p1  onewire.c 
+       @-${MV} ${OBJECTDIR}/onewire.d ${OBJECTDIR}/onewire.p1.d 
+       @${FIXDEPS} ${OBJECTDIR}/onewire.p1.d $(SILENT) -rsi ${MP_CC_DIR}../  
+       
+endif
+
+# ------------------------------------------------------------------------------------
+# Rules for buildStep: assemble
+ifeq ($(TYPE_IMAGE), DEBUG_RUN)
+else
+endif
+
+# ------------------------------------------------------------------------------------
+# Rules for buildStep: link
+ifeq ($(TYPE_IMAGE), DEBUG_RUN)
+dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES}  nbproject/Makefile-${CND_CONF}.mk    
+       @${MKDIR} dist/${CND_CONF}/${IMAGE_TYPE} 
+       ${MP_CC} $(MP_EXTRA_LD_PRE) --chip=$(MP_PROCESSOR_OPTION) -G --asmlist -mdist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.map  -D__DEBUG=1 --debugger=pickit2  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"      -odist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX}  ${OBJECTFILES_QUOTED_IF_SPACED}     
+       @${RM} dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.hex 
+       
+else
+dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES}  nbproject/Makefile-${CND_CONF}.mk   
+       @${MKDIR} dist/${CND_CONF}/${IMAGE_TYPE} 
+       ${MP_CC} $(MP_EXTRA_LD_PRE) --chip=$(MP_PROCESSOR_OPTION) -G --asmlist -mdist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.map  --double=24 --float=24 --opt=default,+asm,-asmfile,+speed,-space,-debug --addrqual=ignore --mode=free -P -N255 --warn=0 --summary=default,-psect,-class,+mem,-hex,-file --output=default,-inhx032 --runtime=default,+clear,+init,-keep,-no_startup,+osccal,-resetbits,-download,-stackcall,+clib "--errformat=%f:%l: error: %s" "--warnformat=%f:%l: warning: %s" "--msgformat=%f:%l: advisory: %s"   -odist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX}  ${OBJECTFILES_QUOTED_IF_SPACED}     
+       
+endif
+
+
+# Subprojects
+.build-subprojects:
+
+
+# Subprojects
+.clean-subprojects:
+
+# Clean Targets
+.clean-conf: ${CLEAN_SUBPROJECTS}
+       ${RM} -r build/XC8_12F1840
+       ${RM} -r dist/XC8_12F1840
+
+# Enable dependency checking
+.dep.inc: .depcheck-impl
+
+DEPFILES=$(shell "${PATH_TO_IDE_BIN}"mplabwildcard ${POSSIBLE_DEPFILES})
+ifneq (${DEPFILES},)
+include ${DEPFILES}
+endif

diff --git a/nbproject/Makefile-genesis.properties b/nbproject/Makefile-genesis.properties
new file mode 100644 (file)
index 0000000..c8778ec
--- /dev/null
+++ b/nbproject/Makefile-genesis.properties
@@ -0,0 +1,11 @@
+#
+#Tue Sep 24 10:40:20 BST 2013
+XC8_12F1822.languagetoolchain.version=1.12
+conf.ids=XC8_12F1840,XC8_12F1822
+XC8_12F1840.languagetoolchain.dir=/opt/microchip/xc8/v1.12/bin
+XC8_12F1822.com-microchip-mplab-nbide-toolchainXC8-XC8LanguageToolchain.md5=6d5a9f45bfc5514a8b0e6f1cea21c122
+XC8_12F1840.com-microchip-mplab-nbide-toolchainXC8-XC8LanguageToolchain.md5=6d5a9f45bfc5514a8b0e6f1cea21c122
+com-microchip-mplab-nbide-embedded-makeproject-MakeProject.md5=8fe1589514540343a5279c082104bce0
+XC8_12F1822.languagetoolchain.dir=/opt/microchip/xc8/v1.12/bin
+host.platform=linux
+XC8_12F1840.languagetoolchain.version=1.12

diff --git a/nbproject/Makefile-impl.mk b/nbproject/Makefile-impl.mk
new file mode 100644 (file)
index 0000000..291c638
--- /dev/null
+++ b/nbproject/Makefile-impl.mk
@@ -0,0 +1,71 @@
+#
+# Generated Makefile - do not edit!
+#
+# Edit the Makefile in the project folder instead (../Makefile). Each target
+# has a pre- and a post- target defined where you can add customization code.
+#
+# This makefile implements macros and targets common to all configurations.
+#
+# NOCDDL
+
+
+# Building and Cleaning subprojects are done by default, but can be controlled with the SUB
+# macro. If SUB=no, subprojects will not be built or cleaned. The following macro
+# statements set BUILD_SUB-CONF and CLEAN_SUB-CONF to .build-reqprojects-conf
+# and .clean-reqprojects-conf unless SUB has the value 'no'
+SUB_no=NO
+SUBPROJECTS=${SUB_${SUB}}
+BUILD_SUBPROJECTS_=.build-subprojects
+BUILD_SUBPROJECTS_NO=
+BUILD_SUBPROJECTS=${BUILD_SUBPROJECTS_${SUBPROJECTS}}
+CLEAN_SUBPROJECTS_=.clean-subprojects
+CLEAN_SUBPROJECTS_NO=
+CLEAN_SUBPROJECTS=${CLEAN_SUBPROJECTS_${SUBPROJECTS}}
+
+
+# Project Name
+PROJECTNAME=uart test.X
+
+# Active Configuration
+DEFAULTCONF=XC8_12F1840
+CONF=${DEFAULTCONF}
+
+# All Configurations
+ALLCONFS=XC8_12F1840 XC8_12F1822 
+
+
+# build
+.build-impl: .build-pre
+       ${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .build-conf
+
+
+# clean
+.clean-impl: .clean-pre
+       ${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .clean-conf
+
+# clobber
+.clobber-impl: .clobber-pre .depcheck-impl
+           ${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=XC8_12F1840 clean
+           ${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=XC8_12F1822 clean
+
+
+
+# all
+.all-impl: .all-pre .depcheck-impl
+           ${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=XC8_12F1840 build
+           ${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=XC8_12F1822 build
+
+
+
+# dependency checking support
+.depcheck-impl:
+#      @echo "# This code depends on make tool being used" >.dep.inc
+#      @if [ -n "${MAKE_VERSION}" ]; then \
+#          echo "DEPFILES=\$$(wildcard \$$(addsuffix .d, \$${OBJECTFILES}))" >>.dep.inc; \
+#          echo "ifneq (\$${DEPFILES},)" >>.dep.inc; \
+#          echo "include \$${DEPFILES}" >>.dep.inc; \
+#          echo "endif" >>.dep.inc; \
+#      else \
+#          echo ".KEEP_STATE:" >>.dep.inc; \
+#          echo ".KEEP_STATE_FILE:.make.state.\$${CONF}" >>.dep.inc; \
+#      fi

diff --git a/nbproject/Makefile-local-XC8_12F1822.mk b/nbproject/Makefile-local-XC8_12F1822.mk
new file mode 100644 (file)
index 0000000..edae0e0
--- /dev/null
+++ b/nbproject/Makefile-local-XC8_12F1822.mk
@@ -0,0 +1,36 @@
+#
+# Generated Makefile - do not edit!
+#
+#
+# This file contains information about the location of compilers and other tools.
+# If you commmit this file into your revision control server, you will be able to 
+# to checkout the project and build it from the command line with make. However,
+# if more than one person works on the same project, then this file might show
+# conflicts since different users are bound to have compilers in different places.
+# In that case you might choose to not commit this file and let MPLAB X recreate this file
+# for each user. The disadvantage of not commiting this file is that you must run MPLAB X at
+# least once so the file gets created and the project can be built. Finally, you can also
+# avoid using this file at all if you are only building from the command line with make.
+# You can invoke make with the values of the macros:
+# $ makeMP_CC="/opt/microchip/mplabc30/v3.30c/bin/pic30-gcc" ...  
+#
+PATH_TO_IDE_BIN=/opt/microchip/mplabx/mplab_ide/mplab_ide/modules/../../bin/
+# Adding MPLAB X bin directory to path.
+PATH:=/opt/microchip/mplabx/mplab_ide/mplab_ide/modules/../../bin/:$(PATH)
+# Path to java used to run MPLAB X when this makefile was created
+MP_JAVA_PATH="/opt/microchip/mplabx/sys/java/jre1.7.0_17/bin/"
+OS_CURRENT="$(shell uname -s)"
+MP_CC="/opt/microchip/xc8/v1.12/bin/xc8"
+# MP_CPPC is not defined
+# MP_BC is not defined
+# MP_AS is not defined
+# MP_LD is not defined
+# MP_AR is not defined
+DEP_GEN=${MP_JAVA_PATH}java -jar "/opt/microchip/mplabx/mplab_ide/mplab_ide/modules/../../bin/extractobjectdependencies.jar" 
+MP_CC_DIR="/opt/microchip/xc8/v1.12/bin"
+# MP_CPPC_DIR is not defined
+# MP_BC_DIR is not defined
+# MP_AS_DIR is not defined
+# MP_LD_DIR is not defined
+# MP_AR_DIR is not defined
+# MP_BC_DIR is not defined

diff --git a/nbproject/Makefile-local-XC8_12F1840.mk b/nbproject/Makefile-local-XC8_12F1840.mk
new file mode 100644 (file)
index 0000000..edae0e0
--- /dev/null
+++ b/nbproject/Makefile-local-XC8_12F1840.mk
@@ -0,0 +1,36 @@
+#
+# Generated Makefile - do not edit!
+#
+#
+# This file contains information about the location of compilers and other tools.
+# If you commmit this file into your revision control server, you will be able to 
+# to checkout the project and build it from the command line with make. However,
+# if more than one person works on the same project, then this file might show
+# conflicts since different users are bound to have compilers in different places.
+# In that case you might choose to not commit this file and let MPLAB X recreate this file
+# for each user. The disadvantage of not commiting this file is that you must run MPLAB X at
+# least once so the file gets created and the project can be built. Finally, you can also
+# avoid using this file at all if you are only building from the command line with make.
+# You can invoke make with the values of the macros:
+# $ makeMP_CC="/opt/microchip/mplabc30/v3.30c/bin/pic30-gcc" ...  
+#
+PATH_TO_IDE_BIN=/opt/microchip/mplabx/mplab_ide/mplab_ide/modules/../../bin/
+# Adding MPLAB X bin directory to path.
+PATH:=/opt/microchip/mplabx/mplab_ide/mplab_ide/modules/../../bin/:$(PATH)
+# Path to java used to run MPLAB X when this makefile was created
+MP_JAVA_PATH="/opt/microchip/mplabx/sys/java/jre1.7.0_17/bin/"
+OS_CURRENT="$(shell uname -s)"
+MP_CC="/opt/microchip/xc8/v1.12/bin/xc8"
+# MP_CPPC is not defined
+# MP_BC is not defined
+# MP_AS is not defined
+# MP_LD is not defined
+# MP_AR is not defined
+DEP_GEN=${MP_JAVA_PATH}java -jar "/opt/microchip/mplabx/mplab_ide/mplab_ide/modules/../../bin/extractobjectdependencies.jar" 
+MP_CC_DIR="/opt/microchip/xc8/v1.12/bin"
+# MP_CPPC_DIR is not defined
+# MP_BC_DIR is not defined
+# MP_AS_DIR is not defined
+# MP_LD_DIR is not defined
+# MP_AR_DIR is not defined
+# MP_BC_DIR is not defined

diff --git a/nbproject/Makefile-variables.mk b/nbproject/Makefile-variables.mk
new file mode 100644 (file)
index 0000000..191bf3d
--- /dev/null
+++ b/nbproject/Makefile-variables.mk
@@ -0,0 +1,20 @@
+#
+# Generated - do not edit!
+#
+# NOCDDL
+#
+CND_BASEDIR=`pwd`
+# XC8_12F1840 configuration
+CND_ARTIFACT_DIR_XC8_12F1840=dist/XC8_12F1840/production
+CND_ARTIFACT_NAME_XC8_12F1840=uart_test.X.production.hex
+CND_ARTIFACT_PATH_XC8_12F1840=dist/XC8_12F1840/production/uart_test.X.production.hex
+CND_PACKAGE_DIR_XC8_12F1840=${CND_DISTDIR}/XC8_12F1840/package
+CND_PACKAGE_NAME_XC8_12F1840=uarttest.x.tar
+CND_PACKAGE_PATH_XC8_12F1840=${CND_DISTDIR}/XC8_12F1840/package/uarttest.x.tar
+# XC8_12F1822 configuration
+CND_ARTIFACT_DIR_XC8_12F1822=dist/XC8_12F1822/production
+CND_ARTIFACT_NAME_XC8_12F1822=uart_test.X.production.hex
+CND_ARTIFACT_PATH_XC8_12F1822=dist/XC8_12F1822/production/uart_test.X.production.hex
+CND_PACKAGE_DIR_XC8_12F1822=${CND_DISTDIR}/XC8_12F1822/package
+CND_PACKAGE_NAME_XC8_12F1822=uarttest.x.tar
+CND_PACKAGE_PATH_XC8_12F1822=${CND_DISTDIR}/XC8_12F1822/package/uarttest.x.tar

diff --git a/nbproject/Package-XC8_12F1822.bash b/nbproject/Package-XC8_12F1822.bash
new file mode 100644 (file)
index 0000000..1e3716c
--- /dev/null
+++ b/nbproject/Package-XC8_12F1822.bash
@@ -0,0 +1,73 @@
+#!/bin/bash -x
+
+#
+# Generated - do not edit!
+#
+
+# Macros
+TOP=`pwd`
+CND_CONF=XC8_12F1822
+CND_DISTDIR=dist
+TMPDIR=build/${CND_CONF}/${IMAGE_TYPE}/tmp-packaging
+TMPDIRNAME=tmp-packaging
+OUTPUT_PATH=dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+OUTPUT_BASENAME=uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+PACKAGE_TOP_DIR=uarttest.x/
+
+# Functions
+function checkReturnCode
+{
+    rc=$?
+    if [ $rc != 0 ]
+    then
+        exit $rc
+    fi
+}
+function makeDirectory
+# $1 directory path
+# $2 permission (optional)
+{
+    mkdir -p "$1"
+    checkReturnCode
+    if [ "$2" != "" ]
+    then
+      chmod $2 "$1"
+      checkReturnCode
+    fi
+}
+function copyFileToTmpDir
+# $1 from-file path
+# $2 to-file path
+# $3 permission
+{
+    cp "$1" "$2"
+    checkReturnCode
+    if [ "$3" != "" ]
+    then
+        chmod $3 "$2"
+        checkReturnCode
+    fi
+}
+
+# Setup
+cd "${TOP}"
+mkdir -p ${CND_DISTDIR}/${CND_CONF}/package
+rm -rf ${TMPDIR}
+mkdir -p ${TMPDIR}
+
+# Copy files and create directories and links
+cd "${TOP}"
+makeDirectory ${TMPDIR}/uarttest.x/bin
+copyFileToTmpDir "${OUTPUT_PATH}" "${TMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755
+
+
+# Generate tar file
+cd "${TOP}"
+rm -f ${CND_DISTDIR}/${CND_CONF}/package/uarttest.x.tar
+cd ${TMPDIR}
+tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/package/uarttest.x.tar *
+checkReturnCode
+
+# Cleanup
+cd "${TOP}"
+rm -rf ${TMPDIR}

diff --git a/nbproject/Package-XC8_12F1840.bash b/nbproject/Package-XC8_12F1840.bash
new file mode 100644 (file)
index 0000000..04bae04
--- /dev/null
+++ b/nbproject/Package-XC8_12F1840.bash
@@ -0,0 +1,73 @@
+#!/bin/bash -x
+
+#
+# Generated - do not edit!
+#
+
+# Macros
+TOP=`pwd`
+CND_CONF=XC8_12F1840
+CND_DISTDIR=dist
+TMPDIR=build/${CND_CONF}/${IMAGE_TYPE}/tmp-packaging
+TMPDIRNAME=tmp-packaging
+OUTPUT_PATH=dist/${CND_CONF}/${IMAGE_TYPE}/uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+OUTPUT_BASENAME=uart_test.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
+PACKAGE_TOP_DIR=uarttest.x/
+
+# Functions
+function checkReturnCode
+{
+    rc=$?
+    if [ $rc != 0 ]
+    then
+        exit $rc
+    fi
+}
+function makeDirectory
+# $1 directory path
+# $2 permission (optional)
+{
+    mkdir -p "$1"
+    checkReturnCode
+    if [ "$2" != "" ]
+    then
+      chmod $2 "$1"
+      checkReturnCode
+    fi
+}
+function copyFileToTmpDir
+# $1 from-file path
+# $2 to-file path
+# $3 permission
+{
+    cp "$1" "$2"
+    checkReturnCode
+    if [ "$3" != "" ]
+    then
+        chmod $3 "$2"
+        checkReturnCode
+    fi
+}
+
+# Setup
+cd "${TOP}"
+mkdir -p ${CND_DISTDIR}/${CND_CONF}/package
+rm -rf ${TMPDIR}
+mkdir -p ${TMPDIR}
+
+# Copy files and create directories and links
+cd "${TOP}"
+makeDirectory ${TMPDIR}/uarttest.x/bin
+copyFileToTmpDir "${OUTPUT_PATH}" "${TMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755
+
+
+# Generate tar file
+cd "${TOP}"
+rm -f ${CND_DISTDIR}/${CND_CONF}/package/uarttest.x.tar
+cd ${TMPDIR}
+tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/package/uarttest.x.tar *
+checkReturnCode
+
+# Cleanup
+cd "${TOP}"
+rm -rf ${TMPDIR}

diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml
new file mode 100644 (file)
index 0000000..bc0f055
--- /dev/null
+++ b/nbproject/configurations.xml
@@ -0,0 +1,228 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<configurationDescriptor version="62">
+  <logicalFolder name="root" displayName="root" projectFiles="true">
+    <logicalFolder name="HeaderFiles"
+                   displayName="Header Files"
+                   projectFiles="true">
+      <itemPath>system.h</itemPath>
+      <itemPath>user.h</itemPath>
+      <itemPath>onewire.h</itemPath>
+    </logicalFolder>
+    <logicalFolder name="SourceFiles"
+                   displayName="Source Files"
+                   projectFiles="true">
+      <itemPath>configuration_bits.c</itemPath>
+      <itemPath>interrupts.c</itemPath>
+      <itemPath>main.c</itemPath>
+      <itemPath>system.c</itemPath>
+      <itemPath>user.c</itemPath>
+      <itemPath>onewire.c</itemPath>
+    </logicalFolder>
+    <logicalFolder name="ExternalFiles"
+                   displayName="Important Files"
+                   projectFiles="false">
+      <itemPath>Makefile</itemPath>
+    </logicalFolder>
+    <itemPath>getting_started.txt</itemPath>
+    <itemPath>legal_disclaimer.txt</itemPath>
+    <itemPath>project_information.txt</itemPath>
+  </logicalFolder>
+  <projectmakefile>Makefile</projectmakefile>
+  <confs>
+    <conf name="XC8_12F1840" type="2">
+      <toolsSet>
+        <developmentServer>localhost</developmentServer>
+        <targetDevice>PIC12F1840</targetDevice>
+        <targetHeader></targetHeader>
+        <targetPluginBoard></targetPluginBoard>
+        <platformTool>PICkit2PlatformTool</platformTool>
+        <languageToolchain>XC8</languageToolchain>
+        <languageToolchainVersion>1.12</languageToolchainVersion>
+        <platform>2</platform>
+      </toolsSet>
+      <compileType>
+        <linkerTool>
+          <linkerLibItems>
+          </linkerLibItems>
+        </linkerTool>
+        <loading>
+          <useAlternateLoadableFile>false</useAlternateLoadableFile>
+          <alternateLoadableFile></alternateLoadableFile>
+        </loading>
+      </compileType>
+      <makeCustomizationType>
+        <makeCustomizationPreStepEnabled>false</makeCustomizationPreStepEnabled>
+        <makeCustomizationPreStep></makeCustomizationPreStep>
+        <makeCustomizationPostStepEnabled>false</makeCustomizationPostStepEnabled>
+        <makeCustomizationPostStep></makeCustomizationPostStep>
+        <makeCustomizationPutChecksumInUserID>false</makeCustomizationPutChecksumInUserID>
+        <makeCustomizationEnableLongLines>false</makeCustomizationEnableLongLines>
+        <makeCustomizationNormalizeHexFile>false</makeCustomizationNormalizeHexFile>
+      </makeCustomizationType>
+      <HI-TECH-COMP>
+        <property key="define-macros" value=""/>
+        <property key="extra-include-directories" value=""/>
+        <property key="identifier-length" value="255"/>
+        <property key="operation-mode" value="free"/>
+        <property key="opt-xc8-compiler-strict_ansi" value="false"/>
+        <property key="optimization-assembler" value="true"/>
+        <property key="optimization-assembler-files" value="false"/>
+        <property key="optimization-debug" value="false"/>
+        <property key="optimization-global" value="true"/>
+        <property key="optimization-level" value="9"/>
+        <property key="optimization-set" value="default"/>
+        <property key="optimization-speed" value="true"/>
+        <property key="preprocess-assembler" value="true"/>
+        <property key="undefine-macros" value=""/>
+        <property key="use-cci" value="false"/>
+        <property key="verbose" value="false"/>
+        <property key="warning-level" value="0"/>
+        <property key="what-to-do" value="ignore"/>
+      </HI-TECH-COMP>
+      <HI-TECH-LINK>
+        <property key="additional-options-checksum" value=""/>
+        <property key="additional-options-code-offset" value=""/>
+        <property key="additional-options-errata" value=""/>
+        <property key="additional-options-extend-address" value="false"/>
+        <property key="additional-options-trace-type" value=""/>
+        <property key="additional-options-use-response-files" value="false"/>
+        <property key="backup-reset-condition-flags" value="false"/>
+        <property key="calibrate-oscillator" value="true"/>
+        <property key="calibrate-oscillator-value" value=""/>
+        <property key="clear-bss" value="true"/>
+        <property key="code-model-external" value="wordwrite"/>
+        <property key="code-model-rom" value=""/>
+        <property key="create-html-files" value="false"/>
+        <property key="data-model-ram" value=""/>
+        <property key="data-model-size-of-double" value="24"/>
+        <property key="data-model-size-of-float" value="24"/>
+        <property key="display-class-usage" value="false"/>
+        <property key="display-hex-usage" value="false"/>
+        <property key="display-overall-usage" value="true"/>
+        <property key="display-psect-usage" value="false"/>
+        <property key="fill-flash-options-addr" value=""/>
+        <property key="fill-flash-options-const" value=""/>
+        <property key="fill-flash-options-how" value="0"/>
+        <property key="fill-flash-options-inc-const" value="1"/>
+        <property key="fill-flash-options-increment" value=""/>
+        <property key="fill-flash-options-seq" value=""/>
+        <property key="fill-flash-options-what" value="0"/>
+        <property key="format-hex-file-for-download" value="false"/>
+        <property key="initialize-data" value="true"/>
+        <property key="keep-generated-startup.as" value="false"/>
+        <property key="link-in-c-library" value="true"/>
+        <property key="link-in-peripheral-library" value="true"/>
+        <property key="managed-stack" value="false"/>
+        <property key="opt-xc8-linker-file" value="false"/>
+        <property key="opt-xc8-linker-link_startup" value="false"/>
+        <property key="opt-xc8-linker-serial" value=""/>
+        <property key="program-the-device-with-default-config-words" value="true"/>
+      </HI-TECH-LINK>
+      <PICkit2PlatformTool>
+      </PICkit2PlatformTool>
+      <XC8-config-global>
+        <property key="output-file-format" value="-mcof,+elf"/>
+      </XC8-config-global>
+    </conf>
+    <conf name="XC8_12F1822" type="2">
+      <toolsSet>
+        <developmentServer>localhost</developmentServer>
+        <targetDevice>PIC12F1822</targetDevice>
+        <targetHeader></targetHeader>
+        <targetPluginBoard></targetPluginBoard>
+        <platformTool>PICkit2PlatformTool</platformTool>
+        <languageToolchain>XC8</languageToolchain>
+        <languageToolchainVersion>1.12</languageToolchainVersion>
+        <platform>2</platform>
+      </toolsSet>
+      <compileType>
+        <linkerTool>
+          <linkerLibItems>
+          </linkerLibItems>
+        </linkerTool>
+        <loading>
+          <useAlternateLoadableFile>false</useAlternateLoadableFile>
+          <alternateLoadableFile></alternateLoadableFile>
+        </loading>
+      </compileType>
+      <makeCustomizationType>
+        <makeCustomizationPreStepEnabled>false</makeCustomizationPreStepEnabled>
+        <makeCustomizationPreStep></makeCustomizationPreStep>
+        <makeCustomizationPostStepEnabled>false</makeCustomizationPostStepEnabled>
+        <makeCustomizationPostStep></makeCustomizationPostStep>
+        <makeCustomizationPutChecksumInUserID>false</makeCustomizationPutChecksumInUserID>
+        <makeCustomizationEnableLongLines>false</makeCustomizationEnableLongLines>
+        <makeCustomizationNormalizeHexFile>false</makeCustomizationNormalizeHexFile>
+      </makeCustomizationType>
+      <HI-TECH-COMP>
+        <property key="define-macros" value=""/>
+        <property key="extra-include-directories" value=""/>
+        <property key="identifier-length" value="255"/>
+        <property key="operation-mode" value="free"/>
+        <property key="opt-xc8-compiler-strict_ansi" value="false"/>
+        <property key="optimization-assembler" value="true"/>
+        <property key="optimization-assembler-files" value="false"/>
+        <property key="optimization-debug" value="false"/>
+        <property key="optimization-global" value="true"/>
+        <property key="optimization-level" value="9"/>
+        <property key="optimization-set" value="default"/>
+        <property key="optimization-speed" value="true"/>
+        <property key="preprocess-assembler" value="true"/>
+        <property key="undefine-macros" value=""/>
+        <property key="use-cci" value="false"/>
+        <property key="verbose" value="false"/>
+        <property key="warning-level" value="0"/>
+        <property key="what-to-do" value="ignore"/>
+      </HI-TECH-COMP>
+      <HI-TECH-LINK>
+        <property key="additional-options-checksum" value=""/>
+        <property key="additional-options-code-offset" value=""/>
+        <property key="additional-options-errata" value=""/>
+        <property key="additional-options-extend-address" value="false"/>
+        <property key="additional-options-trace-type" value=""/>
+        <property key="additional-options-use-response-files" value="false"/>
+        <property key="backup-reset-condition-flags" value="false"/>
+        <property key="calibrate-oscillator" value="true"/>
+        <property key="calibrate-oscillator-value" value=""/>
+        <property key="clear-bss" value="true"/>
+        <property key="code-model-external" value="wordwrite"/>
+        <property key="code-model-rom" value=""/>
+        <property key="create-html-files" value="false"/>
+        <property key="data-model-ram" value=""/>
+        <property key="data-model-size-of-double" value="24"/>
+        <property key="data-model-size-of-float" value="24"/>
+        <property key="display-class-usage" value="false"/>
+        <property key="display-hex-usage" value="false"/>
+        <property key="display-overall-usage" value="true"/>
+        <property key="display-psect-usage" value="false"/>
+        <property key="fill-flash-options-addr" value=""/>
+        <property key="fill-flash-options-const" value=""/>
+        <property key="fill-flash-options-how" value="0"/>
+        <property key="fill-flash-options-inc-const" value="1"/>
+        <property key="fill-flash-options-increment" value=""/>
+        <property key="fill-flash-options-seq" value=""/>
+        <property key="fill-flash-options-what" value="0"/>
+        <property key="format-hex-file-for-download" value="false"/>
+        <property key="initialize-data" value="true"/>
+        <property key="keep-generated-startup.as" value="false"/>
+        <property key="link-in-c-library" value="true"/>
+        <property key="link-in-peripheral-library" value="true"/>
+        <property key="managed-stack" value="false"/>
+        <property key="opt-xc8-linker-file" value="false"/>
+        <property key="opt-xc8-linker-link_startup" value="false"/>
+        <property key="opt-xc8-linker-serial" value=""/>
+        <property key="program-the-device-with-default-config-words" value="true"/>
+      </HI-TECH-LINK>
+      <PICkit2PlatformTool>
+        <property key="pk2settings.3state" value="false"/>
+        <property key="pk2settings.preserveee" value="false"/>
+        <property key="pk2settings.setvddvoltage" value=""/>
+        <property key="pk2settings.userpgmexec" value="true"/>
+        <property key="pk2settings.usetargetpower" value="false"/>
+      </PICkit2PlatformTool>
+      <XC8-config-global>
+        <property key="output-file-format" value="-mcof,+elf"/>
+      </XC8-config-global>
+    </conf>
+  </confs>
+</configurationDescriptor>

diff --git a/nbproject/private/SuppressibleMessageMemo.properties b/nbproject/private/SuppressibleMessageMemo.properties
new file mode 100644 (file)
index 0000000..2642ff7
--- /dev/null
+++ b/nbproject/private/SuppressibleMessageMemo.properties
@@ -0,0 +1,21 @@
+#
+#Fri May 31 09:59:58 BST 2013
+mdbDebugger/MEMORY_VIEW_LAST_HW_BP_RESOURCE_WARN=false
+pkobskde/CHECK_4_HIGH_VOLTAGE_VPP=false
+pk3/DEVID_MISMATCH=false
+mdbDebugger/NO_HW_BP_RESOURCES_WARN=false
+mdbDebugger/MEMORY_VIEW_NO_HW_BP_RESOURCES_WARN=false
+pk3/CHECK_CLOCK=false
+mdbDebugger/LAST_HW_BP_RESOURCE_WARN=false
+pk3/CHECK_4_HIGH_VOLTAGE_VPP=false
+icd3/DEVID_MISMATCH=false
+realice/DEVID_MISMATCH=false
+realice/CHECK_CLOCK=false
+pkoblicdbgr/DEVID_MISMATCH=false
+pkoblicdbgr/CHECK_CLOCK=false
+pkobskde/DEVID_MISMATCH=false
+icd3/CHECK_CLOCK=false
+realice/CHECK_4_HIGH_VOLTAGE_VPP=false
+pkoblicdbgr/CHECK_4_HIGH_VOLTAGE_VPP=false
+icd3/CHECK_4_HIGH_VOLTAGE_VPP=false
+pkobskde/CHECK_CLOCK=false

diff --git a/nbproject/private/configurations.xml b/nbproject/private/configurations.xml
new file mode 100644 (file)
index 0000000..33325c8
--- /dev/null
+++ b/nbproject/private/configurations.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<configurationDescriptor version="62">
+  <projectmakefile>Makefile</projectmakefile>
+  <defaultConf>0</defaultConf>
+  <confs>
+    <conf name="XC8_12F1840" type="2">
+      <platformToolSN></platformToolSN>
+      <languageToolchainDir>/opt/microchip/xc8/v1.12/bin</languageToolchainDir>
+      <mdbdebugger version="1">
+        <placeholder1>place holder 1</placeholder1>
+        <placeholder2>place holder 2</placeholder2>
+      </mdbdebugger>
+      <runprofile version="6">
+        <args></args>
+        <rundir></rundir>
+        <buildfirst>true</buildfirst>
+        <console-type>0</console-type>
+        <terminal-type>0</terminal-type>
+        <remove-instrumentation>0</remove-instrumentation>
+        <environment>
+        </environment>
+      </runprofile>
+    </conf>
+    <conf name="XC8_12F1822" type="2">
+      <platformToolSN></platformToolSN>
+      <languageToolchainDir>/opt/microchip/xc8/v1.12/bin</languageToolchainDir>
+      <mdbdebugger version="1">
+        <placeholder1>place holder 1</placeholder1>
+        <placeholder2>place holder 2</placeholder2>
+      </mdbdebugger>
+      <runprofile version="6">
+        <args></args>
+        <rundir></rundir>
+        <buildfirst>true</buildfirst>
+        <console-type>0</console-type>
+        <terminal-type>0</terminal-type>
+        <remove-instrumentation>0</remove-instrumentation>
+        <environment>
+        </environment>
+      </runprofile>
+    </conf>
+  </confs>
+</configurationDescriptor>

diff --git a/nbproject/private/private.xml b/nbproject/private/private.xml
new file mode 100644 (file)
index 0000000..91a0c05
--- /dev/null
+++ b/nbproject/private/private.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?><project-private xmlns="http://www.netbeans.org/ns/project-private/1">
+    <editor-bookmarks xmlns="http://www.netbeans.org/ns/editor-bookmarks/1"/>
+    <open-files xmlns="http://www.netbeans.org/ns/projectui-open-files/1">
+        <file>file:/home/justin/MPLABXProjects/uart%20test.X/main.c</file>
+        <file>file:/home/justin/MPLABXProjects/uart%20test.X/user.c</file>
+        <file>file:/home/justin/MPLABXProjects/uart%20test.X/onewire.c</file>
+        <file>file:/home/justin/MPLABXProjects/uart%20test.X/interrupts.c</file>
+        <file>file:/home/justin/MPLABXProjects/uart%20test.X/user.h</file>
+    </open-files>
+</project-private>

diff --git a/nbproject/project.properties b/nbproject/project.properties
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/nbproject/project.xml b/nbproject/project.xml
new file mode 100644 (file)
index 0000000..7a889da
--- /dev/null
+++ b/nbproject/project.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?><project xmlns="http://www.netbeans.org/ns/project/1">
+    <type>com.microchip.mplab.nbide.embedded.makeproject</type>
+    <configuration>
+        <data xmlns="http://www.netbeans.org/ns/make-project/1">
+            <name>uart test</name>
+            <creation-uuid>fd17e5a7-f9b6-4f8e-a0b1-1d020538f498</creation-uuid>
+            <make-project-type>0</make-project-type>
+            <c-extensions>c</c-extensions>
+            <cpp-extensions/>
+            <header-extensions>h</header-extensions>
+            <sourceEncoding>ISO-8859-1</sourceEncoding>
+            <make-dep-projects/>
+        </data>
+    </configuration>
+</project>

diff --git a/onewire.c b/onewire.c
new file mode 100644 (file)
index 0000000..2b55f9e
--- /dev/null
+++ b/onewire.c
@@ -0,0 +1,416 @@
+/* Dallas 1-Wire bus routines */
+
+#if defined(__XC)
+    #include <xc.h>         /* XC8 General Include File */
+#elif defined(HI_TECH_C)
+    #include <htc.h>        /* HiTech General Include File */
+#endif
+
+#include <stdint.h>         /* For uint8_t definition */
+#include <stdbool.h>        /* For true/false definition */
+
+#include "system.h"
+#include "user.h"
+#include "onewire.h"
+
+// fast way, macros
+#define OWLOW { PORTAbits.RA5 = 0; TRISAbits.TRISA5 = 0; }
+#define OWHIGH { PORTAbits.RA5 = 1; TRISAbits.TRISA5 = 0; }
+#define OWTRI { TRISAbits.TRISA5 = 1; }
+#define OWREAD (PORTAbits.RA5)
+
+
+// slow way, causes a function call
+inline void drive_OW_low(void)
+{
+    PORTAbits.RA5 = 0;
+    TRISAbits.TRISA5 = 0;
+}
+
+inline void drive_OW_high(void)
+{
+    PORTAbits.RA5 = 1;
+    TRISAbits.TRISA5 = 0;
+}
+
+inline void float_OW(void)
+{
+    TRISAbits.TRISA5 = 1;
+}
+
+inline bool read_OW(void)
+{
+    TRISAbits.TRISA5 = 1;
+    return PORTAbits.RA5;
+}
+
+
+/* start the 1-Wire bus
+ *
+ */
+void OW_start(void)
+{
+    //drive_OW_high();
+    float_OW();
+}
+
+/* reset the bus, test for presence signal */
+bool OW_reset(void)
+{
+    bool presence = 0;
+
+    OWLOW; //drive_OW_low();
+    DelayUs(250);
+    DelayUs(250);
+    OWTRI; //float_OW(); // let it float high
+    DelayUs(70);
+    presence = OWREAD; //read_OW(); // now sample
+    DelayUs(215);
+    DelayUs(215);
+    
+    return ! presence;
+}
+
+void OW_write_bit(bool val)
+{
+#if 0  // Maxim dev note 2420
+    drive_OW_low();
+    DelayUs(3);
+    if (val) float_OW();
+    DelayUs(60);
+    float_OW();
+    DelayUs(2);
+#else
+    OWLOW;
+    NOP();
+    NOP();
+//    NOP();  // doc one for other delays
+    if (val) OWTRI;
+    DelayUs(60);
+    OWTRI;
+    NOP();
+    NOP();
+#endif
+}
+
+bool OW_read_bit()
+{
+    bool val;
+#if 0  /* Maxim dev note 2420 */
+    drive_OW_low();
+    DelayUs(6);
+    float_OW();
+    DelayUs(4);
+    val = read_OW();
+    DelayUs(50);
+#else
+    OWLOW;
+//    NOP();
+    NOP();
+    NOP();
+    NOP();
+    NOP();
+    NOP();
+    OWTRI;
+//    NOP();
+    NOP();
+    NOP();
+    NOP();
+    val = read_OW();
+    DelayUs(50);
+    
+#endif
+    return val;
+}
+
+void OW_write_byte(unsigned char byte)
+{
+    for (char i=8; i!=0; i--)
+    {
+        OW_write_bit( byte & 0x01 );
+        byte >>= 1;
+    }
+}
+
+unsigned char OW_read_byte(void)
+{
+    unsigned char byte = 0;
+    for (char i=8; i!=0; i--)
+    {
+        byte >>= 1;
+        if (OW_read_bit())
+            byte |= 0x80;
+
+    }
+    return byte;
+}
+
+static const unsigned char dscrc_table[] = {
+     0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65,
+      157,195, 33,127,252,162, 64, 30, 95,  1,227,189, 62, 96,130,220,
+       35,125,159,193, 66, 28,254,160,225,191, 93,  3,128,222, 60, 98,
+      190,224,  2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255,
+       70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89,  7,
+      219,133,103, 57,186,228,  6, 88, 25, 71,165,251,120, 38,196,154,
+      101, 59,217,135,  4, 90,184,230,167,249, 27, 69,198,152,122, 36,
+      248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91,  5,231,185,
+      140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205,
+       17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80,
+      175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238,
+       50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115,
+      202,148,118, 40,171,245, 23, 73,  8, 86,180,234,105, 55,213,139,
+       87,  9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22,
+      233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168,
+      116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53
+};
+
+unsigned char romid[8];
+char LastDiscrepancy = 0;
+char LastFamilyDiscrepancy = 0;
+char LastDeviceFlag = false;
+unsigned char crc8;
+
+static unsigned char docrc8(unsigned char value)
+{
+    crc8 = dscrc_table[crc8 ^ value];
+    return crc8;
+}
+
+/* enumerate the devices */
+bool OW_search()
+{
+    char id_bit_number = 1;
+    char last_zero = 0;
+    char rom_byte_number = 0;
+    char search_result = 0;
+    unsigned char rom_byte_mask = 1;
+    unsigned char search_direction;
+
+    crc8 = 0;
+
+    // do not interrupt us
+    int_disable();
+
+    // if the last call was not the last one
+    if (!LastDeviceFlag) {
+        if (!OW_reset())
+        {
+            msg_write("Reset said nothing there.\r\n");
+            // reset the search
+            LastDiscrepancy = 0;
+            LastDeviceFlag = 0;
+            LastFamilyDiscrepancy = 0;
+            int_enable();
+            return 0;
+        }
+
+        // issue the search command
+        OW_write_byte(0xF0);
+
+        // loop to do the search
+        do {
+            // read a bit and its complement
+            bool id_bit = OW_read_bit();
+            DelayUs(6);
+            bool cmp_id_bit = OW_read_bit();
+
+            // check for no devices on bus
+            if (id_bit && cmp_id_bit) {
+                break;
+            }
+
+            if (id_bit != cmp_id_bit) {
+                // all devices have a 0 here, or they all have a 1
+                search_direction = id_bit;
+            } else {
+                // both bits zero, so both 0 and 1 exist
+
+                // if this discrepancy is before the Last Discrepancy
+                // on a previous next then pick the same as last time
+                if (id_bit_number < LastDiscrepancy) {
+                    search_direction = ((romid[rom_byte_number] & rom_byte_mask) > 0);
+                } else {
+                    // if equal to last pick 1, if not then pick 0
+                    search_direction = (id_bit_number == LastDiscrepancy);
+                }
+
+                // if 0 was picked then record its position in LastZero
+                if (search_direction == 0)
+                {
+                    last_zero = id_bit_number;
+                    // check for last discrepancy in family
+                    if (last_zero < 9)
+                        LastFamilyDiscrepancy = last_zero;
+                }
+            }
+
+            // set or clear the bit in the ROM byte rom_byte_number
+            // with mask rom_byte_mask
+            if (search_direction == 1)
+                romid[rom_byte_number] |= rom_byte_mask;
+            else
+                romid[rom_byte_number] &= ~rom_byte_mask;
+
+            // serial number search direction write bit
+            OW_write_bit(search_direction);
+
+            // increment the byte counter id_bit_number
+            // and shift the mask rom_byte_mask
+            id_bit_number++;
+            rom_byte_mask <<= 1;
+
+            // if the mask is 0 then go to new SerialNum byte rom_byte_number and reset mask
+            if (rom_byte_mask == 0)
+            {
+                docrc8(romid[rom_byte_number]); // accumulate the CRC
+                rom_byte_number++;
+                rom_byte_mask = 1;
+            }
+        } while (rom_byte_number < 8); // loop until all rom bytes 0-7
+    } // end of not-last-device
+
+    // if the search was succesful then
+    if (!(id_bit_number < 65 || crc8 != 0))
+    {
+        // search successful
+        LastDiscrepancy = last_zero;
+
+        // check for last device
+        if (LastDiscrepancy == 0)
+            LastDeviceFlag = true;
+
+        search_result = true;
+    }
+
+    if (!search_result || !romid[0])
+    {
+        LastDiscrepancy = 0;
+        LastDeviceFlag = false;
+        LastFamilyDiscrepancy = 0;
+        search_result = false;
+    }
+
+    int_enable();
+    return search_result;
+}
+
+
+void OW_search_init()
+{
+    LastDiscrepancy = 0;
+    LastDeviceFlag = false;
+    LastFamilyDiscrepancy = 0;
+
+    for (int j=0; j<8; j++) romid[j]=0;
+}
+
+
+/* ask the (lone) device for its Serial number */
+void OW_identify()
+{
+    int_disable();
+    OW_reset();
+    // read ROM command
+    OW_write_byte(0x33);
+    for (int j=0; j<8; j++)
+        romid[j] = OW_read_byte();
+    int_enable();
+}
+
+/* is anyone parasite powered ? */
+bool OW_parasite(void)
+{
+    int_disable();
+    OW_reset();
+    OW_write_byte(0xCC); // skip the rom command
+    OW_write_byte(0xB4); // are you parasite powered ?
+    bool no = OW_read_bit();
+    int_enable();
+    return !no;
+}
+
+/* select a specific device,
+ * if family==0 select all devices (skip rom)
+ */
+static void OW_select_id(void)
+{
+    if (romid[0] == 0) {
+        OW_write_byte(0xCC); // all devices for now
+    } else {
+        OW_write_byte(0x55); // match rom
+        for (int8_t j=0; j<8; j++) {
+            OW_write_byte(romid[j]);
+        }
+    }
+}
+
+
+/* read a memory block eg scratchpad 0xBE */
+void OW_read_block(uint8_t code, uint8_t * data, uint8_t len)
+{
+    int_disable();
+    OW_reset();
+    OW_select_id();
+    OW_write_byte(code);
+    for (int8_t j=0; j<len; j++)
+        data[j] = OW_read_byte();
+    int_enable();
+}
+
+/* write a memory block to device, eg scratchpad 0x4E */
+void OW_write_block(uint8_t code, uint8_t * data, uint8_t len)
+{
+    int_disable();
+    OW_reset();
+    OW_select_id();
+    OW_write_byte(code);
+    for (int8_t j=0; j<len; j++) {
+        OW_write_byte(data[j]);
+    }
+    int_enable();
+}
+
+
+// perform temperature conversion
+void OW_convert()
+{
+    // first see if anyone is parasitic
+    bool para = OW_parasite();
+
+    int_disable();
+    OW_reset(); // all command start with reset
+    OW_select_id();
+    //OW_write_byte(0xCC); // all devices
+    OW_write_byte(0x44); // convert
+    if (para) {
+        // hard high for 750mS
+        OWHIGH;
+        DelayUs(250000);
+        DelayUs(250000);
+        DelayUs(250000);
+        DelayUs(250000);
+    } else {
+        // keep polling until its done
+        // device will reply with 0 'pull low' whilst convert in progress
+        do {
+            DelayUs(1000);
+        } while (!OW_read_bit());
+    }
+    int_enable();
+}
+
+/* Available commands :-
+ * 33h - read rom  (sends 8 bytes)
+ * 55h - match rom (reads 8 bytes)
+ * F0h - search rom (enumeration mode)
+ * ECh - alarm search
+ * CC  - skip rom command
+ *
+ * followed by....
+ * 44h - convert temperature
+ * 48h - copy scratchpad -> eeprom
+ * 4Eh - write scratchpad (send 3 bytes )
+ * BEh - read scratchpad ( 8 bytes + crc)
+ * B8h - recall EEPROM -> scratchpad
+ * B4h - read power supply (read 1 bit)
+ */
\ No newline at end of file

diff --git a/onewire.h b/onewire.h
new file mode 100644 (file)
index 0000000..578ae24
--- /dev/null
+++ b/onewire.h
@@ -0,0 +1,35 @@
+/* 
+ * File:   onewire.h
+ * Author: justin
+ *
+ * Created on 31 May 2013, 14:45
+ */
+
+#ifndef ONEWIRE_H
+#define        ONEWIRE_H
+
+bool OW_reset(void);
+void OW_write_bit(bool val);
+bool OW_read_bit();
+void OW_write_byte(unsigned char byte);
+unsigned char OW_read_byte(void);
+
+void OW_search_init();
+bool OW_search(void);
+void OW_start(void);
+
+void OW_identify();
+bool OW_parasite(void);
+void OW_read_block(uint8_t code, uint8_t * data, uint8_t len);
+void OW_convert();
+
+/* these were private, but needed for debug */
+inline void drive_OW_low(void);
+inline void drive_OW_high(void);
+inline void float_OW(void);
+inline bool read_OW(void);
+
+extern unsigned char romid[8];
+
+#endif /* ONEWIRE_H */
+

diff --git a/project_information.txt b/project_information.txt
new file mode 100644 (file)
index 0000000..39279db
--- /dev/null
+++ b/project_information.txt
@@ -0,0 +1,51 @@
+<Application Description for Project Goes Here>
+
+Project Owner(s):
+Author(s):
+Hardware Platform:
+Debuggers Used:
+Programmers Used:
+MPLAB Version:
+C Compiler Version:
+Final Checksum:
+
+FILES INCLUDED IN THE PROJECT TREE:
+
+system.h - Contains custom oscillator configuration function prototypes,
+reset source evaluation function prototypes, and non-peripheral
+microcontroller initialization function prototypes.  It also may contain
+system level #define macros and variables.  This file is included
+by system.c
+
+user.h - Contains parameters and function prototypes used in user.c for user
+level functions, for example, InitApp();
+
+configuration_bits.c - Contains device configuration bit macros.  Refer to
+the comments in configuration_bits.c for instructions on where to get
+information about device configuration bits and their corresponding macros.
+
+interrupts.c - This file contains example stubs for interrupts.  The user would
+put the interrupt vectors for their application in interrupts.c.
+
+main.c - This is the main code for the project.  global variables and the
+main() function are located in main.c  The user would put their primary program
+flow in main.c, and the operation should be contained in main.c with an
+infinite loop.
+
+system.c - Contains custom oscillator configuration functions, reset source
+evaluation functions, and non-peripheral microcontroller initialization
+functions.  Functions in system.c would often be called from main.c during
+device initialization.
+
+user.c - Custom user algorithms, user peripheral initialization, data
+computation functions, and calculation functions would go here.  Prototypes for
+user.c go in user.h.
+
+FILES INCLUDED IN THE PROJECT BUT NOT IN THE PROJECT TREE:
+
+#include <htc.h>             /* Global Header File */
+#include <stdint.h>          /* For uint8_t definition */
+#include <stdbool.h>         /* For true/false definition */
+
+These files come with the HiTech compiler.  Check the compiler documentation for
+more information on these files.

diff --git a/readtemp.sh b/readtemp.sh
new file mode 100755 (executable)
index 0000000..596a710
--- /dev/null
+++ b/readtemp.sh
@@ -0,0 +1,71 @@
+#!/bin/bash
+
+DEV=/dev/ttyUSB0
+TIMEOUT=5
+LOCK=/var/tmp/readtemp.lock
+
+SYSDEV=/sys/bus/usb/devices
+for i in $SYSDEV/*
+do
+if [ -f "$i/interface" ]
+then
+       if grep -q "CP2102 USB to UART" "$i/interface"
+       then
+               DEV=/dev/$(basename `ls -d $i/ttyUSB* `)
+               # dont break here, keep going so we get the last one
+               # break
+       fi
+fi
+done
+
+if ! lockfile -r 3 -l 5 $LOCK
+then
+echo "Failed to obtain lock"
+exit;
+fi
+
+if ! stty --file=$DEV | grep -q 'speed 19200'
+then
+stty --file=$DEV 19200
+sleep 1
+fi
+
+if ! stty --file=$DEV | grep -q '-echo'
+then
+stty --file=$DEV -echo
+sleep 1
+fi
+
+echo -n "t" >> $DEV
+
+MODE=plain
+if [ $# -ge 1 ] && [ "$1" == "-c" ]; then
+MODE=cacti
+fi
+
+while read -t $TIMEOUT -u 3 CODE ID TEM OTH; do
+# last one
+       if [ "$CODE" == "END" ]; then 
+               break;
+       fi
+
+# not a valid line
+       if [ "$CODE" != "TEMP" ]; then
+               echo "ERROR CODE=$CODE ID=$ID TEM=$TEM"
+               continue;
+       fi
+
+# truncate for paranoia
+       TEM=${TEM:0:4}
+
+# calculate degrees from the hex code
+       DEGC=`echo "16 i $TEM A i 4 k 0.0625 * p" | dc`
+# display the result
+if [ $MODE == "cacti" ]; then
+       printf "id:%s temp:%s\n", "$ID" "$DEGC"
+else
+       printf "%s %s degC\n" "$ID" "$DEGC";
+fi
+done 3< $DEV
+
+rm -f $LOCK

diff --git a/serial.c b/serial.c
new file mode 100644 (file)
index 0000000..2f9779b
--- /dev/null
+++ b/serial.c
@@ -0,0 +1,153 @@
+/***
+ *** Serial Port driver for 12f1840 and kin
+ ***/
+
+#include "user.h"
+#include "system.h"
+
+#include <stdint.h>
+#include <stdbool.h>
+
+
+/* outgoing text buffer */
+char outbuff[100];
+char * outp = 0;
+uint8_t outlen = 0;
+
+/* incoming text buffer */
+char inbuff[10];
+uint8_t inlen = 0;
+
+
+void serial_init(void)
+{
+    /* Enabling transmitter 26.1.1.1 page 259 - TX/CK I/O pin */
+    TXSTAbits.TXEN = 1;
+    TXSTAbits.SYNC = 0;
+    RCSTAbits.SPEN = 1;
+    /* Enabling receiver 26.1.2 page 262 - RX/DT I/O pin */
+    RCSTAbits.CREN = 1;
+
+    /* Select pins 4&5 as the uart - page 102 */
+    APFCONbits.RXDTSEL = 1; /* RX/DT on RA5 */
+    APFCONbits.TXCKSEL = 1; /* TX/CK on RA4 */
+    TRISAbits.TRISA5 = 1;   /* RA5 as input  */
+    TRISAbits.TRISA4 = 0;   /* RA4 as output */
+
+    ANSELAbits.ANSA4 = 0; /* no analog */
+
+#if _XTAL_FREQ != 4000000L
+#error "Adjust serial port baudrate settings"
+#endif
+    
+    /* assume 4MHz clock, 19k2 baud */
+    TXSTAbits.BRGH = 0;
+    BAUDCONbits.BRG16 = 1;
+    SPBRG = 12;
+
+    /* Enable interrupts */
+    INTCONbits.GIE = 1;
+    INTCONbits.PEIE = 1;
+
+    /* enable uart receiver interupt */
+    PIE1bits.RCIE = 1;
+}
+
+
+/* is the queue empty yet */
+bool msg_empty(void)
+{
+    if (outp == 0) return 1;
+    return 0;
+}
+
+/* new message in the queue */
+void msg_write(const char *msg)
+{
+    char * p = outbuff + outlen;
+    while (outlen < sizeof(outbuff) && *msg != 0) {
+        *(p++) = *(msg++);
+        outlen++;
+    }
+    *p = 0;
+    if (outp == 0) {
+        outp = outbuff;
+        PIE1bits.TXIE = 1;
+    }
+}
+
+void msg_writebyte(const char msg)
+{
+    if (outlen+1 >= (uint8_t)sizeof(outbuff)) return;
+    outbuff[outlen++] = msg;
+    outbuff[outlen] = 0;
+    if (outp == 0) {
+        outp = outbuff;
+        PIE1bits.TXIE = 1;
+    }
+}
+
+void putch(char data)
+{
+    msg_writebyte(data);
+}
+
+/* called from interrupt routine to send next char */
+void msg_sendnext(void)
+{
+    /* we have finished, turn off the iterrupt */
+    if (outp == 0 || *outp == 0) {
+        PIE1bits.TXIE = 0;
+        outp = 0;
+        outlen = 0;
+        return;
+    }
+    TXREG = *outp;
+    outp++;
+}
+
+/* called from interrupt routine to receive next byte */
+void msg_recvnext(void)
+{
+    while (PIR1bits.RCIF) {
+        bool err = RCSTAbits.FERR;
+        char new = RCREG;
+
+        /* bad char, skip it */
+        if (err) continue;
+
+        /* our input buffer has overflowed */
+        if (inlen > sizeof(inbuff)) return;
+
+        /* keep this one */
+        inbuff[inlen++] = new;
+    }
+}
+
+bool msg_recvready(void)
+{
+    if (inlen > 0) return 1;
+    return 0;
+}
+
+char msg_recv(void)
+{
+    if (inlen == 0) return 0;
+
+    /* record and disable the interupt */
+    bool in = PIE1bits.RCIE;
+    PIE1bits.RCIE = 0;
+
+    char new = inbuff[0];
+    inlen--;
+
+    /* shuffle them down one */
+    for (char i=0;i<inlen;i++)
+        inbuff[i] = inbuff[i+1];
+
+    /* restore the interupt */
+    PIE1bits.RCIE = in;
+    return new;
+}
+
+

diff --git a/serial.h b/serial.h
new file mode 100644 (file)
index 0000000..53ed384
--- /dev/null
+++ b/serial.h
@@ -0,0 +1,37 @@
+/* 
+ * File:   serial.h
+ * Author: justin
+ *
+ * Created on 17 June 2013, 16:08
+ */
+
+#ifndef SERIAL_H
+#define        SERIAL_H
+
+extern char outbuff[];
+char inbuff[];
+
+void serial_init(void);
+
+bool msg_empty(void);
+void msg_write(const char *msg);
+void msg_writebyte(const char msg);
+void msg_sendnext(void);
+
+void msg_recvnext(void);
+bool msg_recvready(void);
+char msg_recv(void);
+void putch(char);
+
+/* TODO Connect serial interupt handlers
+ *
+ *  if (PIE1bits.TXIE && PIR1bits.TXIF)
+ *      msg_sendnext();
+ *
+ *  if (PIE1bits.RCIE && PIR1bits.RCIF)
+ *      msg_recvnext();
+ *
+ */
+
+#endif /* SERIAL_H */
+

diff --git a/system.c b/system.c
new file mode 100644 (file)
index 0000000..6956ace
--- /dev/null
+++ b/system.c
@@ -0,0 +1,26 @@
+/******************************************************************************/
+/* Files to Include                                                           */
+/******************************************************************************/
+
+#if defined(__XC)
+    #include <xc.h>         /* XC8 General Include File */
+#elif defined(HI_TECH_C)
+    #include <htc.h>        /* HiTech General Include File */
+#endif
+
+#include <stdint.h>        /* For uint8_t definition */
+#include <stdbool.h>       /* For true/false definition */
+
+#include "system.h"
+
+/* Refer to the device datasheet for information about available
+oscillator configurations and to compiler documentation for macro details. */
+void ConfigureOscillator(void)
+{
+
+    /* configure 4MHz mode */
+    OSCCONbits.SPLLEN = 0;
+    OSCCONbits.IRCF = 0b1101;
+    OSCCONbits.SCS = 0b00;
+
+}

diff --git a/system.h b/system.h
new file mode 100644 (file)
index 0000000..22fed9d
--- /dev/null
+++ b/system.h
@@ -0,0 +1,31 @@
+/******************************************************************************/
+/* System Level #define Macros                                                */
+/******************************************************************************/
+
+/* TODO Define system operating frequency */
+
+/* Microcontroller MIPs (FCY) */
+#define XTAL_MHZ        4
+#define _XTAL_FREQ      4000000L
+#define SYS_FREQ        4000000L
+#define FCY             SYS_FREQ/4
+
+#include <pic12f1840.h>
+
+/******************************************************************************/
+/* System Function Prototypes                                                 */
+/******************************************************************************/
+
+
+#if _XTAL_FREQ == 4000000L
+#define DelayUs(x) _delay(x)
+#else
+#define DelayUs(x) __delay_us(x)
+#warning "This is slow"
+#endif
+
+/* Custom oscillator configuration funtions, reset source evaluation
+functions, and other non-peripheral microcontroller initialization functions
+go here. */
+
+void ConfigureOscillator(void); /* Handles clock switching/osc initialization */

diff --git a/user.c b/user.c
new file mode 100644 (file)
index 0000000..3ba4692
--- /dev/null
+++ b/user.c
@@ -0,0 +1,80 @@
+/******************************************************************************/
+/* Files to Include                                                           */
+/******************************************************************************/
+
+#if defined(__XC)
+    #include <xc.h>         /* XC8 General Include File */
+#elif defined(HI_TECH_C)
+    #include <htc.h>        /* HiTech General Include File */
+#endif
+
+#include <stdint.h>         /* For uint8_t definition */
+#include <stdbool.h>        /* For true/false definition */
+
+#include "system.h"
+#include "user.h"
+
+/******************************************************************************/
+/* User Functions                                                             */
+/******************************************************************************/
+
+/* <Initialize variables in user.h and insert code for user algorithms.> */
+
+void InitApp(void)
+{
+    /* set watchdog to 4 seconds and enable it */
+    WDTCONbits.WDTPS = 0b01100;
+    WDTCONbits.SWDTEN = 1;
+   
+    /* Select pins 4&5 as the uart - page 102 */
+    APFCONbits.RXDTSEL = 0; /* RX/DT on RA1 */
+    APFCONbits.TXCKSEL = 0; /* TX/CK on RA0 */
+    TRISAbits.TRISA1 = 1;   /* RA5 as input  */
+    TRISAbits.TRISA0 = 0;   /* RA4 as output */
+
+    ANSELA = 0; /* no analog */
+
+
+    /* enable weak pullups, clear them all */
+    WPUA = 0;
+    //WPUAbits.WPUA0 = 0x00000100; // RA0 pullup for 1-wire bus
+    OPTION_REGbits.nWPUEN = 1;
+
+    /* Enabling transmitter 26.1.1.1 page 259 - TX/CK I/O pin */
+    TXSTAbits.TXEN = 1;
+    TXSTAbits.SYNC = 0;
+    RCSTAbits.SPEN = 1;
+    /* Enabling receiver 26.1.2 page 262 - RX/DT I/O pin */
+    RCSTAbits.CREN = 1;
+
+    /* 4MHz clock, 57k6 baud */
+    TXSTAbits.BRGH = 1;
+    BAUDCONbits.BRG16 = 1;
+    //SPBRG = 16; // 57k6
+    SPBRG = 51; // 19k2
+    //SPBRG = 103; // 9k6
+
+    // enable debug LED on RA4
+    TRISAbits.TRISA4 = 0;
+    ANSELAbits.ANSA4 = 0;
+
+    // setup timer1
+
+    // enable the timer (off for now, not gated mode)
+    T1CONbits.TMR1ON = 0;
+    T1GCONbits.TMR1GE = 0;
+    T1CONbits.TMR1CS = 0b00; // instruction clock
+    T1CONbits.T1CKPS = 0b11; // div 8
+    
+
+    // enable TIMER1 interupt
+    PIE1bits.TMR1IE = 1;
+
+    /* Enable interrupts */
+    INTCONbits.GIE = 1;
+    INTCONbits.PEIE = 1;
+
+    /* enable uart receiver interupt */
+    PIE1bits.RCIE = 1;
+}
+

diff --git a/user.h b/user.h
new file mode 100644 (file)
index 0000000..58ae5db
--- /dev/null
+++ b/user.h
@@ -0,0 +1,28 @@
+/******************************************************************************/
+/* User Level #define Macros                                                  */
+/******************************************************************************/
+
+/* TODO Application specific user parameters used in user.c may go here */
+
+/******************************************************************************/
+/* User Function Prototypes                                                   */
+/******************************************************************************/
+
+/* TODO User level functions prototypes (i.e. InitApp) go here */
+
+void InitApp(void);         /* I/O and Peripheral Initialization */
+bool msg_empty(void);
+void msg_write(const char *msg);
+void msg_writebyte(const char msg);
+void msg_sendnext(void);
+void tohex(char val[3], uint8_t i);
+void msg_recvnext(void);
+bool msg_recvready(void);
+char msg_recv(void);
+void putch(char);
+
+void int_disable(void);
+void int_enable(void);
+
+void timer_rollover(void);
+